KR20000043619A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device fabricating method is provided to prevent a bold effect by forming a lower electrode of a capacitor with Si1-xGex. CONSTITUTION: In a semiconductor device fabricating method, an oxide film(22) as an interlayer insulation film is formed on a semiconductor substrate(20) in which an impurity region(21) is formed. A contact hole is formed by etching the interlayer insulation layer to expose the impurity region. A polysilicon layer is deposited on the resultant structure, and the polysilicon layer is etched back to form a plug(23) connected to the impurity region. A Si1-xGex layer is formed on the exposed plug(23) and interlayer insulation film(22) by use of reactive gases of SiH4 and G3H4. A temperature of forming the Si1-xGex layer is maintained below a crystallization temperature. A hemispherical lower electrode(240) is formed on the Si1-xGex layer(24).

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a semiconductor having a hemispherical protrusion of a capacitor formed of Si _1-x Ge _x to prevent a bold effect and to omit an additional doping process, etc. A method for manufacturing a capacitor lower electrode of an apparatus.

Many studies have been conducted to increase the storage density so that the capacitor has a constant storage capacity even if the cell area is reduced due to the high integration of the semiconductor device. In order to increase the capacitance, the capacitor was formed into a stacked or trenched three-dimensional structure to increase the surface area of the dielectric.

In the DRAM manufacturing process, transistors and the like are formed on a semiconductor substrate to form a cell portion, and then a storage electrode and a plate electrode are formed of a plurality of polysilicon layers, and a dielectric film is interposed therebetween to form a capacitor. The metal wiring process is performed.

As described above, in order to increase the effective area for securing the capacitance of the capacitor in the limited area of the cell of the memory device, there is the following conventional technology.

First, the surface of the storage electrode, which is the lower electrode of the capacitor, is formed in a rugged morphology, thereby increasing the area of the capacitor that can not be limited in terms of design rules and structure. As a representative example, first, a box-shaped storage electrode is formed, and then a plurality of hemispherical silica grains (hereinafter referred to as HSG) are formed on the surface thereof, thereby increasing the surface area of the storage electrode.

Second, the dielectric film is formed of a material having a high dielectric constant to increase the capacitance of the capacitor. In this case, materials used as the dielectric film include Ta ₂ O ₅ , BST, and the like.

The HSG forming process is extremely dependent on the crystallization temperature and the doping concentration of the lower electrode forming silicon layer. In the prior art, the conductive layer for forming the lower electrode node is lower than the crystallization temperature of silicon using SiH ₄ and PH 3. Deposited. When the crystallization temperature is 560-580 ° C., since crystal nuclei exist in the silicon layer to be deposited, a silicon layer is easily crystallized in a subsequent process without an incubation time.

Therefore, the deposition temperature of the preferred silicon layer is 500-530 ° C, and this temperature range is a region where temperature dependence is maximized, subject to surface reactions and reactions in limited regions. In other words, the deposition rate is drastically reduced so that a large deposition time is required to obtain a predetermined deposition thickness.

The silicon layer thus deposited must be sufficiently doped in order to serve as a lower electrode, otherwise depletion may occur, which causes a reduction in capacitance depending on an applied voltage.

Also, the incubation time for the crystallization of the silicon layer tends to decrease with the increase of P ions, which are dopants. Therefore, in order to prevent such depletion and the like, a process of removing a natural oxide film formed on the surface after HSG formation and an impurity ion implantation process are further performed.

1A to 1C are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the prior art.

Referring to FIG. 1A, an impurity region 11 used as a source and a drain region by being doped with N-type impurities such as acenic or phosphorus (P) on a silicon substrate 10, which is a P-type semiconductor substrate, is heavily doped. ) Is formed.

The oxide film 12 is formed on the semiconductor substrate 10 by an interlayer insulating layer by chemical vapor deposition (hereinafter referred to as CVD).

Next, a photolithography process using a photoresist is performed on the interlayer insulating layer 12 to form contact holes for exposing the surface of the impurity region 11.

In order to form a plug for the storage electrode to sufficiently fill the contact hole, a polysilicon layer doped with an impurity is deposited on the interlayer insulating layer 12 by CVD to expose the surface of the interlayer insulating layer 12. It etches back to fill the contact hole and form a plug 13 electrically contacted with the impurity region 11.

Next, an amorphous silicon layer 14 is formed by depositing SiH ₄ and PH ₃ as a reactant on the interlayer insulating layer 12 including the exposed plug 13 surface.

At this time, since the silicon layer 14 to be formed is not able to lower the deposition temperature unconditionally, since it is formed between 510 and 530 ° C., the silicon layer 14 is not completely amorphous and has crystal nuclei partially, and this part is partially crystallized in a subsequent process. Therefore, HSG grains are not formed at the crystallized site in the HSG formation process and have a smooth surface compared to the surroundings, which is called a bold effect.

Then, it takes about 24 hours to form such a silicon layer 14 to a thickness of 8000 kPa at 510 占 폚. Generally, when depositing polysilicon, it takes about 6 hours to form the same thickness.

Referring to FIG. 1B, the bottom electrode 140 is patterned by dry etching the silicon layer by photolithography. In this case, the shape of the lower electrode 140 may be patterned into various shapes such as a box shape, a crown shape, a cylinder shape, or a pin shape.

In addition, an HSG process using a selective SiH ₄ gas is performed on the exposed bottom electrode 140 to form a hemispherical protrusion 15 to increase the surface area of the bottom electrode 140. As a result, the lower electrode 140 and the protrusion 15 become the final lower electrodes 140 and 15. In this case, the hemispherical protrusion 15 is formed by flowing SiH ₄ gas on the exposed surface of the lower electrode 140.

Then, in order to prevent the depletion phenomenon, if necessary, after removing the natural oxide film formed on the lower electrode surface, additional impurity ion implantation is performed on the lower electrode 140 and the protrusion 15. This is advantageous in terms of HSG formation, the longer the incubation time for crystallization, and the longer the incubation time, the more doping is necessary because the deposition temperature of the silicon layer 14 must be low or the doping concentration is low.

Referring to FIG. 1C, a dielectric film 16 is formed by depositing Ta ₂ O ₅ having excellent dielectric constant on the surfaces of the final lower electrodes 140 and 15, and then performing a post-treatment process on the dielectric film 16 in an oxygen atmosphere. This improves the characteristics of the dielectric film 16. This is to form a molecular formula consisting of Ta ₂ O ₅ to obtain the dielectric constant value of the ideal dielectric film since the dielectric film 16 is generally composed of Ta ₂ O _5-x .

A capacitor is manufactured by depositing a TiN layer 17 on the surface of the dielectric film 16 to form a metal plate electrode as an upper electrode.

However, the capacitor manufacturing method according to the prior art described above does not meet the increase in capacitance because the formation of HSG grains is not dense due to the bold effect, and thus does not correspond to the increase in capacitance, and thus requires a subsequent doping process. The process is complicated.

Accordingly, an object of the present invention is to form a lower electrode having a hemispherical protrusion of a capacitor as Si _1-x Ge _x to prevent a bold effect and to omit a natural oxide removal process and an additional doping process. The present invention provides a method of manufacturing a capacitor lower electrode.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a Si _1-x Ge _x layer on a semiconductor substrate by using a reactive gas including silicon and a reactive gas including germanium; Patterning the _1-x Ge _x layer into a predetermined shape, and forming a plurality of hemispherical protrusions in silicon on the exposed surface of the patterned Si _1-x Ge _x layer.

In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor device according to the present invention includes plugging a Si _1-x Ge _x layer patterned on an insulating film formed by exposing an upper surface of a conductive plug to a predetermined portion of a semiconductor substrate at or below a crystallization temperature. forming so as to cover the exposed surface of the exposed Si _1-x Ge _x and forming a plurality of semi-spherical protrusions as silicon on the layer surface, and the exposed Si _1-x Ge _x layer surface and a plurality of hemispherical protrusions Forming a dielectric film on the surface, and forming an upper electrode on the dielectric film.

1A to 1C are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the prior art.

2A to 2C are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

3a to 3b are graphs of deposition rates of SiGe with temperature versus Ge content, respectively

4A to 4B are graphs showing deposition rates of SiGe with increasing Ge content at specific temperatures, respectively.

The present invention forms the lower electrode on which HSG is formed of Si _1-x Ge _x using germanium instead of silicon. Ge is a group 4 element, such as silicon, an atom that has fully solid solubility at the silicon site. When GeH ₄ is introduced simultaneously when depositing a silicon layer using SiH ₄ , Ge is substituted on the silicon site to form Si _1-x Ge _x .

This deposition rate increases rapidly as the Ge amount (x) increases, and when x is 0.4, the deposition rate increases more than 10 times under the same temperature.

In addition, even in the case of impurity activation efficiency, Ge is superior to silicon, so that the lower electrode can be formed to suppress the depletion even when the impurity is lowered and deposited.

3A to 3B are graphs of deposition rates of Si _1-x Ge _x according to temperature with respect to Ge content, respectively.

Referring to Figure 3a, the horizontal coordinate axis represents the temperature and the vertical axis represents the deposition rate (Å / min). The three straight lines are shown from the top to the bottom in order of decreasing partial pressure of GeH ₄ and increasing activation energy due to the substitution of Ge. At this time, the silicon source gas is SiH ₂ Cl ₂ .

Therefore, it can be seen that the activation energy decreases as the substitution of Ge increases, and the decrease of the activation energy is less dependent on temperature, which is a factor that makes the Si _1-x Ge _x layer deposited uniform.

Referring to FIG. 3B, the horizontal coordinate axis represents temperature and the vertical coordinate axis represents deposition rate (min / min). The three straight lines are shown from the top to the bottom in order of decreasing partial pressure of GeH ₄ and increasing activation energy due to the substitution of Ge. At this time, the silicon source gas is SiH ₄ .

It can also be seen that the activation energy decreases as the substitution of Ge increases, and the decrease of the activation energy is a small dependence on temperature, which causes the deposited Si _1-x Ge _x layer to be uniform.

4A to 4B are graphs of deposition rates of SiGe with increasing Ge content at specific temperatures, respectively.

Referring to FIG. 4A, the horizontal coordinate axis represents the concentration of Ge in the Si _1-x Ge _x layer to be formed and the vertical axis represents the deposition rate (Å / min). Three straight lines represent Si ₂ H ₆ , SiH ₄ , and SiH ₂ Cl ₂ from top to bottom, respectively, wherein the process conditions are 625 ° C. and 760 Torr pressure.

Referring to FIG. 4B, the horizontal coordinate axis represents the concentration of Ge in the Si _1-x Ge _x layer to be formed, and the vertical axis represents the deposition rate (Å / min). The three straight lines represent Si ₂ H ₆ , SiH ₄ , and SiH ₂ Cl ₂ from top to bottom, respectively, wherein the process conditions are 700 ° C. and 760 Torr pressure.

4A to 4B show the deposition rate change of the Si _1-x Ge _x layer as the amount of Ge increases. For all source gases containing Si, the deposition rate increases as the amount of Ge increases and the x value is 0.4. In the degree of deposition, the deposition rate is increased about 10 times compared to the case where the x value is zero.

Si ₂ H ₆ may be used as a method for lowering the deposition temperature and increasing the deposition rate of the silicon layer on which the HSG is to be formed. However, compared with the case of using SiH ₄ , it has similar results with respect to the concentration of doping impurities and is disadvantageous with respect to contaminant generation, step coverage, uniformity, and deposition rate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

Referring to FIG. 2A, an impurity region 21 used as a source and a drain region by being doped with N-type impurities such as an asic (As) or phosphorus (P) at a high concentration on a silicon substrate 20, which is a P-type semiconductor substrate. ) Is formed.

The oxide film 22 is formed on the semiconductor substrate 20 by an interlayer insulating layer by chemical vapor deposition (hereinafter referred to as CVD).

Next, a photolithography process using a photoresist is performed on the interlayer insulating layer 22 to form contact holes for exposing the surface of the impurity region 21.

Then, a polysilicon layer doped with an impurity is formed on the interlayer insulating layer 22 by CVD to form a plug for the storage electrode to sufficiently fill the contact hole, and then expose the surface of the interlayer insulating layer 22. It etches back to fill the contact hole and form a plug 23 electrically contacting the impurity region 21.

Next, a Si _1-x Ge _x layer 24 is formed by depositing SiH ₄ and GeH ₄ as a reactant on the interlayer insulating layer 22 including the exposed plug 23 surface. At this time, the formation temperature of the Si _1-x Ge _x layer 24 is less than or equal to the crystallization temperature, the deposition rate is reduced by about 10 times or more as compared to the conventional.

In order to effectively form HSG forming hemispherical protrusions, the lower the deposition temperature of silicon or the lower the doping concentration, the longer the incubation time of crystallization, but it is difficult in terms of deposition rate and depletion.

However, in the present invention, since the Si _1-x Ge _x layer 24 is formed, the deposition rate problem can be solved to lower the deposition temperature, and the bold effect can be prevented by extending the crystallization incubation time.

In addition, when the same amount of dopant is present in the silicon layer and the Si _1-x Ge _x layer 24, the dopant activation efficiency of the Si _1-x Ge _x layer 24 is excellent, thus affecting HSG formation. Depletion can be sufficiently prevented in a concentration range that is not known (generally 2E20 atoms / cm 3). Therefore, no additional doping process is required to secure the conductivity of the lower electrode.

Referring to FIG. 2B, the bottom electrode 240 is patterned by dry etching the Si _1-x Ge _x layer 24 by photolithography. In this case, the shape of the lower electrode 240 may be patterned into various shapes such as a box shape, a crown shape, a cylinder shape, or a pin shape.

Then, an HSG process using a selective SiH ₄ gas is performed on the exposed lower electrode 240 to form a hemispherical protrusion 25 to increase the surface area of the lower electrode 240. As a result, the lower electrode 240 and the protrusion 25 become the final lower electrodes 240 and 25. At this time, the hemispherical protrusion 25 is formed by flowing SiH ₄ gas on the exposed surface of the lower electrode 240, and is formed more densely because the bold effect is eliminated as compared to the prior art, thereby increasing the surface area of the lower electrode. To increase the capacitance.

Referring to FIG. 2C, a dielectric film 26 is formed by depositing Ta ₂ O ₅ having excellent dielectric constant on the surfaces of the final lower electrodes 240 and 25, and then performing a post-treatment process on the dielectric film 26 in an oxygen atmosphere. By improving the characteristics of the dielectric film 26. This is to form a molecular formula consisting of Ta ₂ O ₅ in order to obtain the dielectric constant value of the ideal dielectric film since the dielectric film 26 is generally composed of Ta ₂ O _5-x .

A capacitor is manufactured by depositing a TiN layer 27 on the surface of the dielectric film 26 to form a metal plate electrode as an upper electrode.

Therefore, the capacitor manufacturing method according to the present invention forms a Si _1-x Ge _x layer can solve the deposition rate problem to lower the deposition temperature, prolong the crystallization incubation time can prevent the bold effect to further increase the HSG It is densely formed to increase the capacitance of the capacitor by increasing the surface area of the lower electrode, and also has the advantage of simplifying the process because it can prevent the depletion phenomenon without additional doping process.

Claims (10)

Forming a Si _1-x Ge _x layer on the semiconductor substrate by using a reactor comprising silicon and a reactor comprising germanium; Patterning the Si _1-x Ge _x layer into a predetermined shape; Forming a plurality of hemispherical protrusions of silicon on the exposed surface of the patterned Si _1-x Ge _x layer. The method of claim 1, wherein the Si _1-x Ge _x layer and the protrusion are formed to have conductivity. The method of claim 1, wherein the protrusion is formed of hemispherical silicon grains. The method of claim 1, wherein the Si _1-x Ge _x layer is formed at or below a crystallization temperature. The method of claim 1, wherein after forming the protrusion, Forming a dielectric film on the exposed Si _1-x Ge _x layer and the surface of the protrusion, And forming a conductive layer on the dielectric film. The method of claim 1, wherein the x value of the Si _1-x Ge _x layer is about 0.4. Forming a patterned Si _1-x Ge _x layer on the insulating film formed by exposing the upper surface of the conductive plug to a predetermined portion of the semiconductor substrate so as to cover the exposed surface of the plug below a crystallization temperature; Forming a plurality of hemispherical protrusions from silicon on the exposed Si _1-x Ge _x layer surface, Forming a dielectric film on the exposed Si _1-x Ge _x layer surface and a plurality of the hemispherical protrusion surfaces; Forming a top electrode on the dielectric film. The method of claim 7, wherein the Si _1-x Ge _x layer and the protrusion are formed to have conductivity. The method of claim 7, wherein the protrusion is formed of hemispherical silicon grains. 8. The method of claim 7, wherein an x value of the Si _1-x Ge _x layer is about 0.4.