KR20050001601A - fabrication Method of poly-TFT - Google Patents

Abstract

PURPOSE: A method of manufacturing a polycrystalline TFT(Thin Film Transistor) and the polycrystalline TFT thereby are provided to simplify manufacturing processes by performing simultaneously a crystallizing process on an active layer and an activating process on an ohmic contact layer. CONSTITUTION: A gate electrode, a gate insulating layer, an undoped amorphous silicon layer and a doped amorphous silicon layer are sequentially formed on a first substrate. An island-type structure composed of an active layer(210) and an ohmic contact layer(212) is formed by etching selectively the doped and undoped amorphous silicon layers. By irradiating laser beams on the active layer and the ohmic contact layer, a lateral crystallization is performed on the active layer and an activation is performed on the ohmic contact layer as well. An interlayer dielectric is formed thereon.

Description

Manufacturing method of polycrystalline thin film transistor {fabrication Method of poly-TFT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline thin film transistor for a liquid crystal display device, and to a method for manufacturing an inverted staggered type poly-TFT.

In general, the liquid crystal display device is an apparatus for displaying an image by controlling the amount of light emitted downward to the outside through the liquid crystal by using the arrangement characteristics of the liquid crystal that changes when the intensity of the electric field distribution is changed.

Hereinafter, a configuration of a general liquid crystal display device will be described with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

As shown, the liquid crystal panel 11, which is a liquid crystal display device display unit, is divided into an array substrate B1 and a color filter substrate B2, and the array substrate B1 crosses vertically on the transparent insulating substrate 22. The data line 13 and the gate line 15 defining the pixel area P are configured, and the thin film transistor T is positioned at the intersection of the two lines 13 and 15, that is, one side of the single pixel P. Each pixel P is configured with a transparent pixel electrode 17.

The color filter substrate B1 has a black matrix 6 having a larger area corresponding to the thin film transistor T formed on the array substrate on one surface of the transparent insulating substrate 5 and the gate wirings and the data wirings 13 and 15. ) Is configured.

Between the black matrices 6, red, green, and blue color filters 8a, 8b, and 8c correspond to the pixel electrodes 17 of the array substrate B2 in a predetermined order.

A transparent common electrode 18 is formed on the entire surface of the substrate 5 including the black matrix 6 and the color filters 8a, 8b, and 8c.

In the above-described configuration, the thin film transistor T receives a signal from the gate wiring 13 and the data wiring 15, and the signal of the data wiring 15 is changed according to the signal of the gate wiring 13. The thin film transistor T is transferred to the pixel electrode 17 through the thin film transistor T.

Therefore, the liquid crystals 30 located between the array substrate B2 and the color filter substrate B1 are arranged by the electric field generated between the pixel electrode 17 and the common electrode 18, and the arrangement of the liquid crystals is arranged. As a result, light is transmitted and results in displaying an image.

In the above-described configuration, the thin film transistor may optionally use a polycrystalline thin film transistor and an amorphous thin film transistor.

2 is a cross-sectional view showing the configuration of an amorphous thin film transistor having a general inverted staggered type TFT structure.

As shown, the reverse staggered thin film transistor deposits and patterns a low resistance metal such as aluminum on the transparent insulating substrate 30 to form the gate electrode 32.

The gate insulating layer 34 formed by depositing silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) is formed on the gate electrode 32.

The active layer 36 and the ohmic contact layer 38 are sequentially stacked on the gate insulating layer 34 to correspond to the gate electrode 32.

The source electrode 40 and the drain electrode 42 are spaced apart from each other on the ohmic contact layer 38, and the active layer 36 is exposed in the space between the source and drain electrodes 40 and 42. It serves as an active channel (CH).

As described above, the reverse staggered thin film transistor is not very fast because it uses amorphous silicon having an unstable lattice structure as the active layer.

However, a thin film transistor that requires fast operation as a display device has a larger size is required. For this purpose, the active layer is formed of crystalline silicon.

Coplanar type polycrystalline thin film transistors are generally known as such crystalline thin film transistors.

3 is a cross-sectional view schematically illustrating a configuration of a general coplanar polycrystalline thin film transistor.

As shown, the coplanar polycrystalline thin film transistor is formed of polycrystalline silicon 52 patterned generally in an island shape on the insulating substrate 50.

The patterned polycrystalline silicon 52 may be defined as a first active region A1 and a second active region A2 on both sides of the first active region A1.

A gate insulating film 54 composed of silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 50 including the patterned polycrystalline silicon 52.

A gate electrode 56 is formed of a low resistance metal such as aluminum (Al) in a portion of the gate insulating layer 54 corresponding to the first active region A1 of the patterned polycrystalline silicon 52.

An interlayer insulating layer 58 in which the above-mentioned silicon nitride (SiN _X ) or silicon oxide (SIO ₂ ) is deposited is formed on the entire surface of the substrate 50 including the gate electrode 56. A source electrode 60 and a drain electrode 62 respectively contacting the second active region A2 exposed by etching the lower gate insulating layer 54 are formed on the interlayer insulating layer 58.

In the above configuration, the first active region A1 corresponding to the gate electrode 56 serves as the active channel CH.

In the above-described configuration, the patterned polycrystalline silicon layer 52 is to deposit amorphous silicon and then crystallize it through a high temperature or low temperature process to form crystalline silicon.

In addition, after the gate electrode 56 is formed, a process of forming an ohmic contact layer by doping impurity ions (n-type or p-type impurities) in the second active region A2 is necessary. In addition, a process of recovering defects occurring in the second active region A2 during the ion doping through the activation process after the doping process must also be performed.

Therefore, the coplanar polycrystalline thin film transistor has a faster operation of the device than the inverted staggered amorphous thin film transistor, but has a complicated process.

The present invention has been proposed to solve the above-described problem, the present invention proposes a method for manufacturing an inverted sterilized polycrystalline thin film transistor, this inverted sterilized polycrystalline thin film transistor is a conventional coplanar polycrystalline thin film transistor In contrast, the activation process can be performed simultaneously while crystallizing the active pattern, which has the advantage of simplifying the process.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device;

2 is a cross-sectional view showing the configuration of an amorphous thin film transistor,

3 is a cross-sectional view showing the configuration of a polycrystalline thin film transistor,

4 is a plan view schematically showing the configuration of a mask used in the lateral growth crystallization method,

5 is a plan view schematically showing the shape of crystals grown on side crystals,

6A to 6F are cross-sectional views illustrating a process of manufacturing a polycrystalline thin film transistor according to the present invention, in accordance with a process sequence.

<Description of Symbols for Major Parts of Drawings>

210: active layer 212: ohmic contact layer

SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-mentioned problems, and the polycrystalline thin film transistor according to the present invention comprises a gate electrode formed on a substrate; A gate insulating film formed on the gate electrode; A polycrystalline active layer on the gate insulating film on the gate electrode, the polycrystalline active layer comprising crystal grains in which portions corresponding to the gate electrodes are laterally grown; A polycrystalline ohmic contact layer disposed on the polycrystalline active layer and spaced apart from each other by a predetermined distance; And a source electrode and a drain electrode in contact with the ohmic contact layer and spaced apart from each other.

The ohmic contact layer is a crystal layer doped with n + or p + impurities.

A method of manufacturing a polycrystalline thin film transistor according to an aspect of the present invention includes forming a gate electrode on a first substrate; Stacking a gate insulating film, a pure amorphous silicon layer, and an amorphous silicon layer containing impurities on the entire surface of the substrate including the gate electrode; Etching the pure silicon layer and the amorphous silicon layer including impurities to form an active layer and an ohmic contact layer stacked in an island shape; Etching a portion of the ohmic contact layer corresponding to the gate electrode to expose a lower active layer; Irradiating laser on top of the active layer and the ohmic contact layer to laterally crystallize the exposed active layer and to activate the ohmic contact layer; Forming an interlayer insulating film on an entire surface of the substrate on which the crystallized active layer and the ohmic contact layer are formed; Etching the interlayer insulating film to form spaced apart first and second contact holes exposing the ohmic contact layer; Forming a source electrode and a drain electrode in contact with the exposed ohmic contact layer.

The gate insulating film and the interlayer insulating film are formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

The layer thickness of the active layer and the ohmic contact layer is 120 ~ 150nm, the thickness of the active layer exposed between the ohmic contact layer is characterized in that 50nm.

Inverse staggered polycrystalline thin film transistor according to the present invention can proceed simultaneously with the activation process while crystallizing the active pattern, there is an advantage to simplify the process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention is characterized in that the active pattern of the reverse staggered thin film transistor is laterally grown and crystallized at the same time.

Prior to describing the present invention, a lateral growth crystallization is outlined.

4 is a plan view schematically showing a mask required for lateral growth crystallization.

The lateral growth crystallization method necessarily requires a mask M, which is a shape in which the slit-shaped transmissive portion T and the reflecting portion R are alternately formed.

When the laser is irradiated to the lower amorphous film through the slit of the mask, the amorphous silicon corresponding to the slit is crystallized, the crystallized shape is as shown in Figure 5 below.

5 is a plan view showing the planar shape of the lateral growth crystallized crystal layer.

As shown, the portion of the amorphous preceding film 100 corresponding to the transmissive portion T of the mask (M in FIG. 4) becomes the crystal region CP and the portion corresponding to the blocking portion R is the amorphous region. (AP) will remain.

At this time, the grains 106a and 106b grown laterally in the opposite directions are present, and the lateral growth of the grains starts from the boundary between the crystal region CP and the amorphous region AP and is later grown two grains 106a. 106b) stops crystal growth as they meet.

In general, the lengths of the crystal grains 106a and 106b thus grown are slightly different depending on the intensity of the laser to be irradiated.

In addition, as described above, when crystallization is completed by the primary laser irradiation, crystallization may proceed continuously while moving the mask on the X axis, and in this way, it is possible to theoretically grow the crystal grains to a desired length.

Such lateral growth grains have the advantage that the movement speed of the grains is the same as the direction in which the carrier flows, so that the movement speed of the carriers is high.

Hereinafter, a method of manufacturing an inverted staggered type polycrystalline thin film transistor including an active pattern crystallized using the above principle will be described with reference to FIGS. 6A to 6F.

As shown in FIG. 6A, a low resistance metal including aluminum (Al) is deposited and patterned on the transparent insulating substrate 200 to form a gate electrode 202.

As shown in FIG. 6B, a gate insulating film 204, which is a first insulating film, an amorphous silicon layer 206, and an amorphous silicon layer 208 including impurities are formed on the entire surface of the substrate 200 on which the gate electrode 202 is formed. ) Are formed by sequentially laminating them.

In this case, the amorphous silicon layer 206 is formed to a thickness of about 30nm ~ 100nm, the ohmic contact layer 208 is formed of a thickness of about 50nm ~ 400nm.

In the above-described configuration, the first insulating layer 204 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), and the amorphous silicon layer 206 is Pure amorphous silicon (a-Si: H) is formed by depositing, and the impurity amorphous silicon layer 208 is formed by depositing amorphous silicon (n + a-SI: H) containing impurities.

After the etching of the impurity amorphous silicon layer 208 and the amorphous silicon layer 206 below, the process of removing a portion of the center region of the amorphous silicon layer is performed.

In this way, as shown in FIG. 6C, the active layer 210 and the ohmic contact layer 212 can be formed.

In this case, an area exposed between the ohmic contact layer 212 of the active layer 210 is called a first active area A1, and an area in which the ohmic contact layer 212 is present is called a second active area A2. Let's define

In this case, the thickness of the active layer 210 and the ohmic contact layer 212 corresponding to the second active region A2 is about 80 nm to 500 nm, and the active layer corresponding to the first active region A2 ( 210) is composed of a thickness of less than 50nm ~ 100nm.

Next, the laser is irradiated corresponding to the first active region A2 and the second active region A2.

At this time, although the laser is irradiated to the first and second active regions A1 and A2 with the same intensity, the thickness difference corresponding to the first active region A1 and the second active region A2 as described above. Because the crystallization energy is different.

In other words. The relatively thick second active region A2 needs more energy for crystallization.

Accordingly, the active layer 210 corresponding to the first active region A1 is completely melted by the laser irradiation, but the non-melting region is generated in the second active region.

Thus, as shown in FIG. 6D (FIG. 6D is an enlarged cross-sectional view of FIG. 6C.), These non-melted regions act as seeds, so that the first active region A1 and the second active region are seeded. Crystals grow laterally from both sides of the area A2.

That is, as described above with reference to FIGS. 4 and 5, the active layer corresponding to the first active region A1 is formed of a polycrystalline silicon thin film composed of large grains grown laterally.

In this case, the ohmic contact layer 212 and the active layer 210 corresponding to the second active region A2 are crystallized into smaller grains than the first active region and are activated at the same time, so that an additional activation process is not necessary.

Next, as illustrated in FIG. 6E, an interlayer insulating layer 214 is deposited by depositing silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) on the entire surface of the substrate 200 on which the polycrystalline active layer 210 is formed. ).

Next, the interlayer insulating layer 214 is patterned to form a first contact hole 216 and a second contact hole 218 exposing the ohmic contact layer 212 of the second active region V2, respectively.

As shown in FIG. 6F, a conductive metal including chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), and the like on the entire surface of the substrate 200 on which the interlayer insulating film is formed. A selected one of the group is deposited and patterned to form a source electrode 220 and a drain electrode 222 in contact with the exposed ohmic contact layer 212.

Through the process as described above, it is possible to manufacture an inverted sterilized polycrystalline thin film transistor according to the present invention.

Inverse staggered polycrystalline thin film transistor according to the method of the present invention as described above induces lateral crystallization using the thickness difference of the thin film during laser crystallization to form a channel region as a high quality crystal layer, thereby operating characteristics of the polycrystalline thin film transistor This has the effect of being improved.

Second, by simultaneously activating the ohmic contact layer doped with impurities during crystallization, there is an effect of improving the process yield since a separate activation process is not required as compared with the conventional method.

Claims (5)

A gate electrode constructed on the substrate; A gate insulating film formed on the gate electrode; A polycrystalline active layer on the gate insulating film on the gate electrode, the polycrystalline active layer comprising crystal grains in which portions corresponding to the gate electrodes are laterally grown; A polycrystalline ohmic contact layer disposed on the polycrystalline active layer and spaced apart from each other by a predetermined distance; Source and drain electrodes in contact with the ohmic contact layer and spaced apart from each other Polycrystalline thin film transistor comprising a. The method of claim 1, And the ohmic contact layer is a polycrystalline silicon layer doped with n + or p + impurities. Forming a gate electrode on the first substrate; Stacking a gate insulating film, a pure amorphous silicon layer, and an amorphous silicon layer containing impurities on the entire surface of the substrate including the gate electrode; Etching the pure silicon layer and the amorphous silicon layer including impurities to form an active layer and an ohmic contact layer stacked in an island shape; Etching a portion of the ohmic contact layer corresponding to the gate electrode to expose a lower active layer; Irradiating laser on top of the active layer and the ohmic contact layer to laterally crystallize the exposed active layer and to activate the ohmic contact layer; Forming an interlayer insulating film on an entire surface of the substrate on which the crystallized active layer and the ohmic contact layer are formed; Etching the interlayer insulating film to form spaced apart first and second contact holes exposing the ohmic contact layer; Forming a source electrode and a drain electrode in contact with the exposed ohmic contact layer Polycrystalline thin film transistor manufacturing method comprising a. The method of claim 3, wherein And the gate insulating film and the interlayer insulating film are formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 3, wherein Stacking thickness of the active layer and the ohmic contact layer is 80nm ~ 500nm, the thickness of the active layer exposed between the ohmic contact layer is 30nm ~ 100nm polycrystalline thin film transistor manufacturing method.