KR20050001512A - A Method for manufacturing of Bottom Gate type Thin Film Transistor Device - Google Patents

Abstract

PURPOSE: A method of manufacturing a bottom gate type TFT(Thin Film Transistor) device is provided to form a semiconductor layer made of an amorphous silicon layer without an additional photolithographic process by crystallizing selectively an amorphous silicon layer and performing etching thereon using the difference of etching rate between a crystallized silicon portion and an amorphous silicon portion. CONSTITUTION: A gate electrode, a gate insulating layer(116) and an amorphous silicon layer are sequentially formed on a substrate(110). A first region is defined in the amorphous silicon layer and a polysilicon layer(119) is formed by crystallizing selectively a surface of the first region. Etching is performed thereon by using the difference of etching rate between the polysilicon layer and the amorphous silicon layer until the polysilicon layer is completely removed therefrom, so that a stepped portion is formed between the amorphous silicon layer of the first region and the other amorphous silicon layer. A semiconductor layer made of the amorphous silicon layer of the first region is completed by performing over-etching on the resultant structure.

Description

A method for manufacturing of bottom gate type thin film transistor device

The present invention relates to a thin film transistor element. The thin film transistor element includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. In particular, in the present invention, the gate electrode is positioned at the lowermost layer, and the bottom layer is formed of an amorphous silicon (a-Si) material. gate type) A method for manufacturing an amorphous silicon thin film transistor device.

The thin film transistor element is mainly used as a switching element for a liquid crystal display device, and an active matrix type for turning on / off a voltage for each pixel that is a minimum unit for displaying a screen by the thin film transistor element. LCD displays are mainstream.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, inserting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. It is a device that expresses an image by the transmittance of light that varies depending on the movement of liquid crystal molecules by moving the liquid crystal molecules by an electric field.

FIG. 1 is a schematic perspective view of a general liquid crystal display, in which first and second substrates 10 and 30 are disposed to face each other, and a plurality of gate lines 12 intersecting each other on an inner surface of the first substrate 10. ) And the data wiring 14 are formed, and a thin film transistor T is formed at the intersection of the gate wiring 12 and the data wiring 14, and the intersection of the gate wiring 12 and the data wiring 14 is formed. The pixel electrode 16 is connected to the thin film transistor T in the pixel region P defined as the region.

The color filter layer 32 and the common electrode 34 are sequentially formed on the inner surface of the second substrate 30, and the liquid crystal layer 50 is disposed between the pixel electrode 16 and the common electrode 34. Intervened.

In addition, first and second polarizing plates 52 and 54 are disposed on the rear surfaces of the first and second substrates 10 and 30, respectively, and a backlight, which is a light source device for supplying light, is provided on the rear surface of the first polarizing plate 52. It is arranged.

In the liquid crystal display, the thin film transistor plays a switching role of controlling on / off of a voltage applied to the pixel electrode, and the thin film transistor plays a very important role in determining device characteristics of the liquid crystal display.

Hereinafter, a manufacturing process of a conventional thin film transistor element will be described, and a bottom gate type thin film transistor element having a gate electrode as a lower layer will be described as an example.

The bottom gate type thin film transistor device is the most widely used structure, and the interface between the gate insulating film and the amorphous silicon layer is not exposed to air, and the gate insulating film, the amorphous silicon film, and the impurity amorphous silicon film can be continuously deposited in the same chamber. Therefore, the electrical characteristics of the thin film transistor element are good and the process has a simple advantage.

2A through 2I are cross-sectional views illustrating a step of manufacturing a conventional bottom gate type amorphous silicon thin film transistor device.

FIG. 2A is a step of depositing a first metal material layer 72 on a substrate 70. FIG. 2B is a photolithography method using a photosensitive material on the first metal material layer 72. The first PR pattern 74 is formed.

Although not shown in detail in the drawings, the first PR pattern 74 may include applying a photoresist layer (PR), which is a photosensitive material, on the first metal material layer 72, and an open portion on the PR layer. And a mask, and then exposing the PR layer and developing the exposed PR layer.

FIG. 2C illustrates a process of etching a region of an exposed first metal material layer 72 using the first PR pattern 74 as a mask and stripping the first PR pattern 74. Step 76 forms.

FIG. 2D illustrates a step of continuously depositing the gate insulating layer 78, the pure amorphous silicon layer 80, and the impurity amorphous silicon layer 82 in a region covering the gate electrode 76, and FIG. 2E illustrates the impurity amorphous silicon. The second PR pattern 84 is formed at a position covering the gate electrode 76 on the layer 82. The second PR pattern 84 may be formed through the same process steps as the first PR pattern (74 in FIG. 2B).

FIG. 2F illustrates that the exposed impurity amorphous silicon layer 82 and the pure amorphous silicon layer 80 are etched using the second PR pattern 84 as a mask to correspond to the second PR pattern 84. In this step, the semiconductor layer 86 having a pattern structure is formed.

The semiconductor layer 86 may include an active layer 86a formed of an etched pure amorphous silicon layer 80 and an ohmic contact layer 86b formed of an etched impurity amorphous silicon layer 82. layer).

FIG. 2G illustrates a step of depositing a second metal material layer 88 in a region covering the semiconductor layer 86, and FIG. 2H illustrates a region covering a semiconductor layer 86 on the second metal material layer 88. The third PR pattern 90 may be formed to be spaced apart from each other at the center of the semiconductor layer 86.

FIG. 2I illustrates a source electrode 92 having a pattern structure corresponding to the third PR pattern 90 by etching an exposed region of the second metal material layer 88 using the third PR pattern 90 as a mask. ) And the drain electrode 94.

In this step, the ohmic contact layer 86b positioned in the section between the source electrode 92 and the drain electrode 94 is removed by using the source electrode 92 and the drain electrode 94 as a mask. Exposing the active layer 86a constituting the lower layer to configure the exposed active layer 86a as a channel (ch).

The gate electrode 76, the semiconductor layer 86, the source electrode 92, and the drain electrode 94 form a thin film transistor element T.

As described above, in the manufacturing process of the conventional bottom gate type amorphous silicon thin film transistor device, in particular, the patterning process of the semiconductor layer, the process number, process time, production cost, including the PR layer coating step, exposure step, development step There was a problem that the production yield is reduced due to the increase.

In order to solve this problem, it is an object of the present invention to provide a method for manufacturing a bottom gate type amorphous silicon thin film transistor device with a simplified process.

To this end, in the present invention, by partially crystallizing an upper portion of the amorphous silicon layer, by using a method of selectively etching the crystallized silicon region by using an etching rate difference between the silicon region in the crystallized state and the silicon region in the amorphous state, The photolithography process for the semiconductor layer is omitted.

1 is a schematic perspective view of a general liquid crystal display device.

2A to 2I are cross-sectional views illustrating a step of manufacturing a conventional bottom gate type amorphous silicon thin film transistor device.

3A to 3F are cross-sectional views showing step-by-step manufacturing processes of a bottom gate type amorphous silicon thin film transistor device according to a first embodiment of the present invention.

4A to 4C are drawings for the etching process principle of the semiconductor layer according to the present embodiment.

5 is a view showing a selective crystallization process of a semiconductor layer for a bottom gate type amorphous silicon thin film transistor device according to a second embodiment of the present invention.

6 is a schematic cross-sectional view of a liquid crystal display device including a bottom gate type amorphous silicon thin film transistor element according to a third exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

110 substrate 116 pure amorphous silicon layer

118 impurity amorphous silicon layer 119 polysilicon layer

d1: total thickness of the amorphous silicon layer

d2: thickness of the polysilicon layer

α: etching thickness difference between the polysilicon layer and the amorphous silicon layer

d'1: Total thickness of amorphous silicon layer on non-corresponding position of polysilicon layer

d'2: Overall thickness value of the amorphous silicon layer located under the polysilicon layer

In order to achieve the above object, in a first aspect of the present invention, there is provided a method of forming a gate electrode on a substrate; Sequentially forming a gate insulating film and an amorphous silicon layer in a region covering the gate electrode; Defining an amorphous silicon layer region covering the gate electrode as a first region, and selectively crystallizing a surface of the first region to form a polysilicon layer; Removing the polysilicon layer to form a step between the amorphous silicon layer and the other amorphous silicon layer of the first region by an etching condition in which the etching rate of the amorphous silicon layer is faster than that of the polysilicon layer; ; Overetching the amorphous silicon layer having the step to form an amorphous silicon layer patterned in the first region as a semiconductor layer; It provides a method of manufacturing a thin film transistor device comprising forming a source electrode and a drain electrode on the semiconductor layer.

In the forming of the amorphous silicon layer, a pure amorphous silicon layer and an impurity amorphous silicon layer are sequentially formed, and the semiconductor layer includes an active layer formed by etching the pure amorphous silicon layer and the impurity amorphous silicon. And an ohmic contact layer formed by etching the layer, wherein the impurity amorphous silicon layer has a thickness larger than that of the ohmic contact layer, and the polysilicon layer is formed on the surface layer of the impurity amorphous silicon layer. It is done.

The etching selectivity ratio of the polysilicon layer to the amorphous silicon layer is 0.6 to 0.8, wherein the selectively crystallizing is a crystallization step having an energy density capable of initially melting the amorphous silicon layer, wherein the crystallization step is It is characterized in that the crystallization step using the laser energy.

The selective crystallization step is made of the same material in the same step as the gate electrode, characterized in that made on the basis of the alignment key located in the periphery of the substrate.

According to a second aspect of the present invention, there is provided a thin film transistor formed according to the manufacturing method according to the first aspect, a first substrate having a pixel electrode connected to the thin film transistor; A second substrate disposed to face the first substrate and having a common electrode formed thereon; A liquid crystal display device including a liquid crystal layer interposed between the first and second substrates is provided.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment

3A to 3F are cross-sectional views illustrating step-by-step manufacturing processes of a bottom gate type amorphous silicon thin film transistor device according to a first embodiment of the present invention.

3A is a step of forming a gate electrode 112 by forming a first metal material on the substrate 110 and then performing a first mask process, which is a photolithography process.

The gate electrode 112 is selected from a metal material having a low specific resistance.

3B illustrates a step of sequentially depositing the gate insulating layer 114, the pure amorphous silicon layer 116, and the impurity amorphous silicon layer 118 in the region covering the gate electrode 112.

In this step, the impurity amorphous silicon layer 118 is formed to be thicker than the existing deposition thickness, because part of the surface layer is removed through a subsequent etching process.

3C illustrates a step of dehydrogenation of the impurity amorphous silicon layer 118, and selectively crystallization of the impurity amorphous silicon layer 118, so that a portion of the surface area of the impurity amorphous silicon layer 118 is removed. The silicon layer 119 is formed. The dehydrogenation step is a step of removing hydrogen atoms bonded to the impurity amorphous silicon layer 118. Unlike the conventional polysilicon crystallization method in which amorphous silicon must be completely dehydrogenated, dehydrogenation for crystallization with a short time and low temperature is required. Becomes possible.

In addition, the crystallization step corresponds to, for example, a crystallization step using laser energy, and laser irradiation in a low energy region only by surface crystallization is required. The energy density region for melting amorphous silicon can be divided into a partial melting area, a near complete melting area, and a complete melting area according to the energy density size. It can proceed using the energy density of an initial melting area | region.

3D is an etching step of completely removing the polysilicon layer 119. When the total thickness of the impurity amorphous silicon layer 118 and the pure amorphous silicon layer 116 is "d1" and the thickness of the polysilicon layer 119 is "d2", the polysilicon layer 119 is "d2". In the etching step of removing completely, the impurity amorphous silicon layer 118 and the pure amorphous silicon layer 116 are etched by " d2 "

Accordingly, the total thickness value d'2 of the impurity amorphous silicon layer 118 and the pure amorphous silicon layer 119 positioned below the polysilicon layer 119 after the etching process is determined by the other impurity amorphous silicon layer 118. And have a value larger than the total thickness value d'1 of the pure amorphous silicon layer 119, and thus have a step due to the difference in thickness values.

For example, the etching step may use a dry etching process.

3E illustrates that the semiconductor layer 120 is excessively etched by the impurity amorphous silicon layer 118 and the pure amorphous silicon layer 116 having stepped characteristics in a state where the polysilicon layer (119 of FIG. 3D) is removed. Forming.

3D and 3E may be continuously performed through one etching process, and the patterning process may be performed without using an additional mask process by using an etching rate difference between polysilicon and amorphous silicon.

In more detail, the amorphous silicon material has a coarser structure than the crystallized silicon material, and thus the etching speed is faster than that of the crystallized silicon layer. During etching, only a portion of the amorphous silicon region is etched, and if the etching process is continuously performed in consideration of overetching in this state, the semiconductor layer 120 made of the amorphous silicon material may be finally formed. .

Typically, the etching selectivity of the amorphous silicon material to the polysilicon material has a value of 0.6 to 0.8.

The semiconductor layer 120 includes an active layer 120a made of pure amorphous silicon material and an ohmic contact layer 120b made of impurity amorphous silicon material.

3F illustrates a source metal 122 and a drain spaced apart from each other on the semiconductor layer 120 by forming a second metal material in a region covering the semiconductor layer 120 and then performing a second mask process. The electrode 124 is formed.

In this step, the ohmic contact layer 120b positioned in the section between the source electrode 122 and the drain electrode 124 is removed using the source electrode 122 and the drain electrode 124 as a mask, and the lower layer thereof. Exposing the active layer 120a to form a channel (ch).

The gate electrode 112, the semiconductor layer 120, the source electrode 122, and the drain electrode 124 form a thin film transistor element T.

4A to 4C are views illustrating an etching process principle of a semiconductor layer according to the present embodiment.

4A is a step of depositing an amorphous silicon layer 132 on the substrate 130. In this step, the deposition thickness of the amorphous silicon layer 132 is defined as "d3".

4B is a step of selectively crystallizing only a central portion of the amorphous silicon layer 132 to form a polysilicon layer 134 in the central portion.

Next, FIG. 4C illustrates a step in which a polysilicon layer 134 having a thickness of “d4” is left on the substrate 130 by an etching condition process of completely removing the amorphous silicon layer 132. In this step, the polysilicon layer 134 is selectively left because the amorphous silicon layer 132 has a higher etching rate than the polysilicon layer 134.

When the etching selectivity between the amorphous silicon layer 132 and the polysilicon layer 134 is calculated,

(d3: thickness of amorphous silicon layer

d4: thickness of polysilicon layer after etching process

x: etching selectivity of amorphous silicon layer to polysilicon layer)

The relational expression of (1) is established. The etching selectivity required according to the thickness of the polysilicon layer 134 finally remaining when the next amorphous silicon layer 132 and the polysilicon layer 134 are etched using the relationship (1) is as follows.

a) for d3 = 1,500 ms and d4 = 500 ms, x = 0.67

b) x = 0.75 for d3 = 2,000 μs and d4 = 500 μs

c) x = 0.84 when d3 = 2,500 Hz, d4 = 400 Hz

d) when d3 = 1,500 ms, d4 = 300 ms

For example, the crystallization thickness of the amorphous silicon layer using the laser equipment is most stable in the range of 1,500 ~ 2,000 Å. Therefore, even when considering the excessive etching of the amorphous silicon layer it can be seen that the stable etching selectivity (x) has a condition of 0.6 ~ 0.8 can be processed.

As described above, the bottom gate type amorphous silicon thin film transistor device according to the present invention is a method of controlling an etching selectivity between an amorphous silicon layer and a polysilicon layer, and selectively crystallizing only the active region surface of the amorphous silicon layer, and crystallization. Forming an amorphous silicon layer having a step by etching conditions for completely removing the crystallized region by using an etching rate difference between the region and the amorphous region, and over-etching the amorphous silicon layer having the step by the thickness difference. And a semiconductor layer formed by the patterning method.

Second Embodiment

FIG. 5 is a view illustrating a selective crystallization process of a semiconductor layer for a bottom gate type amorphous silicon thin film transistor device according to a second embodiment of the present invention, and corresponds to a plan view of a substrate that has been subjected to the steps of FIGS. 3A to 3C.

As illustrated, a substrate 210 in which a first region II and a second region III forming a periphery of the first region II is defined is disposed. The first region II of the substrate 210 has gate electrodes 212 for each pixel region P, which is the smallest unit for implementing a screen, and a plurality of gate lines 214 are formed in the first direction. The alignment key 220 made of the same material is formed at the same corner of the second region III in the same step as the gate wiring 214.

The gate insulating layer 222 and the amorphous silicon layer 224 are sequentially formed in regions covering the plurality of gate lines 214 and the alignment key 220. Although not shown in detail in the drawing, the amorphous silicon layer 224 corresponds to a silicon layer including a pure amorphous silicon layer and an impurity amorphous silicon layer.

In addition, the third region IV positioned in the region covering the gate electrode 212 may be formed of a polysilicon layer 226. The polysilicon layer 226 is formed by a process of selectively crystallizing the amorphous silicon layer 224 based on the alignment key 220.

That is, in the present exemplary embodiment, the polysilicon layer 226 may be selectively formed in the third region IV based on the alignment key 220 formed in the gate wiring 214 forming step. .

For example, the first area II corresponds to the display area, the second area III corresponds to the non-display area, and the third area IV corresponds to the active area.

Third Embodiment

6 is a schematic cross-sectional view of a liquid crystal display including a bottom gate type amorphous silicon thin film transistor device according to a third embodiment of the present invention, and includes a thin film transistor device formed by a manufacturing process according to the first embodiment. Characterized in that.

As shown, the first and second substrates 310 and 330 are disposed to face each other, the gate electrode 312 is formed on the inner surface of the first substrate 310, and the region covering the gate electrode 312 is provided. A gate insulating film 314 is formed on the gate insulating film 314, and a semiconductor layer 316 having a structure in which the active layer 316a and the ohmic contact layer 316b are sequentially stacked is formed. The semiconductor layer 316 is selectively crystallized only on the surface area of the amorphous silicon layer, and is formed by an etching process using an etching rate difference between the polysilicon layer and the amorphous silicon layer without a separate photolithography process.

The source electrode 318 and the drain electrode 320 are formed on the semiconductor layer 316 so as to be spaced apart from each other, and the ohmic contact layer 316b is removed in the section between the source electrode 318 and the drain electrode 320. The channel portion ch defined as an area where the active layer 316a constituting the lower layer is exposed is located. The gate electrode 312, the semiconductor layer 316, the source electrode 318, and the drain electrode 320 form a thin film transistor T. A passivation layer 324 having a drain contact hole 322 for partially exposing the drain electrode 320 is formed in an area covering the thin film transistor T, and a drain contact hole 322 is formed on the passivation layer 324. The pixel electrode 326 connected to the drain electrode 320 is formed.

Although not shown in the drawings, a gate wiring is formed in the first direction by being connected to the gate electrode 312, and a data wiring is formed in the second direction by being connected with the source electrode 318.

The black matrix 332 is formed at a position corresponding to the thin film transistor T on the inner surface of the second substrate 330, and the color filter layer 334 is formed using the black matrix 332 as a color-specific boundary. The common electrode 336 is formed under the color filter layer 334.

The liquid crystal layer 350 is interposed between the pixel electrode 326 and the common electrode 336.

Although not shown in the drawings, first and second polarizers are positioned on the outer surfaces of the first and second substrates 310 and 330, and a backlight is disposed on the rear surface of the first polarizer.

The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention.

As described above, in the method of manufacturing the bottom gate type amorphous silicon thin film transistor device according to the present invention, a polysilicon layer is selectively formed on the surface region of the amorphous silicon layer, and has a step due to the difference in etching speed between the polysilicon and the amorphous silicon. After forming the amorphous silicon pattern and then over-etching, the semiconductor layer can be formed without a separate photolithography process, thereby improving production yield through process simplification and manufacturing cost reduction.

Claims (9)

Forming a gate electrode on the substrate; Sequentially forming a gate insulating film and an amorphous silicon layer in a region covering the gate electrode; Defining an amorphous silicon layer region covering the gate electrode as a first region, and selectively crystallizing a surface of the first region to form a polysilicon layer; Removing the polysilicon layer to form a step between the amorphous silicon layer and the other amorphous silicon layer of the first region by an etching condition in which the etching rate of the amorphous silicon layer is faster than that of the polysilicon layer; ; Overetching the amorphous silicon layer having the step to form an amorphous silicon layer patterned in the first region as a semiconductor layer; Forming a source electrode and a drain electrode on the semiconductor layer Method of manufacturing a thin film transistor element comprising a. The method of claim 1, In the forming of the amorphous silicon layer, a step of forming a pure amorphous silicon layer and an impurity amorphous silicon layer in order to produce a thin film transistor device. The method of claim 2, The semiconductor layer may include an active layer formed by etching the pure amorphous silicon layer, and an ohmic contact layer formed by etching the impurity amorphous silicon layer, wherein the impurity amorphous silicon layer has a thickness value of the ohmic contact layer. A method of manufacturing a thin film transistor element having a larger value. The method of claim 3, wherein And the polysilicon layer is formed on the surface layer of the impurity amorphous silicon layer. The method of claim 1, The etching selectivity of the polysilicon layer to the amorphous silicon layer is a method of manufacturing a thin film transistor device is 0.6 ~ 0.8. The method of claim 1, The selectively crystallizing may be a crystallization step having an energy density capable of initially melting the amorphous silicon layer. The method of claim 6, The crystallization step is a crystallization step using a laser energy manufacturing method of a thin film transistor element. The method of claim 1, The selective crystallization step is made of the same material in the same step as the gate electrode, a method of manufacturing a thin film transistor element based on the alignment key located in the periphery of the substrate. A thin film transistor formed according to the manufacturing method according to claim 1, and a first substrate having a pixel electrode connected to the thin film transistor; A second substrate disposed to face the first substrate and having a common electrode formed thereon; Liquid crystal layer interposed between the first and second substrates Liquid crystal display comprising a.