KR20050001190A - Method for forming isolation layer of semiconductor device - Google Patents

Method for forming isolation layer of semiconductor device Download PDF

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Publication number
KR20050001190A
KR20050001190A KR1020030042763A KR20030042763A KR20050001190A KR 20050001190 A KR20050001190 A KR 20050001190A KR 1020030042763 A KR1020030042763 A KR 1020030042763A KR 20030042763 A KR20030042763 A KR 20030042763A KR 20050001190 A KR20050001190 A KR 20050001190A
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South Korea
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nitride film
film
oxide film
nitride
cmp
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KR1020030042763A
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Korean (ko)
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곽상현
송필근
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주식회사 하이닉스반도체
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Publication of KR20050001190A publication Critical patent/KR20050001190A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to improve an electrical characteristic by reducing an EFH(effective fox height) variation without using high selectivity slurry in an STI(shallow trench isolation) process. CONSTITUTION: The first oxide layer(22), the first nitride layer, the second oxide layer and the second nitride layer are sequentially formed on a silicon substrate(21). The resultant structure is etched to form a trench(26) in a field region. An insulation oxide layer(27) is deposited on the resultant structure including the trench. The first CMP(chemical mechanical polishing) process is performed to polish the insulation oxide layer and a part of the second nitride layer. The remaining second nitride layer is removed by a wet etch process. The second CMP process is performed to polishing the second oxide layer and a part of the first nitride layer. The remaining first nitride layer is eliminated by a wet etch process.

Description

반도체 소자의 소자분리막 형성방법{METHOD FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는, STI(Shallow Trench Isolation) 공정을 통해 형성된 소자분리막에 생기는 EFH(Effective Fox Height) 편차를 줄임으로써 소자의 전기적 특성을 향상시키기위한 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to improve the electrical characteristics of the device by reducing the EFH (Effective Fox Height) variation in the device isolation film formed through a shallow trench isolation (STI) process. The present invention relates to a device isolation film forming method of a semiconductor device.

주지된 바와 같이, 최근의 반도체 소자는 소자들간의 전기적 분리를 위한 소자분리막을 STI 공정을 이용하여 형성하고 있다. 왜냐하면 기존의 로코스(LOCOS) 공정의 경우 소자분리막의 상단 가장자리에 새부리 형상의 버즈-빅(bird's-beak)이 발생되는 것으로 인해 액티브 영역의 크기를 감소시키게 되지만, 상기 STI 공정의 경우 작은 폭으로의 소자분리막 형성이 가능하여 액티브 영역의 크기를 확보할 수 있기 때문이다.As is well known, recent semiconductor devices have formed device isolation films for electrical separation between devices using an STI process. In the conventional LOCOS process, the size of the active region is reduced due to the occurrence of bird's-beak having a beak shape at the top edge of the device isolation layer, but in the case of the STI process, This is because the device isolation film can be formed to ensure the size of the active region.

종래의 반도체 소자의 소자분리막 형성방법에 대하여 도 1a 및 도 1d를 참조하여 간략하게 설명하면 다음과 같다.A method of forming a device isolation film of a conventional semiconductor device will be briefly described with reference to FIGS. 1A and 1D.

종래의 반도체 소자의 소자분리막 형성방법은, 도 1a에 도시된 바와 같이,먼저, 실리콘 기판(1) 상에 패드산화막(2)과 질화막(3)을 차례로 형성한 다음, 공지의 공정에 따라 상기 질화막(3)과 패드산화막(2)을 패터닝하여 필드 영역(미도시)에 해당하는 기판 부분을 노출시킨다. 그런다음, 노출된 기판 부분을 식각하여 소정 깊이의 트렌치(4)를 형성한다. 이 때, 상기 패드산화막(2)은 50 ~ 100 Å , 상기 질화막(3)은 800 ~ 1300 Å 두께로 증착시킨다.In the method of forming a device isolation film of a conventional semiconductor device, as shown in FIG. 1A, first, a pad oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1, and then, according to a known process. The nitride film 3 and the pad oxide film 2 are patterned to expose the substrate portion corresponding to the field region (not shown). The exposed substrate portions are then etched to form trenches 4 of predetermined depth. In this case, the pad oxide film 2 is deposited at a thickness of 50 to 100 GPa and the nitride film 3 is 800 to 1300 GPa.

그리고, 도 1b에 도시된 바와 같이, 상기 트렌치(4)를 매립하도록 상기 기판 결과물 상에 절연 산화막(5)을 증착 시킨다. 여기서, 상기 절연 산화막(5)은 CVD(Chemical Vapor Deposition) 방식으로 4000 ~ 8000 Å 두께로 증착시킨다.As shown in FIG. 1B, an insulating oxide film 5 is deposited on the substrate product to fill the trench 4. Here, the insulating oxide film 5 is deposited to a thickness of 4000 ~ 8000 Å by CVD (Chemical Vapor Deposition) method.

이어서, 도 1c에 도시된 바와 같이, 상기 질화막(3)이 노출될 때까지 절연 산화막(5)의 표면을 화학적기계연마(Chemical Mechanical Polishing : 이하, 씨엠피라 칭함) 한다.Subsequently, as shown in FIG. 1C, the surface of the insulating oxide film 5 is referred to as chemical mechanical polishing (hereinafter referred to as CMP) until the nitride film 3 is exposed.

도 1d에 도시된 바와 같이, 트렌치 형성을 위한 기판 식각시 식각 장벽으로 이용된 상기 질화막을 인산용액으로 습식 식각을 실시하여 제거하고, 이 결과로서, 트렌치형의 소자분리막(6)을 형성한다.As shown in FIG. 1D, the nitride film used as an etching barrier during the etching of the substrate for trench formation is removed by wet etching with a phosphate solution, and as a result, a trench type device isolation film 6 is formed.

그러나, 종래의 기술에서는 절연 산화막을 4000-8000Å 정도의 두께로 증착함에 따라 증착 후의 웨이퍼 내에 증착 두께의 편차가 400Å 정도 발생하고, 후속 씨엠피를 통해 절연 산화막 4000-8000Å 및 질화막 200Å 정도의 두께를 제거하게 되는데, 이 때, 제거되는 두께의 편차가 발생한다. 일반적으로 질화막을 연마 정지막으로 사용하기 때문에 씨엠피 후의 EFH 편차는 절연 산화막 증착 편차보다는 줄어들게 되지만, 200Å 정도의 두께 편차는 여전히 가지게 된다. 이러한 두께 편차로 인해 트랜지스터의 전기적 특성이 저하되는 문제점이 발생된다. 이를 해결하기 위해 최근들어 산화막과 질화막의 선택비를 높인 고선택비 슬러리(High Selective Slurry)를 사용하여 씨엠피 하는 방법을 이용하기도 하지만, 상기 고선택비 슬러리는 일반적인 씨엠피에 사용하는 슬러리에 비해 단가가 비싸고 산화막의 연마 속도가 현저히 낮으며 스크래치(Scratch)를 많이 발생시키는 문제점이 있다.However, in the prior art, as the insulating oxide film is deposited to a thickness of about 4000-8000 kPa, a variation in the deposition thickness occurs in the wafer after deposition, and the thickness of the insulating oxide 4000-8000 kPa and the nitride film 200 kPa is obtained through subsequent CMP. In this case, a deviation of the thickness to be removed occurs. In general, since the nitride film is used as the polishing stop film, the EFH variation after CMP is smaller than the insulation oxide deposition variation, but still has a thickness variation of about 200 μs. This thickness variation causes a problem that the electrical characteristics of the transistor are degraded. In order to solve this problem, a method of CMP using a high selectivity slurry, which has recently increased the selectivity of an oxide film and a nitride film, has been used. However, the high selectivity slurry is compared to a slurry used in general CMP. There is a problem that the unit cost is high, the polishing rate of the oxide film is significantly low, and a lot of scratches are generated.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, STI 공정시 고선택비 슬러리를 사용하지 않고, EFH 편차를 줄임으로써 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and does not use a high selectivity slurry during the STI process, the method of forming a device isolation layer of a semiconductor device that can improve the electrical characteristics of the device by reducing the EFH variation The purpose is to provide.

도 1a 내지 도 1d는 종래의 기술에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the related art.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정 단면도.2A to 2F are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

21 : 실리콘 기판 22 : 제1산화막21 silicon substrate 22 first oxide film

23 : 제1질화막 24 : 제2산화막23: first nitride film 24: second oxide film

25 : 제2질화막 26 : 트렌치25: second nitride film 26: trench

27 : 절연 산화막 28 : 소자분리막27: insulating oxide film 28: device isolation film

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 소자분리막 형성방법은, 실리콘 기판 상에 제1산화막, 제1질화막, 제2산화막 및 제2질화막을 차례로 형성하는 단계; 상기 결과물을 식각하여 필드 영역에 트렌치를 형성하는 단계; 상기 트렌치를 포함한 기판 전면에 절연 산화막을 증착하는 단계; 1차 씨엠피 하여 상기 절연 산화막과 상기 제2질화막 일부를 연마하는 단계; 상기 잔류된 제2질화막을 습식 식각으로 제거하는 단계; 2차 씨엠피 하여 상기 제2산화막과 상기 제1질화막 일부를 연마하는 단계; 및 상기 잔류된 제1질화막을 습식 식각으로 제거하는 단계를 포함한다.The device isolation film forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film on a silicon substrate; Etching the resultant to form trenches in the field region; Depositing an insulating oxide film on the entire surface of the substrate including the trench; Polishing the insulating oxide film and a portion of the second nitride film by primary CMP; Removing the remaining second nitride film by wet etching; Polishing the second oxide film and a portion of the first nitride film by secondary CMP; And removing the remaining first nitride film by wet etching.

여기서, 상기 제1질화막을 600 ~ 900 Å , 상기 제2산화막을 60 ~ 150 Å , 상기 제2질화막을 300 ~ 600 Å 두께로 증착한다. 그리고, 상기 1차 씨엠피 하는 단계는, 상기 제2질화막의 두께가 200 Å 정도 남을 때까지 연마한다. 또한, 상기 제1질화막 및 상기 제2질화막의 습식 식각시, 인산 용액으로 습식 식각한다.Here, the first nitride film 600 to 900 ~, the second oxide film 60 to 150 Å, the second nitride film 300 to 600 Å thickness is deposited. In the step of primary CMP, the second nitride film is polished until the thickness of the second nitride film remains about 200 mm 3. In addition, during the wet etching of the first nitride film and the second nitride film, wet etching is performed using a phosphoric acid solution.

본 발명에 따르면, 두 번의 씨엠피와 두 번의 질화막 식각을 통해 종래에 한 번의 씨엠피와 한번의 질화막 식각을 하는 것보다 EFH의 편차를 줄일 수 있다.According to the present invention, it is possible to reduce the variation of EFH through two CMPs and two nitride layer etchings than one CMP and one nitride layer conventionally.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 각 공정별 단면도이다.2A through 2F are cross-sectional views of respective processes for describing a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법은, 도 2a에 도시된 바와 같이, 먼저, 실리콘 기판(21) 상에 제1산화막(22), 제1질화막(23), 제2산화막(24) 및 제2질화막(25)을 차례로 형성한 다음, 공지의 공정에 따라 상기 제2질화막(25), 제2산화막(24), 제1질화막(23) 및 제1산화막(22)을 패터닝하여 필드 영역(미도시)에 해당하는 기판 부분을 노출시킨다. 그런 다음, 노출된 기판 부분을 식각하여 소정 깊이의 트렌치(26)를 형성한다. 이 때, 상기 제1산화막(22)은 50 ~ 100 Å 두께로 증착시키고, 상기 제1질화막(23)은 600 ~ 900 Å 두께로 증착시킨다. 그리고, 상기 제2산화막(24)은 60 ~ 150 Å 두께로 증착시키고, 상기 제2질화막(25)은 300 ~ 600 Å 두께로 증착시킨다.In the method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, first, a first oxide film 22, a first nitride film 23, and a second oxide film are formed on a silicon substrate 21. (24) and the second nitride film 25 are formed in this order, and then the second nitride film 25, the second oxide film 24, the first nitride film 23 and the first oxide film 22 are formed in accordance with a known process. Patterning is performed to expose portions of the substrate corresponding to field regions (not shown). The exposed substrate portions are then etched to form trenches 26 of predetermined depth. At this time, the first oxide film 22 is deposited to a thickness of 50 ~ 100 GPa, the first nitride film 23 is deposited to 600 ~ 900 Å thickness. The second oxide film 24 is deposited to a thickness of 60 to 150 GPa, and the second nitride film 25 is deposited to a thickness of 300 to 600 GPa.

다음으로, 도 2b에 도시된 바와 같이, 상기 트렌치(26)를 포함한 기판 전면에 절연 산화막(27)을 증착시킨다. 이 때, 상기 절연 산화막(27)은 CVD 방식으로 4000 ~ 8000 Å 두께로 증착시킨다.Next, as shown in FIG. 2B, an insulating oxide film 27 is deposited on the entire surface of the substrate including the trench 26. At this time, the insulating oxide film 27 is deposited to a thickness of 4000 ~ 8000 Å by CVD.

이어서, 도 2c에 도시된 바와 같이, 상기 절연 산화막(27) 및 상기 제2질화막(25)의 일부를 1차 씨엠피 한다. 여기서, 상기 제2질화막(25)의 두께가 200 Å 정도 남을 때까지 1차 씨엠피 한다. 이 때, EFH 편차는 종래의 공정처럼 200 Å 정도가 된다.Subsequently, as illustrated in FIG. 2C, portions of the insulating oxide layer 27 and the second nitride layer 25 are first CMP. Here, the first CMP is performed until the thickness of the second nitride layer 25 remains about 200 mm 3. At this time, the EFH deviation is about 200 Hz as in the conventional process.

그 다음, 도 2d에 도시된 바와 같이, 상기 잔류된 제2질화막을 습식 식각하여 제거한다. 이 때, 상기 제2질화막의 습식 식각시 인산 용액을 사용한다.Then, as shown in Figure 2d, the remaining second nitride film is removed by wet etching. At this time, a phosphoric acid solution is used during the wet etching of the second nitride film.

그리고, 도 2e에 도시된 바와 같이, 상기 제2산화막 및 상기 제1질화막(23)의 일부를 2차 씨엠피 한다. 여기서, 상기 제1질화막(23)은 연마 정지막으로 사용되며, 연마하는 상기 제2산화막의 양이 매우 적기 때문에 편차가 거의 없이 상기 제2산화막을 제거할 수 있다. 또한, 상기 1차 씨엠피 시, EFH 편차가 200 Å 정도이기 때문에 2차 씨엠피 시에 EFH 편차는 50Å 이내로 줄어들게 된다.As shown in FIG. 2E, a part of the second oxide film and the first nitride film 23 is secondary CMP. Here, the first nitride film 23 is used as a polishing stop film, and since the amount of the second oxide film to be polished is very small, the second oxide film can be removed with little variation. In addition, since the EFH deviation is about 200 dB in the first CMP, the EFH deviation is reduced to within 50 dB in the second CMP.

그리고 나서, 도 2f에 도시된 바와 같이, 상기 잔류된 제1질화막을 습식 식각하여 제거한다. 이 때, 상기 제1질화막의 습식 식각시 인산 용액을 사용한다. 이 결과로서, 트렌치형의 소자분리막(28)을 형성한다.Then, as shown in Figure 2f, the remaining first nitride film is removed by wet etching. At this time, a phosphoric acid solution is used during the wet etching of the first nitride film. As a result, a trench type device isolation film 28 is formed.

상기와 같은 공정을 통해 제조되는 본 발명에 따른 반도체 소자는 두번의 씨엠피와 두번의 질화막 식각을 실시하여 반도체 소자의 소자분리막을 형성함으로써, 종래에 한 번의 씨엠피와 한번의 질화막 식각을 실시하는 것보다 실리콘 기판에서의 절연 산화막의 높이인 EFH 편차를 줄일 수 있고, 이에, 반도체 소자의 전기적 특성을 향상시킬 수 있다.The semiconductor device according to the present invention manufactured by the above process is performed by etching two CMPs and two nitride films to form a device isolation film of the semiconductor device, thereby conventionally performing one CMP and one nitride film etching. Rather, the EFH deviation, which is the height of the insulating oxide film on the silicon substrate, can be reduced, thereby improving the electrical characteristics of the semiconductor device.

이상에서와 같이, 본 발명은 STI 공정시 정지막의 역할을 하는 질화막을 이중으로 증착시키고, 상기 이중으로 증착시킨 질화막들 사이에 산화막을 증착시켜서 두 번의 씨엠피와 두번의 질화막 식각을 실시한다. 따라서, 종래에 질화막을 한 번 증착시킴으로써 한번의 씨엠피와 한번의 질화막 식각을 실시하는 것보다 실리콘 기판에서의 절연 산화막의 높이인 EFH 편차를 줄일 수 있고, 이에, 반도체 소자의 전기적 특성을 향상시킬 수 있다.As described above, in the present invention, the nitride film serving as the stop film in the STI process is deposited twice, and the oxide film is deposited between the deposited nitride films to perform two CMP and two nitride film etching. Therefore, by depositing a nitride film conventionally, an EFH deviation, which is the height of an insulating oxide film on a silicon substrate, can be reduced, compared to performing one CMP and one nitride film etching, thereby improving electrical characteristics of the semiconductor device. Can be.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (7)

실리콘 기판 상에 제1산화막, 제1질화막, 제2산화막 및 제2질화막을 차례로 형성하는 단계;Sequentially forming a first oxide film, a first nitride film, a second oxide film, and a second nitride film on a silicon substrate; 상기 결과물을 식각하여 필드 영역에 트렌치를 형성하는 단계;Etching the resultant to form trenches in the field region; 상기 트렌치를 포함한 기판 전면에 절연 산화막을 증착하는 단계;Depositing an insulating oxide film on the entire surface of the substrate including the trench; 1차 씨엠피 하여 상기 절연 산화막과 상기 제2질화막 일부를 연마하는 단계;Polishing the insulating oxide film and a portion of the second nitride film by primary CMP; 상기 잔류된 제2질화막을 습식 식각으로 제거하는 단계;Removing the remaining second nitride film by wet etching; 2차 씨엠피 하여 상기 제2산화막과 상기 제1질화막 일부를 연마하는 단계; 및Polishing the second oxide film and a portion of the first nitride film by secondary CMP; And 상기 잔류된 제1질화막을 습식 식각으로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And removing the remaining first nitride film by wet etching. 제 1항에 있어서, 상기 제1질화막을 600 ~ 900 Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.2. The method of claim 1, wherein the first nitride film is deposited to a thickness of 600 to 900 GPa. 제 1항에 있어서, 상기 제2산화막을 60 ~ 150 Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.2. The method of claim 1, wherein the second oxide film is deposited to a thickness of 60 to 150 GPa. 제 1항에 있어서, 상기 제2질화막을 300 ~ 600 Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.2. The method of claim 1, wherein the second nitride film is deposited to a thickness of 300 to 600 GPa. 제 1항에 있어서, 상기 1차 씨엠피 하는 단계는, 상기 제2질화막의 두께가 200 Å 정도 남을 때까지 연마하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the first CMP is polished until the thickness of the second nitride film remains about 200 μs. 제 1항에 있어서, 상기 제1질화막의 습식 식각시, 인산 용액으로 습식 식각하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the wet etching of the first nitride layer is performed by wet etching with a phosphoric acid solution. 제 1항에 있어서, 상기 제2질화막의 습식 식각시, 인산 용액으로 습식 식각하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the wet etching of the second nitride film is performed by wet etching with a phosphoric acid solution.
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