KR20050001188A - Method for forming metal line of semiconductor device using damascene - Google Patents
Method for forming metal line of semiconductor device using damascene Download PDFInfo
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- KR20050001188A KR20050001188A KR1020030042761A KR20030042761A KR20050001188A KR 20050001188 A KR20050001188 A KR 20050001188A KR 1020030042761 A KR1020030042761 A KR 1020030042761A KR 20030042761 A KR20030042761 A KR 20030042761A KR 20050001188 A KR20050001188 A KR 20050001188A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910052802 copper Inorganic materials 0.000 claims abstract description 61
- 239000010949 copper Substances 0.000 claims abstract description 61
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000010409 thin film Substances 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 238000005498 polishing Methods 0.000 claims abstract description 28
- 239000002002 slurry Substances 0.000 claims abstract description 16
- 238000007517 polishing process Methods 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 15
- 229910001111 Fine metal Inorganic materials 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 셀내부나 그 밖의 미세금속패턴영역의 연마가 진행중일 때 대면적의 금속막이 증착두께 차이로 인해 연마속도가 현저히 낮아 평탄화가 일어날 때까지 연마를 막아 주므로써 디싱을 방지할 수 있는 다마신을 이용한 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, when a large area metal film is polished in a cell or other micro metal pattern region, the polishing rate is significantly lowered due to the difference in deposition thickness. The present invention relates to a method for forming metal wiring of a semiconductor device using damascene that prevents dishing by preventing polishing until it occurs.
다마신을 이용한 구리배선 공정은 절연산화막에 배선이 형성될 부분을 식각해 낸 이후 금속막을 증착하여 식각부위를 채우고, CMP 공정을 이용하여 배선형성 이외의 불필요한 금속막을 제거하므로써 배선을 형성하는 공정이다. 이때, 금속연마를 위한 슬러리를 사용하게 되는데, 구리증착시 보통 전기도금방법을 이용하게 된다.The copper wiring process using damascene is a process of forming a wiring by etching a part of wiring to be formed in an insulating oxide film and then depositing a metal film to fill an etching part and removing unnecessary metal film other than wiring formation using a CMP process. . At this time, a slurry for metal polishing is used, and when copper is deposited, an electroplating method is usually used.
기존의 구리 다마신공정을 이용한 금속배선 형성방법에 대해 도 1a 및 1e를 참조하여 설명하면 다음과 같다.Referring to FIGS. 1A and 1E, a metal wiring forming method using a conventional copper damascene process is as follows.
도 1a 및 도 1e는 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명 하기 위한 공정별 단면도이다.1A and 1E are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device according to the related art.
기존의 다마신를 이용한 금속배선 형성방법은, 도 1a에 도시된 바와같이, 반도체웨이퍼(11)상에 절연산화막(13)을 형성한후 배선 형성용 마스크(미도시)를 이용하여 상기 절연막(13)을 선택적으로 제거하여 배선부위를 정의한다.In the conventional method for forming metal wiring using damascene, as shown in FIG. 1A, after forming the insulating oxide film 13 on the semiconductor wafer 11, the insulating film 13 is formed using a wiring forming mask (not shown). Optionally remove) to define wiring area.
그다음, 도 1b에 도시된 바와같이, 상기 배선부위를 포함한 전체 구조의 상면에 구리배리어막으로 Ta/TaN 박막(15)을 증착한다. 이때, 상기 배리어막은 PVD 또는 CVD법으로 100∼500Å 정도 두께로 증착한다.Then, as shown in FIG. 1B, a Ta / TaN thin film 15 is deposited on the upper surface of the entire structure including the wiring portion with a copper barrier film. At this time, the barrier film is deposited to a thickness of about 100 ~ 500Å by PVD or CVD method.
이어서, 도 1c에 도시된 바와같이, 전체 구조의 상면, 즉 Ta/TaN 박막(15)상에 구리박막(17)을 도금법(electroplate)으로 약 5000∼15000Å 두께로 증착한다. 이때, 증착특성상 "A"구간과 같은 단일 패턴지역은 정상적인 증착이 되지만 "B" 구간과 같이 패턴이 넓은 대면적 지역은 산화막이 식각된 높이만큼 낮아지게 되고,조밀패턴이 밀집되어 있는 "C"구간은 오히려 증착속도가 빨라 증착높이가 높다.Subsequently, as shown in FIG. 1C, a copper thin film 17 is deposited on the upper surface of the entire structure, that is, the Ta / TaN thin film 15, by a thickness of about 5000 to 15000 으로 by an electroplate. At this time, the single pattern area such as the "A" section is normally deposited due to the deposition characteristic, but the large area area such as the "B" section has a large pattern area lowered by the height where the oxide film is etched, and the "C" where the dense pattern is dense. The interval is rather high, because the deposition rate is high.
한편, 일반적으로 구리 CMP는 다른 CMP와는 달리 구리와 배리어 Ta/TaN, 산화막을 연속적으로 연마해야 하는데, 슬러리별로 연마속도의 차가 커서 일반적으로 구리와 배리어막을 나눠서 연마하는 2단계방법을 사용한다.On the other hand, in general, unlike other CMP, copper CMP must polish copper, barrier Ta / TaN, and oxide film continuously. Since the difference in polishing rate for each slurry is large, the copper CMP is generally divided into two steps by polishing copper and barrier film.
2단계 방법중, 구리증착후 첫 번째 단계에서의 연마시에 구리의 연마속도가 빨라서 연마중 연마모양이 도 1d에서와 같은 모양을 띈다. 즉, 넓은 패턴영역도 같이 연마되어 결국 CMP후 최종적으로 도 1e에서와같이 넓은 영역인 "B"구간은 금속배선의 두께가 얇아지게 되고 심한 경우 금속패턴이 없어지게 된다.In the two-step method, the polishing rate of copper was increased at the time of polishing in the first step after copper deposition, so that the polishing shape during polishing took the shape as shown in FIG. 1D. That is, the wide pattern region is polished as well, and finally, after the CMP, the “B” section, which is a wide region as shown in FIG.
그러나, 이러한 방법은 증착특성 자체 때문에 조밀한 패턴지역은 증착두께가 크고, 금속배선면적이 넓은 지역의 두께는 얇게 된다. 또한, CMP시 금속막의 산화막에 대한 선택비가 크기 때문에 필연적으로 금속면적이 넓은 패턴의 경우 그렇지 않은패턴에 비해 연마랴이 많아 디싱(dishing)현상에 취약하게 된다.However, in this method, because of the deposition characteristics themselves, the dense pattern region has a large deposition thickness, and the thickness of the region having a large metal wiring area becomes thin. In addition, since the selection ratio of the metal film to the oxide film during CMP is large, inevitably, a pattern having a large metal area is more abrasive than a pattern that is not large, and thus becomes vulnerable to dishing.
따라서, 이러한 금속막은 두께가 매우 얇아지거나 모두 연마되어서 배선의 단락을 유발시키거나 저항을 증가시키는 문제점이 있다.Therefore, such a metal film has a problem that the thickness becomes very thin or all polished to cause a short circuit of the wiring or increase the resistance.
또한, 이러한 디싱을 줄이기 위해서는 연마시간을 줄여야 하는데, 이러한 방법은 공정의 마진을 떨어 뜨릴 수 있으므로 다른 차원의 방법의 개발이 매우 중요하다.In addition, in order to reduce the dishing, it is necessary to reduce the polishing time. Since this method may reduce the margin of the process, it is very important to develop another method.
이를 해결하기 위하여 종래에는 구리막 증착후에 포토레지스트나 SOG를 전면에 증착하고 평탄화하여 넓은 패턴에서 함몰된 영역을 매립하는 마스크층을 사용하였으나 이는 다음과 같은 문제점이 있다.In order to solve this problem, a mask layer for filling a recessed area in a wide pattern is conventionally used by depositing and planarizing a photoresist or SOG on the entire surface after deposition of a copper film, which has the following problems.
먼저, 포토레지스트나 SOG는 증착시에 플로우되는 특징이 있어 주로 평탄화공정에 많이 사용하지만 상기와 같은 대 면적의 패턴에서는 평탄화효과가 없는 단점이 있다.First, since photoresist or SOG is flowed during deposition, it is mainly used in the planarization process, but there is a disadvantage in that the planarization effect does not exist in the large area pattern as described above.
설령 증착후 CMP공정을 통해 평탄화해 마스크층을 만든다 해도 다음과 같은 단점이 있다.Even after deposition, the planarization through the CMP process to make a mask layer has the following disadvantages.
즉, 포토레지스트의 경우 경도가 매우 약하고 폴리머성이어서 CMP 평탄화 자체가 불가능할 뿐아니라 강염기나 강산의 슬러리에 들어 갔을 때 데미지가 커서 마스크 역할을 못하고 구리 CMP시에 바로 녹아 버리게 되어 이러한 마스크 작업에는 적당하지 않은 물질이다.In other words, the photoresist is very weak in hardness and polymeric, so it is impossible to planarize CMP itself, and when it enters the slurry of strong base or strong acid, it does not act as a mask because it is melted in copper CMP. Is not a substance.
SOG의 경우에 증착후 열공정을 거쳐 경화를 시키는데, 이때 구리가 산화되는 단점이 있다. 또한, 산화막용 슬러리를 사용하여 SOG를 평탄화할 경우 넓은 영역의 산화막도 모두 연마되어 마스크 형성이 불가능하며, 금속막용 슬러리를 사용하였을 경우 SOG 특성상 3000 Å 이하의 증착이 불가능하므로 금속막용 슬러리로 연마해야 할 산화막의 두께가 지나치게 높아 연마가 거의 불가능한 단점이 있다.In case of SOG, curing is carried out through a thermal process after deposition, in which case copper is oxidized. In addition, when the SOG is planarized using the oxide film slurry, a wide area of the oxide film is also polished to form a mask, and when the metal film slurry is used, it is impossible to deposit 3000 Å or less due to the SOG characteristics, so it must be polished with the metal film slurry. There is a disadvantage in that the thickness of the oxidized oxide film is too high so that polishing is almost impossible.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 셀내부나 그 밖의 미세금속패턴영역의 연마가 진행중일 때 대면적의 금속막이 증착두께 차이로 인해 연마속도가 현저히 낮아 평탄화가 일어날 때까지 연마를 막아 주므로써 디싱을 방지할 수 있는 다마신을 이용한 반도체소자의 금속 배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and the polishing rate of the large-area metal film is significantly lowered due to the difference in deposition thickness when the inside of the cell or the other fine metal pattern region is in progress. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device using damascene that prevents dishing by preventing polishing until it occurs.
도 1a 및 도 1e는 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명 하기 위한 공정별 단면도,1A and 1E are cross-sectional views of processes for explaining a method of forming metal wirings of a semiconductor device according to the prior art;
도 2a 및 도 2c는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명 하기 위한 공정별 단면도.Figure 2a and Figure 2c is a cross-sectional view for each process for explaining a method for forming a metal wiring of the semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 반도체웨이퍼 33 : 절연산화막31 semiconductor wafer 33 insulating oxide film
35 : 제1구리배리어박막 37 : 구리박막35: first copper barrier thin film 37: copper thin film
39 : 제2구리배리어박막39: 2nd copper barrier thin film
상기 목적을 달성하기 위한 본 발명에 따른 다마신을 이용한 반도체소자의 금속배선 형성방법은, 반도체웨이퍼상에 절연산화막을 형성한후 상기 절연산화막내에 배선부위를 형성하는 단계;Method for forming a metal wiring of a semiconductor device using a damascene according to the present invention for achieving the above object comprises the steps of forming an insulating oxide film on the semiconductor wafer and then forming a wiring portion in the insulating oxide film;
상기 배선부위를 포함한 절연산화막상에 제1구리배리어박막을 형성하는 단계;Forming a first copper barrier thin film on the insulating oxide film including the wiring portion;
상기 제2구리배리어박막상에 구리박막을 형성하는 단계;Forming a copper thin film on the second copper barrier thin film;
상기 구리박막상에 제2구리배리어박막을 형성하는 단계;Forming a second copper barrier thin film on the copper thin film;
구리 연마슬러리를 사용하여 상기 제2구리배리어박막과 구리박막을 연마하는 단계; 및Polishing the second copper barrier thin film and the copper thin film using a copper polishing slurry; And
상기 구리배리어박막용 슬러리를 사용한 연마공정을 거쳐 다마신 금속배선을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming a damascene metal wire through a polishing process using the slurry for the copper barrier thin film.
(실시예)(Example)
이하, 본 발명에 따른 다마신을 이용한 반도체소자의 금속배선 형성방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device using damascene according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2c는 본 발명에 따른 다마신을 이용한 반도체소자의 금속배선 형성방법을 설명 하기 위한 공정별 단면도이다.2A and 2C are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device using damascene according to the present invention.
본 발명에 따른 다마신를 이용한 금속배선 형성방법은, 도 2a에 도시된 바와 같이, 반도체웨이퍼(31)상에 절연산화막(33)을 형성한후 배선 형성용 마스크(미도시) 를 이용하여 상기 절연막(33)을 선택적으로 제거하여 배선부위(미도시)를 한정한다.In the method for forming metal wirings using damascene according to the present invention, as shown in FIG. 2A, an insulating oxide film 33 is formed on a semiconductor wafer 31 and then the insulating film is formed using a wiring forming mask (not shown). Optionally remove 33 to define a wiring portion (not shown).
그다음, 상기 배선부위를 포함한 전체 구조의 상면에 제1구리배리어막으로 Ta박막 또는 TaN 박막(35)을 증착한다. 이때, 상기 제1구리배리어막은 PVD 또는 CVD법으로 100∼500Å 정도 두께로 증착한다.Then, a Ta thin film or TaN thin film 35 is deposited on the upper surface of the entire structure including the wiring portion as the first copper barrier film. At this time, the first copper barrier film is deposited to a thickness of about 100 to 500 mW by PVD or CVD.
이어서, 전체 구조의 상면, 즉 제1구리배리어박막(35)상에 구리박막(37)을 도금법(electroplate)으로 약 5000∼15000Å 두께로 증착한다. 이때, 증착특성상 "A"구간과 같은 단일 패턴지역은 정상적인 증착이 되지만 "B" 구간과 같이 패턴이 넓은 대면적 지역은 산화막이 식각된 높이만큼 낮아지게 되고, 조밀패턴이 밀집되어 있는 "C"구간은 오히려 증착속도가 빨라 증착높이가 높다.Subsequently, a copper thin film 37 is deposited on the upper surface of the entire structure, that is, the first copper barrier thin film 35 to a thickness of about 5000 to 15000 mm by an electroplate. At this time, due to the deposition characteristics, a single pattern region such as an "A" section is normally deposited, but a large area such as a "B" region has a large pattern area lowered by the height where an oxide film is etched, and a "C" with a dense pattern. The interval is rather high, because the deposition rate is high.
그다음, 상기 구리박막(37)상에 제2구리배리어막으로 Ta박막 또는 TaN 박막(39)을 증착한다. 이때, 상기 제2구리배리어막은 PVD 또는 CVD법으로 500∼1000Å 정도 두께로 증착한다.Then, a Ta thin film or TaN thin film 39 is deposited on the copper thin film 37 as a second copper barrier film. At this time, the second copper barrier film is deposited to a thickness of about 500 to 1000 mW by PVD or CVD.
이어서, 도 2b에 도시된 바와같이, 구리연마 슬러리를 사용하여 상기 제2구리배리어박막(39) 및 구리박막(37)을 연마하여 평탄화시킨다. 이때, 연마공정을 거치게 되면 좁은 지역(C)의 패턴이나 일반적인 지역(A)의 패턴위의 Ta박막 또는 TaN박막은 기계적으로 연마가 천천히 진행되지만 넓은 지역(B)의 패턴은 단차가 있어 거의 연마가 되지 않는다. 이러한 이유는 보통 연마시 기계적뿐만이 아니라 화학적 연마를 하게 되는데, 구리 연마용 슬러리를 사용하기 때문에 화학적 연마는 이루어지지 않고 기계적 연마만 이루어지기 때문에 단차가 낮은 지역(B)의 연마는 이루어지지 않게 되기 때문이다.Subsequently, as shown in FIG. 2B, the second copper barrier thin film 39 and the copper thin film 37 are polished and planarized using a copper polishing slurry. At this time, when the polishing process is performed, the Ta thin film or TaN thin film on the pattern of the narrow area (C) or the pattern of the general area (A) is slowly mechanically polished, but the pattern of the wide area (B) has a step and is almost polished. Does not become. The reason for this is that not only mechanical polishing but also chemical polishing is usually performed because the polishing slurry is used for the copper polishing process, and therefore, the polishing is not performed in the low step area (B) because the chemical polishing is not performed. to be.
그다음, 도 2c에 도시된 바와같이, Ta 박막 또는 TaN 박막용 슬러리를 사용하여 잔존하는 제2구리배리어박막(39a)과 구리박막(37)을 연마하여 배선부위에 금속배선(37a)을 형성한다.Then, as shown in FIG. 2C, the remaining second copper barrier thin film 39a and the copper thin film 37 are polished using a Ta thin film or a TaN thin film slurry to form a metal wiring 37a at the wiring site. .
상기에서 설명한 바와같이, 본 발명에 따른 다마신을 이용하여 반도체소자의 금속배선 형성방법에 의하면, 셀내부나 그 밖의 미세금속패턴영역의 연마가 진행중일 때 대면적의 금속막이 증착두께 차이로 인해 연마속도가 현저히 낮아 평탄화가 일어날 때까지 연마를 막아 주므로써 디싱을 방지할 수 있다. 즉, Ta박막 또는 TaN박막이 구리슬러리에서 연마가 잘 이루어지지 않는 점에 착안하여 넓은 패턴영역의 디싱을 방지할 수 있다.As described above, according to the method for forming metal wirings of a semiconductor device using damascene according to the present invention, a large-area metal film is deposited due to a difference in deposition thickness when polishing inside a cell or other fine metal pattern region is in progress. The polishing rate is so low that dishing can be prevented by preventing polishing until planarization occurs. That is, since the Ta thin film or TaN thin film is hardly polished in the copper slurry, the dishing of the wide pattern region can be prevented.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (4)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20190038427A (en) * | 2017-09-29 | 2019-04-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor devices and methods of forming |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20190038427A (en) * | 2017-09-29 | 2019-04-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor devices and methods of forming |
| US10636701B2 (en) | 2017-09-29 | 2020-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming semiconductor devices using multiple planarization processes |
| US11121028B2 (en) | 2017-09-29 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices formed using multiple planarization processes |
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