KR20050000971A - Method of manufacturing FeRAM device - Google Patents
Method of manufacturing FeRAM device Download PDFInfo
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- KR20050000971A KR20050000971A KR1020030041579A KR20030041579A KR20050000971A KR 20050000971 A KR20050000971 A KR 20050000971A KR 1020030041579 A KR1020030041579 A KR 1020030041579A KR 20030041579 A KR20030041579 A KR 20030041579A KR 20050000971 A KR20050000971 A KR 20050000971A
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229920000620 organic polymer Polymers 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 4
- 238000003860 storage Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- -1 and in addition Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 강유전성램 소자의 제조에 관한 것으로, 보다 상세하게는, 깊은 콘택 식각 공정의 안정성을 확보하면서 콘택 프로파일의 변동을 방지할 수 있는 강유전성램 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of ferroelectric ram devices, and more particularly, to a method of manufacturing ferroelectric ram devices capable of preventing fluctuations in contact profiles while ensuring stability of a deep contact etching process.
강유전성램(Ferroelectric RAM: 이하 FeRAM) 소자는 디램(DRAM) 소자와는 달리 전원의 온/오프(On/Off)에 관계없이 데이터를 저장하는 비휘발성(Non-Volatile) 메모리 소자이다. 이러한 FeRAM 소자는 그의 캐패시터 형성시 통상의 유전 물질 대신에 강유전성 물질을 이용하며, 아울러, 전극 물질 또한 디램 소자의 그것과는 다른 물질을 사용한다. 예컨데, FeRAM 소자의 캐패시터에 있어서 강유전성 물질로는 SBT(SrBiTaO) 또는 BLT(BiLaTiO) 등을 사용하며, 전극 물질로는 Pt, Ir, IrO2, Ru 또는 RuO2 등을 사용한다.Ferroelectric RAM (FeRAM) devices, unlike DRAM devices, are non-volatile memory devices that store data regardless of whether the power is turned on or off. Such FeRAM devices use ferroelectric materials instead of conventional dielectric materials when forming their capacitors, and in addition, electrode materials also use materials different from those of DRAM devices. For example, SBT (SrBiTaO) or BLT (BiLaTiO) or the like is used as the ferroelectric material in the capacitor of the FeRAM device, and Pt, Ir, IrO 2, Ru, or RuO 2 is used as the electrode material.
한편, 스토리지 노드 콘택 플러그(storage node contact plug) 형성 공정이 적용되는 FeRAM 소자에서는 소자가 점점 고집적화 됨에 따라 콘택홀 깊이 또한 깊어지고 있고, 이에 따라, 기존의 콘택 식각 방법인 감광막 마스크를 이용한 식각은 그 한계에 부딪히게 되었다. 이것은 식각해야할 깊이가 깊어짐에 따라 감광막에 대한 선택비 부족으로 식각이 어려워졌기 때문이다.Meanwhile, in the FeRAM device to which the storage node contact plug forming process is applied, as the device is increasingly integrated, the contact hole depth is also deepened. Accordingly, the etching using the photoresist mask, which is a conventional contact etching method, is more difficult. The limit was met. This is because as the depth to be etched becomes deeper, the etching becomes difficult due to the lack of selectivity for the photoresist film.
따라서, 스토리지 노드 콘택 플러그 형성 공정을 포함하는 FeRAM 소자의 제조시에는 디램 소자의 제조시와 마찬가지로 하드마스크(Hard Mask)의 사용이 불가피해졌다.Therefore, when manufacturing the FeRAM device including the storage node contact plug forming process, the use of a hard mask is inevitable as in the manufacturing of the DRAM device.
그러나, 콘택 식각을 위해 하드마스크를 적용할 경우, 식각의 어려움은 해결할 수 있지만, 식각 진행후에 하드마스크를 제거해야 하는 것과 관련해서, 상기 하드마스크의 제거시, 콘택 프로파일(contact profile)에 데미지(damage)가 가해지는 문제점이 있다.However, when the hard mask is applied for contact etching, the difficulty of etching can be solved. However, when the hard mask is removed after the etching process, the contact profile is damaged during the removal of the hard mask. There is a problem that damage is applied.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 깊은 콘택홀 형성시에 하드마스크를 사용하면서도 콘택 프로파일에의 데미지 인가를 방지할 수 있는 FeRAM 소자의 제조방법을 제공함에 그 목적이 있다Accordingly, an object of the present invention is to provide a method for manufacturing a FeRAM device that can prevent the application of damage to a contact profile while using a hard mask when forming a deep contact hole. have
도 1a 내지 도 1e는 본 발명의 실시예에 따른 강유전성램 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1E are cross-sectional views of processes for describing a method of manufacturing a ferroelectric ram device according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 절연막1 semiconductor substrate 2 insulating film
3,7 : Pt막 4 : 감광막 패턴3,7 Pt film 4: Photosensitive film pattern
5 : 콘택홀 6 : 콘택 플러그5 contact hole 6 contact plug
10 : 캐패시터 하부전극10: capacitor lower electrode
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소정의 하부패턴들이 형성된 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막 상에 하드마스크 물질로서 Pt막을 증착하는 단계; 상기 Pt막을 패터닝하여 콘택홀 형성 영역을 한정하는 단계; 상기 패터닝된 Pt막을 하드마스크로 이용해서 Pt막에 의해 가려지지 않은 절연막 부분을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 내에 도전막을 매립시켜 콘택 플러그를 형성하는 단계; 및 상기 콘택 플러그 및 절연막 상에 상기 하드마스크로 이용된 Pt막으로 이루어지는 캐패시터 하부전극을 형성하는 단계를 포함하는 FeRAM 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an insulating film on a semiconductor substrate formed with a predetermined lower pattern; Depositing a Pt film as a hard mask material on the insulating film; Patterning the Pt film to define a contact hole forming region; Forming a contact hole by etching the portion of the insulating film not covered by the Pt film using the patterned Pt film as a hard mask; Embedding a conductive film in the contact hole to form a contact plug; And forming a capacitor lower electrode formed of the Pt layer used as the hard mask on the contact plug and the insulating layer.
여기서, 상기 Pt막은 800∼1000Å 두께로 증착한다. 상기 Pt막의 패터닝은, 상기 Pt막 상에 반사방지막과 감광막을 차례로 형성하는 단계; 상기 감광막을 노광 및 현상하여 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 이용해서 반사방지막과 Pt막을 식각하는 단계; 및 상기 감광막 패턴을 제거하는 단계로 구성되며, 상기 반사방지막은 유기 계열의 고분자 화합물로 이루어진다.Here, the Pt film is deposited to a thickness of 800 to 1000 GPa. The patterning of the Pt film may include: sequentially forming an anti-reflection film and a photosensitive film on the Pt film; Exposing and developing the photoresist to form a photoresist pattern; Etching the anti-reflection film and the Pt film by using the photoresist pattern; And removing the photoresist pattern, wherein the anti-reflection coating is made of an organic polymer compound.
상기 Pt막을 식각하는 단계는 Ar과 Cl2의 혼합 가스를 사용하여 수행하며, 상기 Ar 가스의 유량과 Cl2 가스의 유량은 각각 30∼50sccm과 5∼10sccm으로 한다.The etching of the Pt film is performed using a mixed gas of Ar and Cl 2, and the flow rate of Ar gas and the flow rate of Cl 2 gas are 30 to 50 sccm and 5 to 10 sccm, respectively.
상기 Pt막을 식각하는 단계는 무거운 Pt 폴리머의 원할한 배출을 위해 기판 온도를 80℃ 이상으로 유지하여 수행한다.The etching of the Pt film is performed by maintaining the substrate temperature at 80 ° C. or higher for smooth discharge of heavy Pt polymer.
상기 절연막은 질화막과 산화막의 적층막으로 구성하며, 상기 질화막의 식각은 CHF3, O2, CO 및 Ar의 혼합 가스를 사용하여 수행하고, 상기 산화막의 식각은C4F8, O2, CO 및 Ar의 혼합 가스를 사용하여 수행한다.The insulating film is composed of a laminated film of a nitride film and an oxide film, and the etching of the nitride film is performed using a mixed gas of CHF 3, O 2, CO, and Ar, and the etching of the oxide film comprises a mixed gas of C 4 F 8, O 2, CO, and Ar. To use.
상기 Pt막의 식각과 절연막의 식각은 동일장비 내에서 연속적으로 수행한다.The etching of the Pt film and the etching of the insulating film are performed continuously in the same equipment.
본 발명에 따르면, 하드마스크로서 산화막 고선택비를 갖는 Pt막을 이용하며, 특히, 이 Pt막을 후속에서 캐패시터 하부전극 물질로서 활용하기 때문에, 깊은 콘택 식각을 안정적으로 수행할 수 있음은 물론 콘택 프로파일의 데미지 발생도 방지할 수 있다.According to the present invention, a Pt film having a high oxide film selectivity is used as a hard mask, and in particular, since the Pt film is subsequently used as a capacitor lower electrode material, the deep contact etching can be stably performed, Damage can also be prevented.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 FeRAM 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A through 1E are cross-sectional views illustrating processes for manufacturing a FeRAM device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 소정의 하부패턴들(도시안됨)이 형성된 반도체 기판(1) 상에 절연막(2)을 형성한다. 여기서, 상기 절연막(2)은 질화막과 산화막의 적층막으로 구성하며, 그 전체 두께는 10000Å 정도로 한다. 상기 절연막(2) 상에 후속하는 콘택 식각에서의 하드마스크 물질로서 Pt막(3)을 800∼1000Å의 두께로 증착한다. 상기 Pt막(3)은 식각 반응성이 거의 없는 중금속으로서 산화막과의 식각선택비가 50:1인 고선택비 식각이 가능하며, 예컨데, 1000Å의 두께로 10000Å 이상의 깊은 콘택 식각이 가능하다.Referring to FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 on which predetermined lower patterns (not shown) are formed. Here, the insulating film 2 is composed of a laminated film of a nitride film and an oxide film, and its total thickness is about 10000 GPa. A Pt film 3 is deposited on the insulating film 2 to a thickness of 800 to 1000 GPa as a hard mask material in subsequent contact etching. The Pt film 3 is a heavy metal having almost no etching reactivity, and has a high selectivity etching with an etching selectivity of 50: 1 with an oxide film. For example, the Pt film 3 may have a deep contact etch of 10000Å or more with a thickness of 1000Å.
계속해서, 상기 Pt막(3) 상에 감광막을 도포한 후, 상기 감광막을 노광 및 현상해서 콘택홀 형성 영역을 한정하는 감광막 패턴(4)을 형성한다. 이때, 상기 감광막의 도포 전, 상기 Pt막(3)의 안정적인 식각을 위해 반사방지막(도시안됨)을 형성하며, 상기 반사방지막으로서는 유기 계열의 고분자 화합물을 이용한다. 여기서, 상기 반사방막으로서 유기 계열의 고분자 화합물을 이용하는 것은 통상 사용되는 SiN 또는 SiON 계열의 물질은 그 제거시에 제거되지 않고 남는 폴리머가 다량 발생될 수 있기 때문이다.Subsequently, after the photosensitive film is applied on the Pt film 3, the photosensitive film is exposed and developed to form a photosensitive film pattern 4 defining a contact hole forming region. In this case, an anti-reflection film (not shown) is formed to stably etch the Pt film 3 before the photosensitive film is applied, and an organic polymer compound of the anti-reflection film is used. Here, the use of the organic polymer compound as the reflective film is because the SiN or SiON-based material that is commonly used can be generated a large amount of the polymer remaining without being removed.
도 1b를 참조하면, 감광막 패턴을 이용해서 그 아래의 Pt막(3)을 식각하고, 이를 통해, 콘택홀 형성 영역에 해당하는 절연막 부분을 노출시킨다. 여기서, 상기 Pt막(3)의 식각은 Ar 가스와 Cl2 가스의 혼합 가스를 사용하여 수행하며, 이때, 상기 Ar 가스의 유량과 Cl2 가스의 유량은 각각 30∼50sccm과 5∼10sccm 정도로 한다. 또한, 상기 Pt막(3)의 식각은 무거운 Pt 폴리머의 원할한 배출을 위해 기판 온도를 80℃ 이상으로 유지하여 수행한다.Referring to FIG. 1B, the Pt layer 3 below is etched using the photoresist pattern, thereby exposing an insulating layer portion corresponding to the contact hole forming region. Here, the etching of the Pt film 3 is performed by using a mixed gas of Ar gas and Cl 2 gas, wherein the flow rate of Ar gas and the flow rate of Cl 2 gas are about 30 to 50 sccm and 5 to 10 sccm, respectively. In addition, the etching of the Pt film 3 is performed by maintaining the substrate temperature at 80 ° C. or higher for smooth discharge of heavy Pt polymer.
다음으로, 식각 장벽으로 이용된 감광막 패턴을 공지의 스트립(strip) 공정에 따라 제거한다.Next, the photoresist pattern used as the etching barrier is removed according to a known strip process.
도 1c를 참조하면, 식각된 Pt막(3)을 하드마스크로 이용해서 노출된 절연막 부분을 식각하고, 이를 통해, 후속에서 스토리지 노드 콘택 플러그를 형성하기 위한 깊은 콘택홀(5)을 형성한다. 여기서, 상기 절연막(2)은 질화막과 산화막의 적층막으로 구성되어 있는 바, 상기 질화막의 식각은 CHF3, O2, CO 및 Ar의 혼합 가스를 사용하여 수행하며, 상기 산화막의 식각은 C4F8, O2, CO 및 Ar의 혼합 가스를 사용하여 수행한다.Referring to FIG. 1C, the exposed insulating layer portion is etched using the etched Pt layer 3 as a hard mask, thereby forming a deep contact hole 5 for subsequently forming a storage node contact plug. Here, the insulating film 2 is composed of a laminated film of a nitride film and an oxide film, the etching of the nitride film is performed using a mixed gas of CHF3, O2, CO and Ar, the etching of the oxide film is C4F8, O2, This is done using a mixed gas of CO and Ar.
여기서, 하드마스크 물질인 Pt막(3)은 전술한 바와 같이 식각 반응성이 거의없는 중금속이며, 특히, 산화막과의 식각선택비가 50:1인 고선택비 식각이 가능하므로, 이러한 Pt막(3)을 하드마스크로 이용하여 절연막(2)을 식각함에 따라 안정적인 프로파일을 갖는 10000Å 이상의 깊은 콘택홀(5)을 형성할 수 있다.Here, the Pt film 3, which is a hard mask material, is a heavy metal having almost no etching reactivity as described above. In particular, since the high selectivity etching with an etching selectivity of 50: 1 with the oxide film is possible, the Pt film 3 By using the as a hard mask to etch the insulating film 2 can form a deep contact hole (5) of 10000 100 or more having a stable profile.
한편, 전술한 본 발명의 실시예에 있어서, 상기 Pt막(3)의 식각과 질화막 및 산화막의 적층막으로된 절연막(2)의 식각은, 바람직하게, 동일장비 내에서 연속적으로 수행한다.On the other hand, in the above-described embodiment of the present invention, the etching of the Pt film 3 and the etching of the insulating film 2 made of a laminated film of the nitride film and the oxide film are preferably performed continuously in the same equipment.
도 1d를 참조하면, 콘택홀(5)을 매립하도록 기판 결과물 상에 콘택 플러그용 도전막, 예컨데, 다결정실리콘막 또는 텅스텐막을 증착한다. 그런다음, 상기 도전막에 대한 에치백(etchback) 또는 CMP(Chemical Mechanical Polishing)를 행하여 상기 콘택홀(5) 내에 콘택 플러그(6)를 형성한다.Referring to FIG. 1D, a conductive plug for contact plug, for example, a polysilicon film or a tungsten film is deposited on the substrate product to fill the contact hole 5. Then, the contact plug 6 is formed in the contact hole 5 by etching back to the conductive film or chemical mechanical polishing (CMP).
여기서, 상기 콘택 플러그용 도전막으로서 다결정실리콘막을 이용한 경우, 상기 다결정실리콘막의 에치백은 HBr과 O2의 혼합가스를 사용하여 수행하며, 이때, HBr 가스의 유량은 30∼80sccm 정도로 하고, O2 가스의 유량은 3∼30sccm 정도로 한다. 반면, 상기 콘택 플러그용 도전막으로서 텅스텐막을 이용한 경우, 상기 텅스텐막의 에치백은 SF6와 N2의 혼합가스를 사용하여 수행하며, 이때, SF6 가스의 유량은 30∼80sccm 정도로 하고, O2 가스의 유량은 10∼30sccm 정도로 한다.In this case, when the polysilicon film is used as the conductive plug film for the contact plug, the etch back of the polysilicon film is performed using a mixed gas of HBr and O2, wherein the flow rate of the HBr gas is about 30 to 80 sccm, and the O2 gas is The flow rate is about 3 to 30 sccm. On the other hand, when the tungsten film is used as the conductive plug film for the contact plug, the tungsten film is etched back using a mixed gas of SF6 and N2, wherein the flow rate of the SF6 gas is about 30 to 80 sccm, and the flow rate of the O2 gas is It should be about 10-30 sccm.
도 1e를 참조하면, 콘택 플러그(6) 및 식각된 Pt막(3)를 포함한 기판 결과물 상에 도전막, 바람직하게 Pt막(7)을 재차 증착한다. 그런다음, 상기 재차 증착된 Pt막 및 식각된 Pt막(3)을 공지의 공정에 따라 패터닝하여 캐패시터 하부전극(10)을 형성한다.Referring to FIG. 1E, a conductive film, preferably a Pt film 7, is again deposited on the substrate product including the contact plug 6 and the etched Pt film 3. Then, the deposited Pt film and the etched Pt film 3 are patterned according to a known process to form the capacitor lower electrode 10.
여기서, 본 발명의 방법은 하드마스크로 이용된 Pt막(3)을 제거함이 없이 캐패시터 전극 물질로 이용하기 때문에, 하드마스크의 제거로 인한 콘택 프로파일의 데미지 발생은 근본적으로 일어나지 않으며, 그래서, 원하는 프로파일의 콘택홀(6)을 얻을 수 있게 된다.Here, since the method of the present invention is used as a capacitor electrode material without removing the Pt film 3 used as the hard mask, damage of the contact profile due to the removal of the hard mask does not fundamentally occur, and thus, the desired profile. The contact hole 6 can be obtained.
한편, 전술한 본 발명의 실시예에서는 상기 캐패시터 하부전극을 Pt막의 추가 증착을 통해 형성하였으나, 전극 두께가 얇지 않다면, Pt막의 추가 증착없이 이미 하드마스크로 이용되어진 식각된 Pt막 자체를 패터닝하여 형성하는 것도 가능하다.Meanwhile, in the above-described embodiment of the present invention, the capacitor lower electrode is formed through the additional deposition of the Pt film, but if the electrode thickness is not thin, the etching is performed by patterning the etched Pt film itself that is already used as a hard mask without further deposition of the Pt film. It is also possible.
이상에서와 같이, 본 발명은 FeRAM 소자 제조 공정의 깊은 콘택 형성시에 하드마스크 물질로서 산화막 고선택비를 갖는 Pt막을 이용하며, 특히, 이 Pt막을 후속에서 캐패시터 하부전극 물질로서 활용하기 때문에, 깊은 콘택 식각을 안정적으로 수행할 수 있음은 물론 콘택 프로파일의 데미지 발생도 방지할 수 있으며, 그래서, 본 발명은 스토리지 노드 콘택 플러그 형성 공정이 적용되는 FeRAM 소자의 공정 개발을 앞당길 수 있다.As described above, the present invention uses a Pt film having an oxide film high selectivity as a hard mask material at the time of forming a deep contact in the FeRAM device fabrication process, and in particular, since the Pt film is subsequently used as a capacitor lower electrode material, The contact etching can be stably performed, and the damage of the contact profile can be prevented. Accordingly, the present invention can speed up the process development of the FeRAM device to which the storage node contact plug forming process is applied.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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