KR20040110217A - Apparatus and Method of Adaptive Frequency Phase Locked Loop with Low Phase Jitter - Google Patents

Abstract

PURPOSE: An adaptive frequency phase detection system is provided to increase an S/N ratio of a recovered signal and reduce an error rate by adaptively a point of convergence of a frequency according to an input signal. CONSTITUTION: A complex frequency multiplier(304) is used for performing a complex frequency multiplication process for a received pilot signal and an oscillation signal. A phase converter(305) is used for converting a phase of a real part of an output signal from the complex frequency multiplier. A limiter(306) is used for limiting an output signal of the phase converter. A synchronous detector(307) is used for detecting a synchronous convergence. A mode selector(310) is used for limiting selectively a band of an imaginary part by using the synchronous convergence as a control signal. A multiplier(311) is used for multiplying an output of the limiter by an output of the mode selector.

Description

Adaptive frequency phase detection device with low phase noise and its method {Apparatus and Method of Adaptive Frequency Phase Locked Loop with Low Phase Jitter}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive frequency phase detection device with low phase noise and a method thereof. More particularly, the present invention relates to a frequency phase detection loop (FPLL) in recovering frequency and phase of a carrier wave included in a signal received at a receiver of a wireless communication system. The present invention relates to an adaptive frequency phase detection apparatus and method for reducing the amount of phase noise of a recovered carrier when using a Frequency Phase Locked Loop.

First, a brief description of carrier recovery in a wireless communication system, carrier recovery is a process of matching a frequency and a phase of a carrier of a signal input to a receiver with a carrier generated by the receiver to eliminate a difference in frequency, that is, a frequency offset. This is called frequency synchronization, and matching the phase of a carrier wave having a matching frequency is called phase synchronization. This synchronization process consists of an acquisition process that reduces errors and a tracking process that maintains synchronization, and a synchronization process that starts tracking after acquisition is called convergence.

For example, in recovering a carrier by using a frequency phase detection loop at a receiver of a conventional wireless communication system, an American digital transmission using an 8-level residual side band (8-VSB: 8-Vestigial Side Band) as a modulation method. The Advanced Advanced Telecom System Committee (ATSC) system is as follows.

In the 8-VSB transmission system, the signal spectrum is symmetrical, added by a roll-off factor of 5.38 MHz, half of the 10.76 MHz band, for data transmission at 10.76 Msps (symbol per second). The bands are combined to transmit signals through a conventional analog broadcast band of 6 MHz in total.

In addition, the 8-VSB transmission system uses reference signals inserted at regular intervals for symbol timing synchronization or equalization. However, for frequency synchronization, a predetermined DC component called a pilot is added to each signal before transmission of the residual sideband modulation without using a special reference signal. This pilot is located at the position of the DC component in the baseband upon reception. When the frequency is raised to the radio frequency (RF) band, the pilot appears as a single frequency component, that is, a pilot tone.

The 8-VSB modulated signal is thus propagated into the air, which is demodulated via the 8-VSB receiver. To explain the operation of demodulation, simply select the desired channel frequency with the tuner, and use the Surface Acoustic Wave Filter (SAW Filter) to remove the other channel signal from the analog / digital converter. To. The digitized 8-VSB signal is multiplied by the multiplier with the carrier signal (5.38MHz) generated by the numerically controlled oscillator and separated into the real part (I) and the imaginary part (Q). It is multiplied by the oscillator's signal (2.69MHz), restored to the baseband signal, and passed through the channel equalizer. This will be described in more detail with reference to FIGS. 1 and 2 as follows.

1 is an overall configuration diagram of an embodiment of a conventional eight-level residual sideband receiver.

As shown in FIG. 1, the eight-level residual sideband receiver includes a tuner 101, a SAW filter 102, an analog / digital converter 103, a multiplier 104, a matched filter 105, and an adder 111. , A timing recovery unit 112, a channel equalizer 113, a carrier recovery unit 114, and the like.

In operation, when the 8-VSB signal of the radio frequency band is received through the antenna, the tuner 101 selects a desired channel frequency using a heterodyne demodulation method and then the VSB signal of the radio frequency band loaded on the channel frequency. Is transmitted to a fixed intermediate frequency band, and the SAW filter 102 properly removes signals of other channels. The signal of the intermediate frequency band is sampled by the analog / digital converter 103 using the clock recovered by the timing recovery unit 112 and converted into a digital signal. At this time, the center frequency of the received signal passing through the analog-digital converter 103 is located at the final intermediate frequency (5.38MHz). The 8-VSB signal digitized as described above is multiplied by the carrier signal generated by the numerically controlled oscillator 110 and the multiplier 104, and separated into a real part (I) and an imaginary part (Q). The multiplier multiplies the signal of the fixed frequency oscillator 107 (2.69MHz) to restore the baseband signal, and then adds the multiplier 111 again to pass through the channel equalizer 113.

However, when the 8-VSB signal is received, a frequency offset of several hundred kHz and a phase noise are generated by the over-the-air transmission channel, the tuner 101, and the radio frequency oscillator. Accordingly, the carrier recovery unit 114 composed of the band pass filter 106, the frequency phase detection unit 108, the loop filter 109, the numerically controlled oscillator 110, and the fixed frequency oscillator 107 of FIG. Operate in a direction that minimizes offset and phase noise.

2 is a detailed block diagram of an embodiment of the frequency phase detection device 108 of the conventional eight-level residual sideband carrier recovery unit.

As shown in FIG. 2, the frequency phase detection device 108 includes a complex frequency multiplier 206 for performing complex frequency multiplication on the digitized 8-VSB received signal and the signal generated by the fixed frequency oscillator 107. A low pass filter 207 for switching the frequency phase of the real part signal output from the complex frequency multiplier 206, a limiter 208 for limiting the output of the low pass filter 207, and the limiter 208. And a multiplier 209 for multiplying an output and an imaginary part signal output from the complex frequency multiplier 206.

Looking at the operation of the frequency phase detection device 108 in more detail, the digitized 8-VSB signal is first multiplied by the carrier signal (5.38MHz) generated by the numerically controlled oscillator 110 through the multiplier 104, and then real The I component and the imaginary component Q are respectively separated, and the pilot component of the 8-VSB signal is located in the 2.69 MHz band. Therefore, in order to extract only these pilot components, each signal is input to a band pass filter (BPF) 106 centered on 2.69 MHz. At this time, the passband of the bandpass filter 106 is a carrier signal, an air wave transmission channel, a tuner 101 and a radio frequency oscillator that are freely oscillated without performing carrier recovery in the numerical control oscillator 110 during the carrier recovery initial operation. It should be wide enough so that the level of the pilot is not affected by the frequency offset of several hundred kHz caused by. The real part I and the imaginary part Q signals passing through the bandpass filter 106 in this manner have a frequency of 2.69 MHz in the fixed frequency oscillator 107 composed of the oscillator 201 and the 90 degree phase shifter 202. The complex frequency multiplication is performed by the real part I 'and imaginary part Q' signals and the complex frequency multiplier 206, respectively, and are output as the real part I "and imaginary part Q" signals.

Thereafter, the I ″ signal passes through a low pass filter (LPF) 207. The characteristics of the low pass filter 207 are 90 degrees different in phase response according to a frequency offset with respect to a DC component. This I pass through the low pass filter 207 is passed through the limiter 208, the limiter 208 is +1 if the sign of the input signal is positive is negative Output -1

When the output of the limiter 208 and the Q " signal are multiplied by the multiplier 209, a positive signal or a negative signal is output according to the frequency offset, so that the magnitude of the frequency offset can be detected. The offset signal is input to the numerically controlled oscillator 110 through the loop filter 109 to generate a restored carrier, which is synchronized with the frequency through this process, ie, when the restored frequency is smaller than the input frequency, frequency offset is performed. The detection signal has a positive signal component, thereby increasing the frequency of the numerically controlled oscillator 110 so as to be equal to the input frequency, at which time the loop filter 109 adjusts the high frequency component of the detected frequency offset signal. And accumulates the magnitude of the detected frequency offset signal.

On the other hand, when the frequency synchronization is completed, the phase offset signal detected to detect the phase offset is also input to the numerically controlled oscillator 110 through the loop filter 109 to compensate for the phase offset.

Here, the bandwidth of the loop filter 109 is the convergence time of the synchronization process for compensating the frequency and phase offset of the numerically controlled oscillator 110 based on the pilot signal extracted from the bandpass filter 106 and the residual phase noise after convergence. Determine the amount of. In other words, if the bandwidth is wider, the convergence time may be reduced, but after convergence, the amount of phase noise is increased. If the bandwidth is narrow, the amount of phase noise is decreased, but the convergence time is increased.

In addition, the bandwidth of the bandpass filter 106 that selects only the pilot signal of the received signal is a carrier signal, an air wave transmission channel, and a tuner that are freely oscillated without performing carrier recovery in the numerical control oscillator 110 during initial carrier recovery. However, it is necessary to consider that the level of the pilot is not affected by the frequency offset of several hundred kHz generated by the radio frequency oscillator, so that not only the pilot signal but also the data signal spectrum components are passed together. Therefore, in order to compensate for a wide range of frequency offsets, the band of the bandpass filter 106 should be set wide. In this case, the pilot signal passing through the bandpass filter 106 includes a large number of data signal spectral components, and thus the phase after convergence. There is a problem that the noise is increased.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and adaptively finds a frequency synchronization convergence point according to a changing channel condition of a changing input signal by using a limiter output in a frequency phase detection loop. Accordingly, an object of the present invention is to provide an adaptive frequency phase detection device and method for reducing phase noise by selectively connecting a lowpass filter.

1 is an overall configuration diagram of an embodiment of a conventional eight-level residual sideband receiver.

Figure 2 is a detailed configuration diagram of an embodiment of the frequency phase detection apparatus of the conventional eight-level residual sideband carrier recovery unit.

Figure 3 is an overall configuration diagram of an embodiment of a low frequency noise adaptive frequency phase detection apparatus according to the present invention.

4 is an operation explanatory diagram of a synchronous detector in an adaptive frequency phase detection device with low phase noise according to the present invention;

5 is a detailed block diagram of an embodiment of a synchronization detector of an adaptive frequency phase detection device with low phase noise according to the present invention.

* Explanation of symbols for the main parts of the drawings

108: frequency phase detection unit 206, 304: complex frequency multiplier

305: first low pass filter 306: limiter

307: sync detector 310: mode selector

312: adaptive frequency phase detector

An apparatus of the present invention for achieving the above object comprises: a complex frequency multiplication means for performing complex frequency multiplication by receiving a received pilot signal and an oscillation signal; Phase shifting means for shifting a phase of a real part signal among the output signals of said complex frequency multiplication means; Limiting means for outputting different signals before and after frequency synchronization convergence by limiting the output signal from said phase shifting means; Sync detection means for adaptively detecting whether the sync converged with the output of the limiting means; Mode selection means for selectively limiting the band of the imaginary part signal among the output signals of the complex frequency multiplication means by using whether or not the synchronization detection is detected by the synchronization detection means; And multiplication means for multiplying the output of said limiting means and the output of said mode selection means.

In addition, the present invention provides an adaptive frequency phase detection method comprising: a first step in which a complex frequency multiplier receives a received pilot signal and an oscillation signal and performs complex frequency multiplication; A second step of converting a phase of a real part signal among signals output by complex frequency multiplication by the complex frequency multiplier; A third step of limiting the phase shifted real part signal to output a different signal before and after frequency synchronization convergence; A fourth step of receiving, by the sync detector, the output of the limiter and adaptively detecting whether or not the frequency sync is converged; A fifth step of selectively limiting the band of the imaginary part signal among the output signals of the complex frequency multiplier by using a mode selector as a control signal as to whether or not the sync detector detects sync convergence; And a sixth step of multiplying the output of the limiter by the output of the mode selector.

As described above, when the carrier is reconstructed using the frequency phase locked detection loop at the receiving end of the wireless communication system, the present invention adaptively adjusts the frequency according to the changing channel condition of the input signal which is changed using the limiter output in the frequency phase locked detection loop. Find the synchronization convergence point and according to the result, do not selectively connect the lowpass filter to the imaginary signal line before the frequency synchronization convergence, and after the frequency synchronization convergence, selectively connect the lowpass filter to the imaginary signal line. By reducing the influence of noise, it is possible to improve the carrier synchronization performance by reducing the phase noise in the tracking process without increasing the convergence time.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 3 is a schematic diagram of an embodiment of an adaptive frequency phase detection device 312 with low phase noise according to the present invention.

As shown in FIG. 3, the adaptive frequency phase detector 312 according to the present invention receives a pilot signal extracted from a digitized 8-VSB received signal and a signal generated by the fixed frequency oscillator 107 and receives a complex frequency. Complex frequency multiplier 304 for performing multiplication, a first low pass filter 305 for detecting a frequency deviation by converting the phase of the real part signal of the output signal of the complex frequency multiplier 304 by 90 degrees, the first 1 Limiter 306 for outputting a positive signal or a negative signal before the frequency synchronization convergence with the output of the low pass filter 305 as an input, and a constant value of only one of the positive signal or the negative signal after the frequency synchronization convergence. ), The complex detector for receiving the output of the limiter 306 and adaptively detecting the synchronization convergence, using the output of the sync detector 307 as a control signal. Among the output signals of the multiplier 304, the imaginary convergence is selectively connected to or not connected to the second lowpass filter 309, that is, whether or not the synchronization detection is detected by the synchronization detector 307 as a control signal. A mode selector 310 for passing the imaginary signal from the complex frequency multiplier 304 and limiting the band of the imaginary signal from the complex frequency multiplier 304 after synchronous convergence, and the limiter 306 And a multiplier 311 for detecting the frequency deviation by multiplying the output of the multiplier by the output of the mode selector 310.

The mode selector 310 uses a second low-pass filter 309 before synchronous convergence of the imaginary part of the output signals of the complex frequency multiplier 304 by using whether the synchronization detector 307 detects synchronous convergence. To reduce the noise band of the imaginary part of the output signal of the complex frequency multiplier 304 according to the switch 308, and the situation of the switch 308 A second low pass filter 309 for the filter.

Next, the operation of each component will be described in detail.

The real part signal I ″ passing through the complex frequency multiplier 304 of the adaptive frequency phase detector 312 is a first low pass filter that detects a frequency deviation by converting the frequency phase by 90 degrees according to the frequency offset ( 305).

Thereafter, the limiter 306 receives the output signal of the first low pass filter 305 and outputs a value of +1 or -1 before frequency synchronization convergence, and one of +1 or -1 after frequency convergence. Only a value is output to limit the output signal of the first low pass filter 305.

In addition, the output of the limiter 306 is divided in two directions, one of which is input to the multiplier 311 and passes through the imaginary part signal Q ″ or the second low pass filter 309 to multiply the signal of the imaginary part of which the band is limited. And is used to detect frequency and phase deviation, the other being input to a sync detector 307 according to the present invention.

The sync detector 307 finds an appropriate frequency sync convergence point according to the situation by using the sum of the output of the limiter 304 outputting the value limited to +1 and -1 every hour and the absolute value thereof. After convergence, 1 is output to control the switch 308 of the mode selector 310. At this time, the synchronization detector 307 according to the present invention has a feature of detecting frequency synchronization by automatically adjusting a threshold value according to the amount of frequency offset of the signal input to the carrier recovery unit.

On the other hand, the signal Q " of the imaginary part passing through the complex frequency multiplier 304 passes through the mode selector 310. The switch 308 of the mode selector 310 controls the control signal from the sync detector 307. After inputting the signal, the imaginary part of the imaginary part passes through the signal as it is, so as to achieve fast frequency synchronization, and after the frequency synchronization, the second low pass filter 309 passes through the noise component that is low in all frequency bands. The noise band is reduced by limiting the bandwidth of the second lowpass filter 309.

4 is an explanatory diagram of the operation of the synchronous detector 307 of the adaptive frequency phase detection device with low phase noise according to the present invention.

As shown in FIG. 4, the left graph shows the sum of the output values of the limiter. The output moving with a slope of +1 and -1 before the frequency convergence has a slope of either +1 or -1 after the frequency convergence. It is kept constant, and the graph on the right is a graph that takes an absolute value with respect to the result on the left. After convergence, it is always kept at a constant slope of +1.

The operation of the sync detector 307 is largely divided into two processes. For example, referring to the graph of FIG. 4A, the first process is an operation process before convergence and performs an operation of finding a maximum value such as a point 'a'. To this end, a temporary buffer is stored to store the maximum value, and the maximum value is detected in the section before convergence by comparing the current symbol value with the symbol value stored in the buffer and inserting a large value back into the buffer for each symbol. The second process is the post-convergence operation. When the synchronization loop maintains a constant convergence value and a section with a constant slope 1 appears, the current symbol value is compared with the maximum value (a) stored in the buffer in the first process. When the value (b) is reached, this point is determined as a convergence point and the mode is switched. Due to such a feature, even if a separate threshold value is not set at the time of mode switching, the mode can be switched by adaptively estimating the threshold value according to the situation.

5 is a detailed block diagram of an embodiment of a synchronization detector 307 of an adaptive frequency phase detection device with low phase noise according to the present invention.

As shown in FIG. 5, the sync detector 307 according to the present invention includes an accumulator 503 for accumulating values by adding an output of the limiter 306 and a maximum value of an output value of the accumulator 503. The absolute value converter 504 for converting the output value of the accumulator 503 into an absolute value and the output value of the absolute value converter 504 are inputted to be used to determine whether the frequency is synchronized or not. Comparators for comparing the current input value and keeping the past value as the maximum value in the loop if the past value is large, and keeping the current value as the maximum value in the loop if the current value is large and outputting the signal out of the loop. 511 and a threshold for controlling the switch 308 of the mode selector 310 according to the signal of the comparator 511 output out of the loop when the present value of the absolute value converter 504 is larger than the past value. detection And a 512. The

The accumulator 503 delays the adder 501 adding the output value of the limiter 306 and the output value of the adder 501, and then delays the delayed value to the adder 501. ).

The comparator 511 may operate in the same manner as the first comparator 505 and the first comparator 505 that receive and compare an output value of the absolute value converter 504 and a past value from the first delay unit 507. The second comparator 506, the first multiplier 509 to multiply the output value of the absolute value converter 504 and the output value of the first comparator 505, the output value and the second delay of the second comparator 506 Input the second multiplier 510 to multiply the output value of the unit 508, the adder 511 to add the output value of the first multiplier 509 and the output value of the second multiplier 510, the output value of the adder 511 A second delay 507 that receives the first and second comparators 505 and 506 and inputs an output value of the adder 511 to the second multiplier 510. Group 508.

The accumulator 503 calculates the sum of the inputs at every instant and uses the present value. The absolute value converter 504 converts the value accumulated by the accumulator 503 into an absolute value and converts the absolute value to the present value. Input to comparator 512. In the first comparator 505 and the second comparator 506, the present value is compared with the past value held in the first delayer 507 and the second delayer 508 serving as a buffer, and the present value is the past value. If smaller, the first comparator 505 outputs 0 and the second comparator 506 outputs 1 to maintain the maximum value in the loop.If the current value is greater than the past value, the first comparator 505 returns 1. The second comparator 506 outputs 0 to maintain the current value in the loop as the maximum value, and passes 1 to the threshold detector 513 to output the control signal to the switch 308 of the mode selector 310. do.

This control signal, i.e., the output of the sync detector 307, controls the switch 308 of the mode selector 310 connected to the imaginary part signal Q "passed through the complex frequency multiplier 304 before the frequency sync convergence. After the frequency synchronization convergence without connecting the second low pass filter 309, the second low pass filter 309 is connected. Thus, the frequency phase detection device according to the present invention can compensate under conditions having the same loop filter. Although the size and frequency of convergence can be the same as in the conventional method, the phase noise is reduced in the tracking process after the frequency synchronization, thereby eliminating the phase noise of the restored carrier.

On the other hand, when frequency synchronization is detected, the phase offset signal detected to detect the phase offset is also input to the numerically controlled oscillator 110 through the loop filter 109 to compensate for the phase offset. The phase detection process as described above is the same as the frequency detection process and will not be described in detail.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention adaptively finds a frequency synchronization convergence point in accordance with a changing input signal when the carrier is restored at a receiving end of the wireless communication system, and according to the result, a lowpass filter is applied to the imaginary number before the frequency synchronization convergence. After the frequency synchronization convergence without selective connection, the low pass filter is selectively connected to the imaginary part to reduce the phase noise to increase the signal-to-noise ratio of the restored signal, thereby reducing the error occurrence rate.

Claims (7)

In the adaptive frequency phase detection device, Complex frequency multiplication means for receiving a received pilot signal and an oscillation signal and performing complex frequency multiplication; Phase shifting means for shifting a phase of a real part signal among the output signals of said complex frequency multiplication means; Limiting means for outputting different signals before and after frequency synchronization convergence by limiting the output signal from said phase shifting means; Sync detection means for adaptively detecting whether the sync converged with the output of the limiting means; Mode selection means for selectively limiting the band of the imaginary part signal among the output signals of the complex frequency multiplication means by using whether or not the synchronization detection is detected by the synchronization detection means; And Multiplication means for multiplying the output of the limiting means and the output of the mode selection means Adaptive frequency phase detection device comprising a. The method of claim 1, The synchronization detecting means is Accumulating means for receiving an output of the limiting means and continuously accumulating the input values; Absolute value converting means for converting the output value of the accumulation means into an absolute value; The output value of the absolute value converting means is input and the past value is compared with the currently input value. If the past value is large, the past value is kept in the loop as the maximum value, and if the present value is large, the current value is maximum. Comparison means for keeping the value in the loop and outputting the signal out of the loop; And Threshold detection means for receiving the output signal of the comparison means and transmitting a control signal to the mode selection means Adaptive frequency phase detection device comprising a. The method according to claim 1 or 2, The mode selection means, Switching means for passing an imaginary part signal of the output signal of the complex frequency multiplication means before synchronous convergence and switching to a filtering means after synchronous convergence, with or without synchronous convergence detection in the synchronous detection means as a control signal; And The filtering means for limiting a pass band by receiving an imaginary part signal of an output signal of the complex frequency multiplication means according to the switching of the switching means Adaptive frequency phase detection device comprising a. The method of claim 3, wherein The phase conversion means, And a low pass filter converting the frequency phase by 90 degrees according to the frequency offset of the real part signal among the output signals of the complex frequency multiplication means. In the adaptive frequency phase detection method, A first step in which the complex frequency multiplier receives the received pilot signal and the oscillation signal and performs complex frequency multiplication; A second step of converting a phase of a real part signal among signals output by complex frequency multiplication by the complex frequency multiplier; A third step of limiting the phase shifted real part signal to output a different signal before and after frequency synchronization convergence; A fourth step of receiving, by the sync detector, the output of the limiter and adaptively detecting whether or not the frequency sync is converged; A fifth step of selectively selecting a band of the imaginary part signal among the output signals of the complex frequency multiplier by using a mode selector as a control signal as to whether or not the sync detector detects sync convergence; And A sixth step of multiplying the output of the limiter by the output of the mode selector Adaptive frequency phase detection method comprising a. The method of claim 5, wherein The fourth step, A accumulator receives the output of the limiter and continuously accumulates the input values; An eighth step of converting the output value of the accumulator to an absolute value; The comparator receives the output value converted into the absolute value, compares the past value with the current input value, and keeps the past value as the maximum value in the loop if the past value is large, and if the current value is large, A ninth step of keeping the value at the maximum in the loop and outputting a signal out of the loop; And A tenth step in which a threshold detector receives the output of the comparator and controls the mode selector Adaptive frequency phase detection method comprising a. The method according to claim 5 or 6, The fifth step, An eleventh step, wherein the switch passes the imaginary part signal of the output signal of the complex frequency multiplier before synchronous convergence and switches to a filter after synchronous convergence, using whether the synchronization detector detects synchronous convergence in the synchronous detector; And A twelfth step of the filter limiting a pass band of an imaginary part signal of an output signal of the complex frequency multiplier according to switching of the switch Adaptive frequency phase detection method comprising a.