KR101344976B1 - Apparatus for recovering carrier wave in digital broadcasting receiver - Google Patents

Abstract

The present invention relates to a carrier recovery apparatus of a digital broadcast receiver for correcting a frequency offset of a carrier using a pilot signal or a received signal according to a received signal state in a digital broadcast receiver receiving a VSB (Vestigial Sideband) modulation broadcast signal. To this end, the present invention is a phase separator for receiving a digitally converted passband signal and separating it into a passband complex signal of real and imaginary components having different phases, and a digital passband complex output from the phase separator. A downconverter receiving a complex conjugate value of a signal and a complex sine wave at a fixed frequency and multiplying it to convert a digital passband complex signal into a baseband signal, and a baseband complex signal passed through the downconverter. A plurality of phase error detection units provided with different phase error detection characteristics After detecting the phase errors through each of the phase errors, the detected phase errors are accumulated to estimate the frequency errors of the plurality of phase error detectors, and the complex sinusoids are generated by compensating the frequency errors by sharing the estimated frequency errors. And a carrier recovery unit for converting the complex signal into a baseband signal whose frequency offset is corrected by multiplying the complex signal passing through the down converter.

Description

Carrier recovery device of digital broadcasting receiver {APPARATUS FOR RECOVERING CARRIER WAVE IN DIGITAL BROADCASTING RECEIVER}

1 is a block diagram showing a carrier recovery apparatus of a digital broadcast receiver according to the prior art.

FIG. 2 is a diagram illustrating a detailed configuration of a carrier restoration unit and a symbol timing restoration unit of FIG. 1.

3 is a schematic block diagram showing a carrier recovery apparatus of a digital broadcast receiver according to an embodiment of the present invention.

4 is a diagram illustrating a detailed configuration of a symbol timing restoration unit and a carrier restoration unit of FIG. 3 according to an embodiment of the present invention.

5 is a diagram illustrating a detailed configuration of the first phase error detection unit of FIG. 4 according to the present invention.

6 is a diagram illustrating a detailed configuration of a second phase error detection unit of FIG. 4 according to the present invention.

7 is a diagram illustrating a detailed configuration of the frequency sharing loop filter of FIG. 4 according to the present invention.

8 is a diagram illustrating a detailed configuration of the frequency sharing loop filter of FIG. 4 according to another embodiment of the present invention.

9A to 9G are diagrams illustrating signal spectra output from respective elements of FIG. 4.

DESCRIPTION OF THE REFERENCE NUMERALS

150: A / D converter 170: phase separator

190: downconverter 191: complex multiplier

195: NCO 210: Symbol Timing Restoration Unit

211: resampler 213: passband timing error detection unit

215: loop filter 217: numerically controlled oscillator

230: carrier recovery unit 231: first complex multiplier

232: second complex multiplier 235: control unit

241: first phase error detection unit 242: second phase error detection unit

242-1: First Downsampler 242-2: OQAM Signal Generator

242-3: Phase error calculator 242-4: Second down sampler

242-5: upsampler 245: frequency sharing loop filter

247: first numerically controlled oscillator (NCO) 248: second numerically controlled oscillator (NCO)

250: matching filter 270: DC eliminator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for correcting the symbol timing and frequency offset of a carrier, and in particular, in a digital broadcast receiver for receiving a broadcast sideband (VSB) modulated broadcast signal, it is easy to offset the frequency of the carrier without depending on the pilot signal. The present invention relates to a carrier recovery apparatus of a digital broadcast receiver capable of recovering a carrier by detecting and correcting the same.

In general, the ATSC A / 53 digital television standard, proposed by the Grand Alliance and adopted as the SDTV / HDTV terrestrial transmission standard in the United States and Korea, delivers payload data at 19.4 MHz over 8-VSB on 6 MHz channels. It is based on the modulation and transmission to (8-level Vestigial SideBand). The VSB method modulates only the remaining part when one sideband signal of the two sidebands generated up and down about a carrier is greatly attenuated when the signal is amplitude modulated. In other words, it takes one side waveband spectrum of the baseband and transfers it to the passband to transmit the band.

At this time, when the baseband DC spectrum is shifted to the passband during the VSB modulation, it is converted into a tone spectrum, and this signal is often referred to as a pilot signal. That is, when VSB modulation is performed in a broadcasting station, a pilot signal of a small size is loaded on the receiver to facilitate carrier recovery.

1 is a general block diagram of a digital broadcast receiver for receiving and restoring a broadcast signal of the VSB modulation scheme.

First, the airwave RF signal input to the antenna is converted into a passband signal of intermediate frequency (IF) in the tuner 11, and the passband signal is analog signal processed via the IF processor 13. It is then input to the A / D converter 15. The IF processor 13 includes a SAW filter for removing high frequency components generated from interference and tuners of adjacent channels, a gain controller (AGC) for adjusting the level of an input signal, and the like.

The A / D converter 15 converts the analog passband signal output from the IF processor 13 into a digital passband signal and outputs the signal to the phase separator 17. For example, when the fixed oscillator is used in the A / D converter 15, the analog signal is converted into a digital signal having a fixed sampling frequency (25 MHz).

The phase separator 17 converts a digitally transformed passband signal into a complex signal (I signal, Q signal). The phase separator 17 separates the carrier band by separating the passband signals of real and imaginary components whose phases are 90 서로 to each other. Output to the restoration unit 19.

The carrier recovery unit 19 converts the passband complex signal output from the phase separator 17 into a baseband complex signal and outputs the complex signal to the symbol timing recovery unit 21 for symbol clock recovery.

The symbol timing restoration unit 21 serves to synchronize the clock of the transmitter and the clock of the receiver, and ultimately, by sampling the baseband or passband signal at an optimum point in time, at the output of the channel equalizer 27. It should be operated to minimize decision error.

The output of the symbol timing restorer 21 passes through the matched filter 23. The matched filter 23 uses a square root cosine filter having a roll-off factor. The output signal of the matched filter 23 is a DC eliminator. After passing through 25, the pilot signal is removed and input to the channel equalizer 27.

The channel equalizer 27 removes the inter-symbol interference (ISI) included in the signal passing through the symbol timing restoring unit 21 and outputs it to the phase tracker 29. That is, in a digital transmission system such as HDTV, a bit detection error is caused at the receiving side due to distortion caused by a transmission signal passing through a multi-path channel, interference by an NTSC signal, and distortion by a transmission / reception system. In particular, propagation of signals through multipaths causes intersymbol interference (ISI), which is a major cause of bit detection errors. Thus, the channel equalizer 27 eliminates this inter-symbol interference (ISI).

The phase tracker 29 corrects the residual phase of the carrier that is not completely removed by the carrier restorer 19 and outputs the frequency to the frequency error corrector 31.

The frequency error corrector 31 corrects the error of the phase-corrected signal and outputs it to the A / V processor 33. The A / V processor 33 restores the video and audio signals compressed by the MPEG-2 and Dolby AC-3 schemes to the original state, and transfers the video signals to the monitor 37 so that the screen can be viewed. Is transmitted to the speaker 39 so that the sound can be heard.

2 illustrates an example of the carrier recovery unit 19 and the symbol timing restoration unit 21 of FIG. 1 according to the prior art.

The carrier recovery unit 19 is composed of a frequency and phase locked loop (FPLL) system that simultaneously performs frequency acquisition and tracking using a pilot signal. The process of restoring a carrier using the pilot signal will be described below. same.

First, a phase splitter 17 is passed to obtain a complex signal from a passband real signal converted into a digital signal by the A / D converter 15. The complex signal passing through the phase separator 17 is converted into a baseband signal by the carrier recovery unit 19.

The first complex multiplier 19-1 of the carrier recovery unit 19 has a frequency offset of f _{P, est} which is a frequency offset of the pilot signal estimated at f _P , which is a pilot frequency, to the passband complex signal passed through the phase separator 17. When the complex conjugate is multiplied, the pilot signal is present at a position deviated by the amount of f _P -f _{P, est which} is a frequency offset Δf _P from DC. Here, in order to reduce the influence of the data pattern jitter from the pilot signal having the frequency offset of Δf _P , the pilot signal is passed through the low pass filter 19-2 (LPF) and then the frequency / The phase error detection means 19-3 to 19-7 extract the error and phase error of the carrier frequency to correct the baseband frequency offset output from the first complex multiplier 19-1.

Here, the real component signal Re (·) output through the low pass filter 19-2 is input to the multiplier 19-4 directly or through a delay unit 19-3. The signal Imag (·) is input directly to the multiplier 19-4. This configuration is used to widen the frequency recovery range. For example, the multiplexer (MUX) selects and outputs the delayed real component signal through the delay unit 19-3 before the carrier frequency is restored. After the carrier frequency is restored, a signal of a real component that is not delayed is selected and output.

Subsequently, the symbol timing restoring unit 21 restores symbol timing from a signal converted to baseband through a frequency and phase locked loop (FPLL), which is a carrier restoring system of the carrier restoring unit 19.

The symbol timing restoring unit 21 employs a typical Gardner type timing error detector (TED), and in order to reduce the influence of pattern jitter due to transition of 8-level VSB symbols, the upper side band After passing a band pass filter 21-2 (BPF) having a bay as a pass band, an error required for symbol timing recovery is extracted through the Gardner TED (Gardner TED).

The error thus obtained is low pass filtered by the loop filter 21-4, and then passes through the NCO 21-5 to control the control signal of the re-sampler 21-1. Will be created. The resampler 21-1 is converted from a baseband digital signal sampled at a fixed frequency used in A / D conversion to a baseband digital signal sampled at a frequency corresponding to exactly two times the symbol frequency.

The signal whose symbol timing is restored is passed through the matching filter 23 and then passed through the DC remover 25 to the channel equalizer 27.

In the carrier recovery system of FIG. 2, since carrier recovery depends solely on the pilot signal and its frequency and phase, when the frequency corresponding to the position of the pilot signal is severely attenuated in the selective channel environment of the frequency, the carrier recovery is performed. It becomes impossible.

In addition, when the coherence bandwidth of the channel is very narrow compared to the signal band, only the pilot signal is severely attenuated, and the lower sideband signals located around the pilot signal are often not attenuated. The lower sideband signals, which are not attenuated, act as pattern jitter, resulting in overall performance degradation of the receiver.

An object of the present invention is to provide a carrier recovery apparatus of a digital broadcast receiver in which a carrier recovery performance is not degraded even in a frequency selective fading channel environment in a digital broadcast receiver that receives a VSB (Vestigial Sideband) modulation broadcast signal.

Another object of the present invention is to compensate for the frequency offset of the carrier using the form of a pilot signal or a baseband complex signal according to the state of the received signal, thereby recovering the carrier of the digital broadcast receiver in which the carrier of the received signal can be easily restored under any circumstances. To provide a device.

Technical means of the present invention for achieving the above object, in the carrier recovery system for receiving a passband signal of a specific channel and converting the passband digital signal and extracting the symbol through the carrier recovery, the digitally converted passband A phase separator for receiving a signal and separating the real and imaginary passband complex signals having different phases and outputting the separated signals; A down converter for converting the digital passband complex signal into a base signal of a base signal by multiplying the complex pass value of the digital passband complex signal output from the phase separator and a complex sine wave of a fixed frequency; And detecting a phase error through a plurality of phase error detection units having different phase error detection characteristics by receiving a baseband complex signal passing through the down converter, and accumulating the detected phase errors to accumulate the plurality of phase error detection units. Estimate the frequency error, generate a complex sine wave to compensate for the frequency error by sharing the estimated frequency error, and multiply the generated complex sine wave with the complex signal passing through the downconverter And a carrier recovery unit for converting the signal into a signal.

It is installed between the down-converter and the carrier recovery unit and samples the complex signal passing through the phase separator at 2 times the symbol frequency, analyzes the sampled signal to detect the timing error, and then adjusts the sampling time according to the timing error. Characterized in that it further comprises a symbol timing recovery unit for restoring the timing.

In detail, the plurality of phase error detection units may include: a first phase error detection unit detecting a phase error by detecting a pilot signal of an input complex signal; And a second phase error detector which detects a phase error by using a form of an input complex signal.

The carrier recovery unit includes a first and second parallel connection that corrects a frequency offset of a baseband complex signal by mutually multiplying a baseband complex signal passing through a downconverter and a complex sine wave corresponding to an estimated frequency error value. Second complex multiplier; A first phase error detection unit detecting a phase error by detecting a pilot signal of a complex signal output through the first complex multiplier; A second phase error detector which detects a phase error using a form of a complex signal output through the second complex multiplier; The frequency error is estimated by accumulating the phase error values output from the first and second phase error detectors, and converting the phase error into a frequency error by adding a phase error by sharing the estimated frequency error value. A frequency shared loop filter for supplying frequency error values to the first and second complex multipliers through an oscillator; And monitoring the complex signals input from the first and second complex multipliers to differentially control the sharing contribution to the phase errors of the first and second phase error detection units input to the frequency sharing loop filter, and to control the first and second complex error signals. And a control unit for selectively controlling the output of the complex signal input from the complex multiplier.

The first phase error detector may include: a low pass filter configured to receive a complex signal output through a first complex multiplier and extract a pilot signal; A delay unit receiving and delaying a pilot signal of a real component Re (·) output from the low pass filter; A multiplexer for receiving a pilot signal of a real component from the delay or low pass filter and selectively outputting the pilot signal; And a phase error value is detected by multiplying the imaginary component signal (Imag (·)) output from the low pass filter and the real component signal output from the multiplexer, and detecting the phase error value. And a multiplier for outputting.

The second phase error detection unit includes: a downsampler for sampling and outputting a baseband complex signal output through the second complex multiplier at a frequency equal to a symbol frequency; An OQAM signal generator for multiplying and receiving a complex signal output from the downsampler and a complex sine wave having a center frequency of 1 / n of a symbol frequency from the outside, and separating the complex signal into an OQAM signal of real and imaginary components; And a phase error calculator configured to extract a phase error value by calculating a phase error value from the OQAM signals of the real and imaginary components respectively output from the OQAM signal generator.

The 1 / n complex sine wave of the OQAM signal generator is a fixed oscillation signal having a center frequency of 1/4 of a symbol frequency, and the phase error calculator comprises a real component (I (k)) output from the OQAM signal generator. And calculate the phase error values tanh (I (k) * Q (k)) − tanh (Q (k-1 / 2) * I (k−) 1/2)) value.

The frequency sharing loop filter includes: a first Kp multiplier configured to receive and multiply a phase error value of the first phase error detector by a proportional gain control signal output from the controller; A second Kp multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a proportional gain control signal output from the controller; A first Ki multiplier for receiving and multiplying a phase error value of the first phase error detection unit and a cumulative gain control signal output from the control unit; A second Ki multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a cumulative gain control signal output from the control unit; An accumulator for adding the outputs of the first and second Ki multipliers and accumulating phase error values to calculate a frequency error value of a carrier; A first adder for adding a phase error value output from the first Kp multiplier and a frequency error value output from an accumulator to convert the phase error into a frequency error value; And a second adder for adding the phase error value output from the second Kp multiplier and the frequency error value output from the accumulator to convert the phase error into a frequency error value.

The symbol timing restoring unit may include: a resampler for sampling and outputting a baseband signal output through the carrier restoring unit at a clock frequency corresponding to two times a predetermined symbol frequency at a transmitting end; A passband timing error detection unit configured to extract a signal of an upper band from the signal spectrum generated from the resampler and monitor a state of zero crossing to detect synchronization error of timing; A loop filter which receives the timing error signal output from the passband timing error detection unit and performs low pass filtering; And a numerically controlled oscillator for generating a sampling clock compensated for the error timing according to the signal output from the loop filter and supplying it to the resampler.

According to another aspect of the present invention, there is provided a baseband complex signal in a carrier recovery system that receives a passband signal of a specific channel, converts it into a passband digital signal, and extracts a symbol through carrier recovery. And first and second complex multipliers connected to each other to correct a frequency offset for a complex signal of a baseband by mutually multiplying a complex sine wave corresponding to the estimated frequency error value. A first phase error detection unit detecting a phase error by detecting a pilot signal of a complex signal output through the first complex multiplier; A second phase error detector which detects a phase error using a form of a complex signal output through the second complex multiplier; By accumulating the phase error values output from the first and second phase error detectors, the frequency error is estimated, and the numerical error is controlled after converting the phase error into a frequency error by adding the phase error by sharing the estimated frequency error value. A frequency shared loop filter for supplying frequency error values to the first and second complex multipliers through an oscillator; And monitoring the complex signals input from the first and second complex multipliers to differentially control the sharing contribution to the phase errors of the first and second phase error detection units input to the frequency sharing loop filter, and to control the first and second complex error signals. And a control unit for selectively controlling the output of the complex signal input from the complex multiplier.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit block diagram showing a carrier recovery apparatus of a digital broadcast receiver according to an embodiment of the present invention, and includes a tuner 110, an IF processor 130, an A / D converter 150, a phase separator 170, and a down. Converter 190, symbol timing recovery unit 210, carrier wave recovery unit 230, matching filter 250, DC eliminator 270 and the like.

The tuner 110 is configured to receive an airwave RF signal input to an antenna and convert it into a passband signal having an intermediate frequency (IF).

The IF processor 130 is configured to receive the passband signal output from the tuner 110, process the analog signal, and output the analog signal to the A / D converter 150. The IF processor 130 is composed of a SAW filter for removing high frequency components generated from adjacent channel interference and the tuner 110, and a gain controller (AGC) for adjusting the level of an input signal.

The A / D converter 150 receives an analog passband signal output from the IF processor 130, samples the signal using a fixed sampling frequency, and converts the signal into a digital passband signal through quantization to the phase separator 170. It is configured to output.

The phase separator 170 receives a digitally transformed passband signal from the A / D converter 150 to convert the complex signal into a complex signal (I signal, Q signal), and outputs the phases 90 ° to each other. It is separated into a passband signal of imaginary components and output to the down converter 190. Here, for convenience of explanation, the real component signal output from the phase separator 170 is called an I signal, and the imaginary component signal is called a Q signal.

The down converter 190 receives a digital passband signal output from the phase separator 170 and a conjugate complex value of a complex sine wave at a fixed frequency, and multiplies the digital passband signal into a baseband signal. It is configured to convert.

The symbol timing restoring unit 210 samples the complex signal of the base band (Rear Baseband) output from the down converter 190 at 2 times the symbol frequency and analyzes the sampled signal to detect the timing error and then timing error. The sampling time is adjusted to restore the timing of the symbol frequency.

The carrier recovery unit 230 includes first and second complex multipliers 231 and 232, a phase / frequency error estimator 240, and a controller 235, and the first and second complex multipliers 231. , 232 corrects the frequency offset of the baseband complex signal by multiplying the complex signal of the baseband passing through the symbol timing restoration unit 210 with the complex sine wave corresponding to the estimated frequency error value. The phase / frequency error estimator 240 is provided with a baseband complex signal output from the first and second complex multipliers 231 and 232 to provide a detector having different phase error detection characteristics therein. Each phase error is detected, the frequency error value is estimated according to the phase error, and the signals compensated for this are output to the first and second complex multipliers 231 and 232 so that the pilot signal is zero frequency point (f = 0). Is the baseband signal located at And the control unit 235 monitors the complex signals input from the first and second complex multipliers 231 and 232 to determine the shared contribution of the phase and frequency error estimation unit 240 to the phase and frequency error. In addition to the differential control, an output of a complex signal input from the first and second complex multipliers 231 and 232 is selected and output to the matching filter 250.

The matched filter 250 is a fixed coefficient I, Q digital having a roll-off value defined around 6 MHz, which is the same as the complex square root raised cosine filter used in the transmission stage. The matching filter is configured to remove and output aliasing from a baseband complex signal output through the carrier recovery unit 230.

The DC canceller 270 is configured to remove an inserted pilot signal in order to facilitate carrier recovery and output the same to a channel equalizer 290 for removing intersymbol interference (ISI).

4 is a diagram showing the detailed configuration of the down converter 190, the symbol timing recovery unit 210 and the carrier recovery unit 230 of FIG. 3 according to an embodiment of the present invention, the timing of the carrier using the FPLL system The carrier is recovered by recovering the phase error.

The down converter 190 receives a complex complex value for a complex passband signal output from the phase separator 170 and a fixed frequency complex sine wave output from the numerically controlled oscillator 195 and multiplies it through a complex multiplier 191. And converts the digital passband signal into a signal of a baseband (baseband with no frequency offset corrected).

The symbol timing restoration unit 210 is composed of an FPLL system including a resampler 211, a passband timing error detection unit 213, a loop filter 215, and a numerically controlled oscillator 217. That is, the symbol timing restoring unit 210 receives the signal converted into the base band by the down converter 190 and receives the resampler 211 and the passband timing error detection unit 213 and the loop. Through a predetermined FPLL system consisting of a filter 215 and a Numerically Controlled Oscillator (217), the baseband signal is sampled at exactly 2 times the symbol frequency (2f _{S, VSB} ). After analyzing the sampled signal to detect the timing error, the timing of the symbol is adjusted to synchronize the symbol timing. In this case, since a baseband signal having no frequency offset corrected corresponds to a passband signal, the passband timing error detection unit 215 may be used to accurately set the frequency band of the symbol to a predetermined 5.38MHz.

The carrier recovery unit 230 is composed of an FPLL system including a first complex multiplier 231, a second complex multiplier 232, a control unit 235, and a phase / frequency error estimation unit 240.

The phase / frequency error estimator 240 detects a pilot signal of a complex signal output through the first complex multiplier 231 and detects a phase error, and the first phase error detector 241 detects a phase error. A second phase error detector 242 for detecting a phase error by using a complex signal output through the double complex multiplier 232, and phases output from the first and second phase error detectors 241 and 242; Accumulate the error value to estimate the frequency error, and share the estimated frequency error value and add the phase error to convert the phase error to frequency error, and then use the numerically controlled oscillator to convert the frequency error value into the first and second complexes. The frequency sharing loop filter 245 for supplying to the multipliers 231 and 232, and the frequency error associated with the first phase error detection unit 241 output from the frequency sharing loop filter 245 are provided to the frequency error value. Corresponding complex Frequency error values related to the first value control oscillator 247 for generating a wave and outputting the first complex multiplier 231 and the second phase error detection unit 242 output from the frequency sharing loop filter 245 are obtained. The second numerical control oscillator 248 generates a complex sine wave corresponding to the frequency error value and outputs the complex sine wave to the second complex multiplier 232.

That is, the output signal of the symbol timing restoring unit 210 passes through the first and second complex multipliers 231 and 232 and uses the estimated frequencies / phases output from the first and second numerically controlled oscillators 247 and 248. As the complex sine wave is multiplied, the frequency and phase of the carrier wave are respectively corrected.

Here, the first and second phase error detectors 241 and 242 receive complex signals outputted through the first and second complex multipliers 231 and 232 to recover the carrier, and detect the phase error. The first and second phase error detectors 241 and 242 have different phase error detection characteristics.

For example, the first phase error detector 241 detects a phase error using a pilot signal, but the second phase error detector 242 detects a phase error using a shape of a complex signal rather than a pilot signal. Done. Therefore, even when the pilot signal included in the carrier is severely attenuated, the second phase error detection unit 242 can be used to recover the carrier.

Detailed configurations of the first and second phase error detection units 241 and 242 having such characteristics are shown in FIGS. 5 and 6, respectively.

As shown in FIG. 5, the first phase error detector 241 includes a low pass filter 241-1, a delayer 241-2, a multiplexer 241-3, and a multiplier 241-4. .

The low pass filter 241-1 receives a complex signal output through the first complex multiplier 231 to extract a pilot signal, and the delay unit 241-2 receives the low pass filter 241-1 from the low pass filter 241-1. The pilot signal of the real component Re (·) outputted is delayed, and the multiplexer 241-3 receives the pilot signal of the real component from the delay unit 241-2 or the low pass filter 241-1. The multiplier 241-4 receives the imaginary component signal Imag (·) output from the low pass filter 241-1 and the real component signal output from the multiplexer 241-3. Each of them is provided to be multiplied to detect a phase error value and then output the detected phase error value to the frequency sharing loop filter 245.

That is, a pilot signal is extracted by passing a complex signal output through the first complex multiplier 231 through a low pass filter 241-1 (LPF), and a real component output through the low pass filter 241-1. The pilot signal Re (·) is input to the multiplexer 241-3 (MUX) directly or through the delay unit 241-2, and the output signal of the multiplexer 241-3 and the low pass filter 241−. The imaginary signal Imag (·) output through 1) is input to the multiplier 241-4 and multiplied. This configuration is used to widen the frequency recovery range. For example, the multiplexer 241-3 selects and outputs a signal of the real component delayed through the delayer 241-2 before the carrier frequency is restored. However, after the carrier frequency is restored, the non-delayed real component signal is selected and output.

Meanwhile, as illustrated in FIG. 6, the second phase error detector 242 includes a first down sampler 242-1, an OQAM signal generator 242-2, a phase error calculator 242-3, and a second And a downsampler 242-4 and an upsampler 242-5.

The first downsampler 242-1 samples the baseband complex signal output from the second complex multiplier 232 at 1 fs, the same frequency as the symbol frequency, and outputs the same to the OQAM signal generator 242-2.

The OQAM signal generator 242-2 includes a complex signal output from the first downsampler 242-1 and a complex sine wave whose center frequency is 1/4 of the symbol frequency from the outside (e ^{-j (n / 2) π} ). It is composed of complex multipliers that receive and multiply each and output a complex signal separated by real and imaginary components.

As described above, the complex signal of the real and imaginary components output through the OQAM signal generator 242-2 is input to the phase error calculator 242-3.

The phase error calculator 242-3 includes a first tanh calculator 242-31, a first delay unit 242-32, a second delay unit 242-33, a second tanh calculator 242-34, and a And a multiplier 242-35, a second multiplier 242-36, and an adder 242-37. On the other hand, the carrier recovery of the phase error calculator 242-3 is a method of estimating the phase of the baseband from the noise-received received signal, and does not assume a pilot signal. It is not affected by the attenuation at all.

As described above, in the present invention, the correlation between the VSB signal and the Offset-Quadrature Amplitude Modulation (OQAM) signal is used to apply the carrier recovery without using the pilot signal to the VSB scheme. Equivalence of the VSB signal and the OQAM signal is well known through the known literature, and thus detailed description thereof will be omitted.

Accordingly, the carrier recovery algorithm based on the assumption of the OQAM signal can be applied to the VSB method by equivalence. In the present invention, the carrier recovery can be performed without the pilot signal by applying the OQAM method to the carrier recovery.

Referring to the operation of the detailed configurations of the phase error calculator 242-3, first, the first tanh calculator 242-31 inputs a real signal I (k) to a tanh (I (k)) value. The first delay units 242-32 receive the I (k) signal and delay it to generate an I (k-1 / 2) signal.

The second delay unit 242-33 receives the imaginary signal Q (k) and delays it to generate a Q (k-1 / 2) signal, and the second tanh calculator 242-34 receives Q (k-1). / 2) The tanh (Q (k-1 / 2)) value is calculated and output as a signal.

The first multiplier 242-35 calculates and outputs a tanh (I (k) * Q (k)) value from the output of the first tanh calculator 242-31 and the imaginary signal, and the second multiplier 242-36. Calculates and outputs a tanh (Q (k-1 / 2) * I (k-1 / 2)) value from the outputs of the second tanh calculators 242-34 and the first delay units 242-32.

Finally, when the output signal of the second multiplier 242-36 passes through the adder 242-37, tanh (I (k) * Q (k))-tanh (Q (k-1 / 2) * I (k-1 / 2)) value, which is a phase error value obtained by the OQAM method.

In addition, since the carrier recovery of the OQAM method presupposes the restoration of symbol timing due to the characteristics of the algorithm, the phase error calculation unit 242-3 of the carrier recovery unit 230 is a symbol timing restoration unit 210 as shown in FIG. It is located after the. In other words, the symbol timing restoring unit 210 should apply a passband symbol timing restoring algorithm capable of restoring the symbol timing even in the presence of a frequency offset of the carrier for smooth operation of the synchronization unit. It should be possible to extract the phase error of the band.

Since the phase error calculator 242-3 operates in a double-sampled time domain, the second downsampler 242-4 in the rear stage has a phase frequency of 1/2 fs (for example, 5.38 MHz). Only baseband phase error values in symbol units are extracted.

As described above, the second downsampler 242-4 extracts the phase error value corresponding to the frequency offset output from the phase error calculator 242-3 as a 1 / 2fs sampling frequency and then up-sampler 242-5; And the upsampler 242-5 to _adjust the baseband phase error input at a speed of 1f _{S, OQAM} ( _5.38MHz ) to match the operating frequency with the portion compensating the phase of the baseband. The second complex multiplier 232 is upsampled at a clock speed 2fs and then output to the frequency sharing loop filter 245.

As such, the carrier phase error values estimated by the first and second phase error detection units 241 and 242 are input to the frequency sharing loop filter 245, and the frequency sharing loop filter 245 accumulates the phase error value. The frequency error is estimated, and the phase error is converted into a frequency error as the phase error is added by sharing the estimated frequency error value.

Meanwhile, in the above embodiment, the first complex multiplier 231, the first phase error detector 241, the second complex multiplier 232, and the second phase error detector 242 provided in the carrier recovery unit 230 are symbolized. Although all are disposed at the rear end of the timing restoring unit 210, it is possible to arrange them at different positions or to arrange the first and second complex multipliers 231 and 232 at different positions. In other words, the first complex multiplier 231, the first phase error detector 241, the second complex multiplier 232, and the second phase error detector 242 before the symbol timing are restored to the front end of the resampler 211. The rear end of the matching filter 250, the rear end of the DC eliminator 270, or the like may be disposed at different positions.

Although the carrier recovery unit 230 shows and describes only a plurality of phase error detection units 241 and 242, the present invention is not limited to a plurality of phase error detection units and complex multipliers having different phase error detection characteristics. Of course, it can be further configured with a numerically controlled oscillator.

In addition, FIG. 7 illustrates a detailed configuration of a frequency sharing loop filter according to an embodiment of the present invention. As illustrated, the frequency sharing loop filter 245 includes a plurality of Kp multipliers 245-11 and 245-12. ), A second multiplier loop composed of a plurality of Ki multipliers (245-21, 245-22), an adder (245-3), an accumulator (245-4), and a plurality of adders (245-51, 245-52). It is a modified structure.

As described above, the frequency sharing loop filter 245 receives and multiplies the phase error value of the first phase error detection unit 241 and the proportional gain control signal Kp1 output from the control unit 235 and multiplies the first Kp multiplier 245. -11), a second Kp multiplier 245-12 for receiving and multiplying the phase error value of the second phase error detection unit 242 and the proportional gain control signal Kp2 output from the control unit 235; A first Ki multiplier 245-21 for receiving and multiplying the phase error value of the first phase error detector 241 and the cumulative gain control signal Ki1 output from the controller 235, and the second phase error detector 242; A second Ki multiplier (245-22) for receiving and multiplying the phase error value of the control unit and the cumulative gain control signal Ki2 output from the controller 235, and the first and second Ki multipliers (245-21, 245-22). And an accumulator 245-4 for accumulating the phase error value to calculate the frequency error value of the carrier, and adding the first Kp multiplier 24. 5-11) a first adder 245-51 for adding a phase error value output from the accumulator 245-4 and a frequency error value output from the accumulator 245-4, and converting the phase error into a frequency error value, and the second Kp multiplier A second adder 245-52 converts the phase error into a frequency error value by adding the phase error value output from the 245-12 and the frequency error value output from the accumulator 245-4.

That is, the input signals from the first and second phase error detectors 241 and 242 are the first and second Kp multipliers 245-11 and 245-12 and the first and second Ki multipliers 245-21 and 245-22. The first Kp multiplier 245-11 is a portion that reflects the proportional gain of the first phase error detector 241, and the first Ki multiplier 245-21 is the first phase. It is a part that reflects the integrated gain of the error detection unit 241, and the second Kp multiplier 245-12 is a part that reflects the proportional gain of the second phase error detection unit 242. The second Ki multipliers 245-22 reflect a cumulative gain of the second phase error detection unit 242.

The outputs of the first Ki multipliers 245-21 and the second Ki multipliers 245-22 are added by an adder 245-3, and then input to an accumulator 245-4. The frequency error value of the carrier is calculated by accumulating the phase error value as shown in Equation 1 below.

Is the phase error value and Δf is the frequency error value.

That is, the adder 245-3 combines the outputs of the first Ki multiplier 245-21 and the second Ki multiplier 245-22 to reflect the frequency estimate, and the accumulator 245-4 is combined. The frequency signals of the carriers are estimated by accumulating the output signals of the first and second Ki multipliers 245-21 and 245-22.

The output signal of the accumulator 245-4 is output signal of the first Kp multiplier 245-11 and the second Kp multiplier 245-12 through the first adder 245-51 and the second adder 245-52. And the added output signal is input to the first and second numerically controlled oscillators 247 and 248, respectively.

The first and second numerically controlled oscillators 247 and 248 generate a complex sine wave having a frequency and a phase estimated from the signals output from the first and second adders 245-51 and 245-52 to generate a first complex multiplier. 231 and the second complex multiplier 232.

Accordingly, the first complex multiplier 231 is a complex sine wave having a baseband complex signal output from the symbol timing restoration unit 210 and an estimated frequency and phase output from the first numerical control oscillator 247. Multiply by to correct the offset of the frequency (locating the pilot signal at zero frequency point (f = 0)) so that the complex signal is correctly converted to baseband.

In addition, the second complex multiplier 232 is a complex sine wave having a baseband complex signal output from the symbol timing restoring unit 210 and an estimated frequency and phase output from the second numerical control oscillator 248. By multiplying the frequency offset to correct the complex signal to the baseband (baseband) to accurately convert.

On the other hand, the control unit 235 generates the signals required for the control of the frequency shared loop filter 245 by using the output signals of the first and second complex multipliers 231 and 232 as inputs, the first and second complexes. The overall contribution can be controlled by observing the output signals of the multipliers 231 and 232 to control the parameters Kp and Ki of the frequency sharing loop filter 245.

For example, when the attenuation of the pilot signal is large, the first phase error detection unit 241 (depending on the pilot signal when restoring the carrier) reduces the contribution of the phase error generated while the second phase error detection unit ( 242 (not dependent on the pilot signal when reconstructing the carrier) may be controlled to increase the contribution of the phase error generated by the first phase error detection unit 241 to compensate for and overcome the weak point of the carrier reconstruction.

Accordingly, the controller 235 monitors the complex signals input from the first complex multiplier 231 and the second complex multiplier 232 to control the calculation of the phase and frequency error values of the frequency sharing loop filter 245. In addition, a baseband complex signal output from the first and second complex multipliers 231 and 232 is provided to select one of the baseband complex signals. Here, the controller 235 may select any one of the output signals of the first or second complex multipliers 231 and 232 as the output signal. This is complex because the frequency sharing loop filter 245 adds the phase error values of the first and second phase error detection units 241 and 242, respectively, and estimates and shares the frequency error values as accumulating in the accumulator 245-4. The first and second complex multipliers 231 and 232 may recover the carrier regardless of the signal characteristics.

8 illustrates a frequency shared loop filter according to another embodiment of the present invention, wherein the frequency shared loop filter 245 includes a plurality of Kp multipliers 245-11 and 245-12 and a plurality of accumulators 245-21, respectively. 245-22), a plurality of Ki multipliers 245-31 and 245-32, an adder 245-4, and a plurality of adders 245-51 and 245-52.

The signals output from the first and second phase error detectors 241 and 242 are input to the plurality of Kp multipliers 245-11 and 245-12 and the first and second accumulators 245-21 and 245-22, respectively. The output signals of the first and second accumulators 245-21 and 245-22 are accumulated gain control output from the controller 235 through the first Ki multipliers 245-31 and the second Ki multipliers 245-32. The signals Ki1 and Ki2 are respectively multiplied and input to the adder 245-4.

That is, in the case of FIG. 8, the combination of the output signals of the accumulators 245-21 and 245-22 is different from FIG. The signals passing through the first and second accumulators 245-21 and 245-22 contain information on the frequency error. The output signals of the first and second accumulators 245-21 and 245-22 are added to each other. 245-4) to estimate the frequency error of the carrier. In addition, the parameter signals Ki1 and Ki2 input to the first Ki multipliers 245-31 and the second Ki multipliers 245-32 are output from the controller 235. As also mentioned in FIG. 7, the controller 235 observes the states of the input signals of the first and second phase error detection units 241 and 242, and through the first and second signals Kp and Ki, respectively. The phase error detection units 241 and 242 control the degree of contribution to the frequency estimation.

Then, the carrier recovery process according to an embodiment of the present invention will be described in more detail with reference to FIGS. 4 to 7.

First, the A / D converter 150 samples the received passband analog signal at a fixed frequency (for example, 25 MHz) and converts the passband digital signal into a passband digital signal. The converted passband digital signal is a phase separator 170. splitter). At this time, the signal spectrum input to the phase separator 170 is as shown in Figure 9a, the signal spectrum is formed of the spectrum of the 6MHz band centering around the passband frequency ㅁ 6MHz, the signal spectrum is a phase separator 170 Is entered.

The phase separator 170 converts a real passband real signal into a passband complex signal using a Hilbert transform and then outputs it to the downconverter 190. In this case, the signal spectrum output from the phase separator 170 is as shown in FIG. 9B, and the signal spectrum centered at -6 MHz is removed from the phase separator 170, and only the signal spectrum centered at +6 MHz is complex-multiplier of the downconverter 190. 191).

The down converter 190 receives a complex complex value for a complex passband signal output from the phase separator 170 and a fixed frequency complex sine wave output from the numerically controlled oscillator 195 and multiplies it through a complex multiplier 191. The digital passband signal is converted into a signal of the base band (the baseband where the frequency offset is not corrected).

The complex multiplier 191 multiplies the passband complex signal output from the phase separator 170 and the conjugate complex value of the complex sine wave output from the numerically controlled oscillator 195 to output the baseband signal, but the complex multiplier 191 The complex signal of the baseband outputted from) is outputted with the frequency offset as shown in FIG. 9C.

As described above, the complex signal of the base band including the frequency offset is supplied to the resampler 211 of the symbol timing restoring unit 210, and the resampler 211 transmits the complex signal to the symbol frequency predetermined at the transmitter. (fs; for example, 10.76 MHz) is sampled at a clock frequency (2fs; 21.52 MHz) corresponding to twice, and the signal passed through the resampler 211 is the first and second complex of the carrier recovery unit 230 The multipliers 231 and 232 are respectively input.

The passband timing error detection unit 213 extracts a signal of the upper band from the signal spectrum generated from the resampler 211 and monitors a zero-crossing state to determine a timing synchronization error. The timing error signal is lowpass filtered through a loop filter 215 operating at symbol frequency fs (10.76MHz). The low pass filtered signal output from the loop filter 215 becomes a DC component, and the DC signal is input to the numerically controlled oscillator 217. The numerically controlled oscillator 217 provides the resampler 211 with a sampling clock whose error timing is compensated according to the input DC. As described above, the symbol timing restoring unit 210 may restore symbol timing even if a frequency offset exists in the baseband complex signal.

The symbol timing restoring unit 210 restores symbol timing by checking a timing error from a signal output from the complex multiplier 191 through the above process. Of course, the symbol timing is restored by the symbol timing restoring unit 210, but as shown in the signal spectrum of FIG. 9D, the output signal of the resampler 211 still has a frequency offset. In addition, since the baseband signal without frequency offset correction corresponds to a passband, the frequency band of the signal passing through the resampler 211 must be pre-designated only by using the passband timing error detector 215. Accurately set to 5.38MHz.

The complex signal output through the resampler 211 is input to the first and second complex multipliers 231 and 232 of the carrier restorer 230.

The first complex multiplier 231 multiplies the complex signal output from the resampler 211 and the complex sine wave output from the first numerically controlled oscillator 247 to output the baseband signal, but the first complex multiplier 231 The complex signal (rear baseband) that is output from the C-T is output as it is until the frequency offset is corrected. That is, when the frequency offset is corrected, the pilot signal is located at the zero frequency point f = 0.

Like the first complex multiplier 231, the second complex multiplier 232 multiplies the complex signal output from the resampler 211 by the complex sine wave output from the second numerical control oscillator 248 to output the baseband signal. However, the complex signal (Rear Baseband) output from the second complex multiplier 232 is output as it is until the frequency offset is corrected.

As such, the output signals of the first and second complex multipliers 231 and 232 are input to the first and second phase error detection units 241 and 242 and the control unit 235 of the phase / frequency error estimation unit 240, respectively. do.

The complex signal inputted to the first phase error detection unit 241 passes through the low pass filter 241-1 (LPF), and the pilot signal included in the complex signal is extracted and output through the low pass filter 241-1. The real signal pilot signal Re (·) is input to the multiplexer 241-3 (MUX) directly or through the delay unit 241-2, and the output signal of the multiplexer 241-3 and the low pass filter. The imaginary component signal Imag (·) output through 241-1 is input to the multiplier 241-4 and multiplied.

This configuration is used to widen the frequency recovery range. For example, the multiplexer 241-3 selects a signal of the real component delayed through the delayer 241-2 until the frequency of the carrier is restored. After the carrier frequency is restored, a signal of a real component that is not delayed is selected and output.

In addition, the complex signal input to the second phase error detector 242 is downsampled to the same frequency as the symbol frequency through the first downsampler 242-1, and then the output complex signal having the spectrum as shown in FIG. 9E is an OQAM signal. It is input to the generator 242-2.

Subsequently, the OQAM signal generator 242-2 receives and receives a complex signal having a spectrum as shown in FIG. 9E and a complex sine wave whose center frequency is 1/4 of a symbol frequency through the second complex multiplier 232, respectively. do. At this time, if there is a frequency offset, the output signal of the OQAM signal generator 242-2 is slightly skewed to one side by the frequency offset as shown in FIG.

The OQAM signal generator 242-2 is represented as a complex multiplier having the output complex signal and the complex sine wave of the first downsampler 242-1 as inputs, but the center frequency of the input complex sine wave is 1 / the symbol frequency. Since 4, in fact, it can be simply implemented without the need of a complex multiplier.

In other words, in the input complex sine wave (e ^{-j (n / 2) π} ), n is 0, 1, 2, 3,... When the complex sine wave is ^{1 (e -j · 0 = 1} ), -j (e -j (π / 2) = cos (π / 2) -jsin (π / 2) = - j), -1 ( e- ^{j π} = cos ^π -jsin ^π = -1) , j (e- ^{j · (3/2) π} = j) ,... Since it repeats the value of, it can be implemented simply by selecting the input signal with sign conversion.

When the real and imaginary components are separated from the output complex signal of the OQAM signal generator 242-2 and input to the phase error calculator 242-3, the phase error calculator 242-3 using the OQAM method without a pilot signal. We can calculate the phase error value which is the frequency offset using.

The phase error calculator 242-3 receives and calculates the OQAM signals of the real component I (k) and the imaginary component Q (k) output from the OQAM signal generator, respectively, and calculates a phase error value tanh ( I (k) * Q (k))-tanh (Q (k-1 / 2) * I (k-1 / 2)) will be output.

Meanwhile, the complex signal input to the OQAM signal generator 242-2 is input at the same frequency as the symbol frequency (10.76 MHz), and the complex signal input to the phase error calculator 242-3 is converted into an OQAM signal. After the conversion, the sampling frequency is the same by the first and second delay units 242-32 and 242-33 of the phase error calculator 242-3, but the symbol interval of the converted OQAM signal is increased as the symbol period is increased. This is twice as long. This is a state oversampled twice in terms of the OQAM signal output from the OQAM signal generator 242-2. In other words, 1f _{S, VSB} = _10.76MHz = 2f _{S, OQAM} .

Therefore, since the first and second delay units 242-32 and 242-33 are delayed by one clock on the basis of 1f _{S and VSB, the} delay is 1/2 symbol on the basis of the OQAM signal. Since the phase error calculator 242-3 operates in a double-sampled time domain, the second downsampler 242-4 in the rear stage has a phase frequency of 1/2 fs (for example, 5.38 MHz). Only baseband phase error values in symbol units are extracted.

As described above, the second downsampler 242-4 extracts the phase error value corresponding to the frequency offset output from the phase error calculator 242-3 as a 1 / 2fs sampling frequency and then up-sampler 242-5; And the upsampler 242-5 to _adjust the baseband phase error input at a speed of 1f _{S, OQAM} ( _5.38MHz ) to match the operating frequency with the portion compensating the phase of the baseband. The sample is sampled at the clock speed 2fs on the second complex multiplier 232 side.

The phase error signal whose operating speed is adjusted through the upsampler 242-5 is input to the frequency sharing loop filter 245.

Accordingly, the phase error signals output from the first phase error detector 241 and the second phase error detector 242 are first and second Kp multipliers 245-11 and 245-12 of the frequency sharing loop filter 245. And first and second Ki multipliers 245-21 and 245-22, respectively.

The outputs of the first Ki multipliers 245-21 and the second Ki multipliers 245-22 are added by an adder 245-3 and then input to an accumulator 245-4, and an accumulator 245-4. Calculates the frequency error value of the carrier by accumulating the phase error value. That is, the adder 245-3 combines the outputs of the first Ki multiplier 245-21 and the second Ki multiplier 245-22 to reflect the frequency estimate, and the accumulator 245-4 is combined. The frequency signals of the carriers are estimated by accumulating the output signals of the first and second Ki multipliers 245-21 and 245-22.

Meanwhile, the phase error signals output from the first and second Kp multipliers 245-11 and 245-12 are accumulated through the first adder 245-51 and the second adder 245-52. Are added to the estimated frequency error values and converted into frequency error signals, and the converted frequency error signals are input to the first and second numerical control oscillators 247 and 248, respectively.

The first and second numerically controlled oscillators 247 and 248 generate a complex sine wave having a frequency and a phase estimated from the signals output from the first and second adders 245-51 and 245-52 to generate a first complex multiplier. 231 and the second complex multiplier 232.

Accordingly, the first complex multiplier 231 is a complex sine wave having a baseband complex signal output from the symbol timing restoration unit 210 and an estimated frequency and phase output from the first numerical control oscillator 247. Multiply by to correct the offset of the frequency (locating the pilot signal at the zero frequency point f = 0) so that the complex signal is correctly converted to baseband.

In addition, the second complex multiplier 232 is a complex sine wave having a baseband complex signal output from the symbol timing restoring unit 210 and an estimated frequency and phase output from the second numerical control oscillator 248. By correcting the offset of the frequency by multiplying so that the complex signal is accurately converted to the baseband (baseband) as shown in Figure 9g.

Assuming that the carrier restoration unit 230 corrects a phase error that is exactly a frequency offset, the output signals of the first and second complex multipliers 231 and 232 may have a pilot signal of zero frequency point as shown in the signal spectrum of FIG. f = 0) so that it is exactly converted to baseband.

In addition, the control unit 235 generates the signals necessary for the control of the frequency sharing loop filter 245 by using the output signals of the first and second complex multipliers 231 and 232 as inputs. The overall contribution can be controlled by observing the output signals of the multipliers 231 and 232 to control the parameters Kp and Ki of the frequency sharing loop filter 245.

For example, when the attenuation of the pilot signal is large, the first phase error detection unit 241 (depending on the pilot signal when restoring the carrier) reduces the contribution of the phase error generated while the second phase error detection unit ( 242 (not dependent on the pilot signal when reconstructing the carrier) may be controlled to increase the contribution of the phase error generated by the first phase error detection unit 241 to compensate for and overcome the weak point of the carrier reconstruction.

Accordingly, the controller 235 monitors the complex signals input from the first complex multiplier 231 and the second complex multiplier 232 to control the calculation of the phase and frequency error values of the frequency sharing loop filter 245. In addition, a baseband complex signal output from the first and second complex multipliers 231 and 232 is provided to select one of the baseband complex signals.

Thereafter, the signal output through the controller 235 is input to the matching filter 250, and the matching filter 250 removes aliasing included in the baseband complex signal and then inputs the DC eliminator 270. do.

In the above embodiment, the first complex multiplier 231, the first phase error detector 241, the second complex multiplier 232, and the second phase error detector 242 of the carrier recovery unit 230 are rear ends of the symbol timing restorer. Although all are arranged in, it is possible to arrange them in different positions or to place the first and second complex multipliers 231 and 232 in different positions. In other words, the first complex multiplier 231, the first phase error detector 241, the second complex multiplier 232, and the second phase error detector 242 before the symbol timing are restored to the front end of the resampler 211. The rear end of the matching filter 250, the rear end of the DC eliminator 270, or the like may be disposed at different positions.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention, It will be readily apparent to those skilled in the art.

As described above, in the present invention, in a digital broadcast receiver that receives a VSB (Vestigial Sideband) modulation broadcast signal, a frequency offset of a carrier is corrected by using a pilot signal or a baseband complex signal according to a received signal state. Accordingly, the carrier recovery performance is not degraded even in the frequency selective fading channel environment, and the carrier recovery performance is excellent in the selective fading channel environment, thereby improving the performance of the digital room transceiver.

Claims (19)

A carrier recovery apparatus for receiving a passband signal of a specific channel, converting the passband digital signal, and extracting a symbol through carrier recovery, A phase separator which receives the digitally converted passband signal and separates and outputs a passband complex signal of real and imaginary components having different phases; The digital passband complex signal output from the phase separator and the complex complex value of a fixed frequency complex sine wave output from a predetermined numerically controlled oscillator are received and multiplied to convert the digital passband complex signal into a signal of a baseband. A down converter to convert; After receiving the baseband complex signal and detecting the phase error through a plurality of phase error detection units having different phase error detection characteristics, the detected phase errors are accumulated to estimate frequency errors of the plurality of phase error detection units. The complex sinusoid is generated by compensating the frequency error by sharing the estimated frequency error value, and the complex signal is converted into a baseband signal whose frequency offset is corrected by multiplying the generated complex sinusoid by the complex signal passed through the downconverter. Carrier recovery unit; and Installed between the down-converter and the carrier recovery unit, and sample the complex signal passing through the phase separator at 2 times the symbol frequency, analyze the sampled signal to detect the timing error, and adjust the sampling time according to the timing error. And a symbol timing restoring unit for restoring symbol timing and outputting the symbol timing restoring unit to a carrier restoring unit. delete The method according to claim 1, The plurality of phase error detection units may include a first phase error detection unit detecting a phase error by detecting a pilot signal of an input complex signal; And a second phase error detector which detects a phase error by using a form of an input complex signal. The method according to claim 1, The carrier recovery unit includes: parallel-connected first and second complex multipliers for respectively correcting a frequency offset of a baseband complex signal by multiplying a complex signal of a baseband and a complex sine wave corresponding to an estimated frequency error value; A first phase error detection unit detecting a phase error by detecting a pilot signal of a complex signal output through the first complex multiplier; A second phase error detector which detects a phase error using a form of a complex signal output through the second complex multiplier; The frequency error is estimated by accumulating the phase error values output from the first and second phase error detectors, and converting the phase error into a frequency error by adding a phase error by sharing the estimated frequency error value. A frequency shared loop filter for supplying frequency error values to the first and second complex multipliers through an oscillator; And monitoring the complex signals input from the first and second complex multipliers to differentially control the sharing contribution to the phase errors of the first and second phase error detection units input to the frequency sharing loop filter, and to control the first and second complex error signals. And a control unit for selectively controlling the output of the complex signal input from the complex multiplier. The method of claim 4, The first phase error detector may include: a low pass filter configured to receive a complex signal output through a first complex multiplier and extract a pilot signal; A delay unit receiving and delaying a pilot signal of a real component Re (·) output from the low pass filter; A multiplexer configured to receive a pilot signal of a real component from the delay or low pass filter and to selectively output the pilot signal; And a phase error value is detected by multiplying the imaginary component signal (Imag (·)) output from the low pass filter and the real component signal output from the multiplexer, and detecting the phase error value. And a multiplier outputted to the carrier recovery apparatus for a digital broadcast receiver. The method of claim 4, The second phase error detection unit includes: a downsampler for sampling and outputting a baseband complex signal output through the second complex multiplier at a frequency equal to a symbol frequency; An OQAM signal generator for multiplying and receiving a complex signal output from the downsampler and a complex sine wave having a center frequency of 1 / n of a symbol frequency from the outside, and separating the complex signal into an OQAM signal of real and imaginary components; And a phase error calculator configured to extract a phase error value by calculating a phase error value from the OQAM signals of real and imaginary components respectively output from the OQAM signal generators. The method of claim 6, And a 1 / n complex sine wave of the OQAM signal generator is a fixed oscillation signal whose center frequency is 1/4 of a symbol frequency. The method of claim 6, The phase error calculator receives and calculates an OQAM signal of a real component (I (k)) and an imaginary component (Q (k)) output from the OQAM signal generator, respectively, and calculates a phase error value tanh (I (k) * Q). (k))-tanh (Q (k-1 / 2) * I (k-1 / 2)) values for outputting a carrier recovery apparatus for a digital broadcast receiver. The method of claim 6, The second phase error detection unit may include: a second down sampler extracting a phase error value corresponding to the frequency offset output from the phase error calculator as half frequency of a sampling frequency; And sampling the phase error of the baseband inputted from the second downsampler at a symbol frequency rate by increasing the clock speed to match an operating frequency with a portion for compensating the phase of the baseband and outputting the frequency error to the frequency sharing loop filter. The carrier recovery apparatus of the digital broadcast receiver, characterized in that it further comprises an upsampler. The method of claim 4, The frequency sharing loop filter includes: a first Kp multiplier configured to receive and multiply a phase error value of the first phase error detector by a proportional gain control signal output from the controller; A second Kp multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a proportional gain control signal output from the controller; A first Ki multiplier for receiving and multiplying a phase error value of the first phase error detection unit and a cumulative gain control signal output from the control unit; A second Ki multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a cumulative gain control signal output from the control unit; An accumulator for adding the outputs of the first and second Ki multipliers and accumulating phase error values to calculate a frequency error value of a carrier; A first adder for adding a phase error value output from the first Kp multiplier and a frequency error value output from an accumulator to convert the phase error into a frequency error value; And a second adder for adding the phase error value output from the second Kp multiplier and the frequency error value output from the accumulator to convert the phase error into a frequency error value. The method of claim 4, The frequency sharing loop filter includes: a first Kp multiplier configured to receive and multiply a phase error value of the first phase error detector by a proportional gain control signal output from the controller; A second Kp multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a proportional gain control signal output from the controller; A first accumulator for accumulating a phase error value output from the first phase error detector and calculating a frequency error value of a carrier; A second accumulator for accumulating a phase error value output from the second phase error detector and calculating a frequency error value of a carrier; A first Ki multiplier for receiving and multiplying the frequency error value of the first accumulator and the cumulative gain control signal output from the controller; A second Ki multiplier for receiving and multiplying a frequency error value of the second accumulator and a cumulative gain control signal output from a controller; An adder for adding frequency error values output from the first and second Ki multipliers; A first adder for adding a phase error value output from the first Kp multiplier and a frequency error value output from the adder to convert the phase error into a frequency error value; And a second adder for adding a phase error value output from the second Kp multiplier and a frequency error value output from the adder to convert the phase error into a frequency error value. The method according to claim 1, The symbol timing restoring unit may include: a resampler for sampling and outputting a baseband signal output through a down converter at a clock frequency corresponding to two times a predetermined symbol frequency at a transmitter; A passband timing error detection unit configured to extract a signal of an upper band from the signal spectrum generated from the resampler and monitor a state of zero crossing to detect synchronization error of timing; A loop filter which receives the timing error signal output from the passband timing error detection unit and performs low pass filtering; And a numerically controlled oscillator for generating a sampling clock compensated for the error timing according to the signal output from the loop filter and supplying the sample clock to the resampler. A carrier recovery apparatus for receiving a passband signal of a specific channel, converting the passband digital signal, and extracting a symbol through carrier recovery, First and second complex multipliers connected in parallel to each other to correct a frequency offset of the complex signal of the baseband by mutually multiplying the complex signal of the baseband and the complex sine wave corresponding to the estimated frequency error value; A first phase error detection unit detecting a phase error by detecting a pilot signal of a complex signal output through the first complex multiplier; A second phase error detector which detects a phase error using a form of a complex signal output through the second complex multiplier; The frequency error is estimated by accumulating the phase error values output from the first and second phase error detectors, and converting the phase error into a frequency error by adding a phase error by sharing the estimated frequency error value. A frequency shared loop filter for supplying frequency error values to the first and second complex multipliers through an oscillator; And By monitoring the complex signals input from the first and second complex multipliers, differentially controlling the sharing contribution to the phase errors of the first and second phase error detectors input to the frequency sharing loop filter, and the first and second complexes. And a carrier restoring unit including a control unit for selectively controlling an output of a complex signal input from a multiplier. 14. The method of claim 13, The first phase error detector may include: a low pass filter configured to receive a complex signal output through a first complex multiplier and extract a pilot signal; A delay unit receiving and delaying a pilot signal of a real component Re (·) output from the low pass filter; A multiplexer configured to receive a pilot signal of a real component from the delay or low pass filter and to selectively output the pilot signal; And a phase error value is detected by multiplying the imaginary component signal (Imag (·)) output from the low pass filter and the real component signal output from the multiplexer, and detecting the phase error value. And a multiplier outputted to the carrier recovery apparatus for a digital broadcast receiver. 14. The method of claim 13, The second phase error detection unit includes: a downsampler for sampling and outputting a baseband complex signal output through the second complex multiplier at a frequency equal to a symbol frequency; An OQAM signal generator for multiplying and receiving a complex signal output from the downsampler and a complex sine wave having a center frequency of 1 / n of a symbol frequency from the outside, and separating the complex signal into an OQAM signal of real and imaginary components; And a phase error calculator configured to extract a phase error value by calculating a phase error value from the OQAM signals of real and imaginary components respectively output from the OQAM signal generators. 16. The method of claim 15, And a 1 / n complex sine wave of the OQAM signal generator is a fixed oscillation signal whose center frequency is 1/4 of a symbol frequency. 16. The method of claim 15, The phase error calculator receives and calculates an OQAM signal of a real component (I (k)) and an imaginary component (Q (k)) output from the OQAM signal generator, respectively, and calculates a phase error value tanh (I (k) * Q). (k))-tanh (Q (k-1 / 2) * I (k-1 / 2)) values for outputting a carrier recovery apparatus for a digital broadcast receiver. 16. The method of claim 15, The second phase error detection unit may include: a second down sampler extracting a phase error value corresponding to the frequency offset output from the phase error calculator as half frequency of a sampling frequency; And sampling the phase error of the baseband inputted from the second downsampler at a symbol frequency rate by increasing the clock speed to match an operating frequency with a portion for compensating the phase of the baseband and outputting the frequency error to the frequency sharing loop filter. The carrier recovery apparatus of the digital broadcast receiver, characterized in that it further comprises an upsampler. 16. The method of claim 15, The frequency sharing loop filter includes: a first Kp multiplier configured to receive and multiply a phase error value of the first phase error detector by a proportional gain control signal output from the controller; A second Kp multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a proportional gain control signal output from the controller; A first Ki multiplier for receiving and multiplying a phase error value of the first phase error detection unit and a cumulative gain control signal output from the control unit; A second Ki multiplier for receiving and multiplying a phase error value of the second phase error detection unit and a cumulative gain control signal output from the control unit; An accumulator for adding the outputs of the first and second Ki multipliers and accumulating phase error values to calculate a frequency error value of a carrier; A first adder for adding a phase error value output from the first Kp multiplier and a frequency error value output from an accumulator to convert the phase error into a frequency error value; And a second adder for adding the phase error value output from the second Kp multiplier and the frequency error value output from the accumulator to convert the phase error into a frequency error value.

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