KR20040106771A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor display panel and a method for manufacturing the same are provided to increase the optical transmittance by forming the thin protection layer on the top of the pixel opening part. CONSTITUTION: A thin film transistor display panel includes an insulation substrate, a gate line(121), a gate insulation layer, a semiconductor layer, a data line(171), a protection layer and a pixel electrode(190). The insulation substrate is provided with a trench. The gate line is formed on th insulation substrate. The gate insulation layer formed on the gate line. The semiconductor layer is formed on the gate insulation layer. The data line is formed on the gate insulation layer and is provided with a data line, a source electrode connected to the data line and the drain electrode facing to the source electrode. The protection layer is formed on the data line. And, the pixel electrode is formed on the protection layer and is electrically connected to the drain electrode.

Description

Thin film transistor array panel and manufacturing method thereof {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array panel for a liquid crystal display device for improving light transmittance of a liquid crystal display device and a method of manufacturing the same.

The liquid crystal display is one of the flat panel display devices most widely used at present, and includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. Voltage is applied to both electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is changed to rearrange the liquid crystal molecules of the liquid crystal layer, thereby controlling the transmittance of transmitted light to display an image.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two display panels and switching a voltage applied to the electrode is one of the liquid crystal display devices, and one of the two substrates includes a plurality of wirings such as a gate line and a data line. A thin film transistor is formed to remove the pixel electrode and the data signal transmitted to the pixel electrode (hereinafter referred to as a thin film transistor display panel), and the other display panel has a common electrode facing the pixel electrode, and red (R) and green (G). In general, a blue (B) color filter is formed.

In order to improve the brightness of such a liquid crystal display device, securing a high aperture ratio is an important problem. To this end, in manufacturing a liquid crystal display device, an organic insulating film is formed between the wiring and the wiring or the electrode to insulate the conductive wiring from each other. In recent years, since the coupling capacitance generated between the data line and the pixel electrode is large, the thickness of the organic insulating film has been increased. Is formed thick to realize a high opening ratio of the thin film transistor.

However, in the method of manufacturing the liquid crystal display device, in order to connect the drain electrode and the pixel electrode of the thin film transistor, a contact hole must be formed in the organic insulating film. The organic insulating films are all organic films, and since they are too thick, It is difficult to form contact holes with good profiles. Further, due to the organic insulating film formed between the gate insulating film and the pixel electrode, the data line can be protected from the etching process for forming the pixel electrode pattern, but the light transmittance is reduced due to the thickness of the organic insulating film.

An object of the present invention is to provide a thin film transistor array panel which can improve the light transmittance of a liquid crystal display.

1A is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

1B and 1C are cross-sectional views taken along lines Ib-Ib 'and Ic-Ic' of FIG. 1A, respectively.

2A through 6C are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention according to a process sequence.

In order to solve this problem, the present invention provides the following thin film transistor array panel.

An insulating substrate having a trench, a gate wiring formed on the insulating substrate and including a gate line and a gate electrode, a gate insulating film formed on the gate wiring, a semiconductor layer formed on the gate insulating film, and formed on the semiconductor layer And a data line formed in the trench, the data line including a data line formed along the trench, a source electrode connected to the data line, and a drain electrode facing the source electrode on the semiconductor layer. A thin film transistor array panel is formed on the passivation layer and the pixel electrode formed on the passivation layer and electrically connected to the drain electrode.

At this time, the trench of the insulating substrate is preferably formed in a reverse tapered structure having both sides of the inclination angle of 60 ° or less.

In addition, the trench of the insulating substrate is preferably formed to have a depth of 1-3㎛.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. In contrast, when a part is just above another part, it means that there is no other part in between.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1A is a layout view illustrating a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views taken along lines Ib-Ib and Ic-Ic ′ of FIG. 1A.

1A to 1C, a plurality of trenches are formed in the insulating substrate 110 of the thin film transistor array panel according to the exemplary embodiment at regular intervals. In this case, the trenches are formed in portions where the data lines to be described later will be formed to form side by side stripes.

The gate line 121 and the storage electrode line 131 are formed directly on the insulating substrate 110.

The gate line 121 is elongated in the horizontal direction and includes a gate electrode 124 that is a part of the gate line 121. At this time, one end portion 129 of the gate line 121 is extended in width for connection with an external circuit.

The storage electrode line 131 overlaps the pixel electrode 190, which will be described later, and the storage conductor 177 connected to the pixel electrode 190, to form a storage capacitor that improves the charge retention ability of the pixel, and the pixel electrode 190 and the gate If the holding capacity generated by the overlap of the lines 121 is sufficient, it may not be formed.

The gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131, and the semiconductor layer 151 and the ohmic contact layer 160 are formed on the gate insulating layer 140. The ohmic contact layer 160 is formed on the linear semiconductor 151 in such a pattern and has two island-type ohmic contact members facing each other with respect to the gate electrode 124 and the linear ohmic contact member 161. 163, 165).

The data line 171 is formed on the ohmic contact layer 160 and the gate insulating layer 140. In this case, the data line 171 is formed along the trench inside the trench of the substrate 110.

Here, the data line 171 is a first metal layer 711, 731, 751, 791 made of Cr or Mo alloy or the like and a second metal layer 712, 732, 752, 792 made of Al or Ag alloy having a low resistance. It consists of a double layer of.

The data line 171 vertically intersects the gate line 121 to define a pixel region, is a branch of the data line 171, and is connected to the ohmic contact layer 163 and the source electrode 173 and the source electrode 173. And a drain electrode 175 formed on the island-like ohmic contact layer 165 opposite to the source electrode 173 with respect to the gate electrode 123. One end portion 179 of the data line 171 is extended in width for connection with an external circuit.

The data line 171, the storage conductor 177, and the ohmic contact layer 160 are formed in the same planar pattern, and the semiconductor layer 151 is formed in the same planar pattern except for the island type semiconductor 154, which is a channel part. . That is, although the source electrode 173 and the drain electrode 175 are separated from the island type semiconductor 154 serving as the channel part, and the ohmic contact layers 163 and 165 disposed under the source and drain electrodes 173 and 175 are separated, The island semiconductors 154, which are channel portions, are connected without being separated to form channels of the thin film transistors.

A passivation layer 180 made of an organic material is formed on the data line 171 and the gate insulating layer 140. In this case, since the data line 171 is recessed and formed in the trench, the passivation layer 180 is thickly formed on the data line 171, and the passivation layer 180 is thinly formed on the gate insulating layer 140, which is a pixel opening. It is.

In the passivation layer 180, the first contact hole 181 exposing one end portion 129 of the gate line 121 and the second contact hole 182 exposing one end portion 179 of the data line 171. And a third contact hole 185 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 through the third contact hole 185 and the one end portion 129 of the gate line 121 through the first contact hole 181 on the passivation layer 180. And a data contact assistant member 82 connected to one end portion 179 of the data line 171 through the gate contact assistant member 81 and the second contact hole 182 connected to each other.

The pixel electrode 190 and the gate and data contact auxiliary members 81 and 82 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Next, a method of manufacturing a thin film transistor having such structural features will be described in detail with reference to FIGS. 2A to 6C.

First, as illustrated in FIGS. 2A and 2C, trenches are formed through photolithography in regions where data lines of the insulating substrate 110 are to be formed. At this time, the etching proceeds to wet etching using an etching solution such as HF, and the trench is formed in an inverted taper structure having an inclination angle of 60 ° or less on both sides with a depth of 2-3 μm.

And sputtering a first metal layer (not shown) made of Cr or Mo alloy or the like and a second metal layer (not shown) made of Al or Ag alloy having low resistance on the insulating substrate 110 having the trench formed therein. By successive lamination and dry or wet etching in a first photolithography process using a mask, a gate line 121 and a storage electrode line 131 are formed on the substrate 110.

The gate line 121 is formed to be elongated in the horizontal direction and includes a gate electrode 124 that is a part of the gate line 121. At this time, one end portion 129 of the gate line 121 is extended in width for connection with an external circuit. The storage electrode line 131 overlaps the pixel electrode 190, which will be described later, and the storage conductor 177 connected to the pixel electrode 190, to form a storage capacitor that improves the charge retention ability of the pixel, and the pixel electrode 190 and the gate If the holding capacity generated by the overlap of the lines 121 is sufficient, it may not be formed.

3A and 3B, the gate insulating layer 140 made of silicon nitride, the amorphous silicon layer 150 which is not doped with impurities, and the dopants are doped on the gate line 121 and the storage electrode line 131. The semiconductor layers 160 are sequentially stacked by chemical vapor deposition. Subsequently, the first metal layer 701 made of Cr or Mo alloy or the like and the second metal layer 702 made of Al or Ag alloy having a low resistance are successively laminated by a method such as sputtering.

As shown in FIGS. 4A and 4B, after forming the photoresist film PR directly on the second metal layer 702, the photoresist film pattern PR having a portion where the entire thickness is exposed and a portion where the thickness is partially exposed is formed. Form.

Subsequently, when the photoresist pattern PR is developed, a portion A positioned between the channel portion of the thin film transistor, that is, the source electrode 173 and the drain electrode 175 is thicker than the portion positioned in the portion B where the data line is to be formed. It becomes small and all the photosensitive films of other parts are removed. At this time, the thickness of the photosensitive film remaining in the channel portion and the thickness of the photosensitive film remaining in the data line portion is preferably such that the former thickness is 1/2 or less of the latter thickness, for example, 4000 kPa or less.

As shown in FIGS. 5A to 5C, the photoresist pattern PR and the films below it, that is, the first and second metal layers 701 and 702, the amorphous silicon layer 150, and the semiconductor layer 160 doped with impurities ) Is sequentially etched to form the data line 171, the ohmic contact layer 160, and the semiconductor including the first metal patterns 711, 731, 751, and 791 and the second metal patterns 712, 732, 752, and 792. Form layer 151.

In more detail, the etching using the photoresist pattern PR as a mask is performed in multiple steps. First, the semiconductor layer 160 doped with impurities is exposed by wet etching a region (third portion C) where the photoresist pattern PR is not formed to remove the second metal layer 702 and the first metal layer 701. . At this time, the wet etching is performed to etch the second metal layer 702 and the first metal layer 701 at the same time by using an acid in which acetic acid, phosphoric acid and nitric acid are mixed in an appropriate ratio.

Thereafter, along with the photoresist pattern PR of the first portion A, the ohmic contact layer 160 which is a semiconductor layer doped with impurities of the third portion C and the semiconductor layer 150 that are not doped with impurities are dry-etched. The semiconductor layer is completed and an ohmic contact layer in which the channel portion is not separated is formed. At this time, the photosensitive layer of the second part B is also partially etched.

Next, the photosensitive layer is ashed to remove the first portion A, thereby exposing the second metal layer 702 over the channel portion.

Subsequently, the second metal layer 702, the first metal layer 701, and the ohmic contact layer 160 of the first portion A are etched to form the first metal patterns 711, 731, 751, and 791 and the second metal pattern. The data line 171, the ohmic contact layer 160, and the semiconductor layer 151 formed of the 712, 732, 752, and 792 are formed. In this case, a portion of the semiconductor layer 150 of the first portion A and the photoresist pattern PR of the second portion B may be etched. Subsequently, the photosensitive layer PR of the second part B is removed.

At this time, the data line 171 is formed on the bottom surface of the trench having a depth of 2-3 μm previously formed on the insulating substrate 110.

6A through 6C, an organic material is deposited on a substrate including the data line 171 to form a passivation layer 180. In this case, the passivation layer 180 is thickly formed on the data line 171 formed in the trench, and the passivation layer 180 is formed thinly in the portion where the pixel electrode 190 is to be formed. Accordingly, a coupling problem that may occur between the data line 171 and the pixel electrode 190 is solved, and a decrease in transmittance caused by the passivation layer 180 is reduced, thereby improving light transmittance.

Next, first to third contact holes 181, 182, and 185 are formed by a photolithography process (third mask).

Thereafter, a conductive layer is formed of ITO or IZO, which is a transparent conductive material, on the entire surface of the substrate including the first to third contact holes 181, 182, and 185, and then patterned to form a drain electrode 175 and a pixel electrode 190. The gate contact auxiliary member 81 connected to one end 129 of the gate line 121 and the data contact auxiliary member 82 connected to one end 179 of the data line 171 are formed. (The fourth mask)

The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 185, and the gate contact auxiliary member 81 is connected to one end portion 129 of the gate line through the first contact hole 181. The data contact auxiliary member 82 is connected to one end 179 of the data line through the second contact hole 182 and the redundant data line 83 is connected to the data line 171 through the contact portion 188. Connection (see FIGS. 1A-1C).

Although the preferred embodiments of the present invention have been described in detail as described above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the present invention.

As described above, the present invention solves the coupling problem occurring between the data line and the pixel electrode by forming a data line in the trench to form a thick protective film on the data line, and increases the aperture ratio and at the same time a protective film on the pixel opening. It can be formed thin to increase the light transmittance.

Claims (5)

An insulated substrate having a trench, A gate wiring formed on the insulating substrate and including a gate line and a gate electrode; A gate insulating film formed on the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the semiconductor layer and including a data line formed in the trench along the trench, a source electrode connected to the data line, and a drain electrode facing the source electrode on the semiconductor layer; A protective film formed on the data wiring, And a pixel electrode formed on the passivation layer and electrically connected to the drain electrode. In claim 1, The trench has a thin film transistor array panel having a reverse tapered structure having both sides having an inclination angle of 60 ° or less. The method of claim 1 or 2, And the trench is formed to have a depth of 1-3 μm. Forming a trench through photolithography in a region where a data line of the insulating substrate is to be formed; Forming a gate wiring including a gate line and a gate electrode on the insulating substrate; Forming a gate insulating film on the gate wiring; Forming a semiconductor layer on the gate insulating film, Forming a data line on the semiconductor layer, the data line including a source electrode facing the drain electrode on the gate electrode; Forming a protective film having a contact hole on the data line; Forming a pixel electrode connected to the drain electrode through the contact hole Method of manufacturing a thin film transistor array panel comprising a. In claim 4, The forming of the trench may be performed by performing a wet etching process with an HF solution.