KR20040095921A - Pull-up pre-driver and pull-down pre-driver in semiconductor device - Google Patents

Abstract

PURPOSE: A pull-up pre-driver and a pull-down pre-driver of a semiconductor device are provided to save the time and cost for analyzing the failure of the slew rate by finely adjusting the slew rate of the output driver. CONSTITUTION: A pull-up pre-driver(50) and a pull-down pre-driver(51) of a semiconductor device includes a first PMOS transistor(P52) and a first NMOS transistor(N51), a plurality of resistors(R51-R54) and a second NMOS transistor(N52). The first PMOS transistor(P52) and a first NMOS transistor(N51) form an inverter structure by utilizing the pull-up signal as a common gate input and connecting each of the sources between the power voltage terminal and the ground voltage terminal. The plurality of resistors(R51-R54) is connected between the drain of the first PMOS transistor(P52) and the drain of the first NMOS transistor(N51). The drain of the second NMOS transistor(N52) is connected one of the drain of the PMOS transistor(P52), the drain of the first NMOS transistor(N52) or the connection nodes between each of the resistors and the source of the second NMOS transistor(N52) is connected to the ground voltage terminal. And, the second NMOS transistor(N52) utilizes the pull-up signal as the gate input.

Description

PULL-UP PRE-DRIVER AND PULL-DOWN PRE-DRIVER IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to an output driver of a DRAM (Dynamic Random Access Memory). More particularly, a pull-up capable of fine-adjusting a slew rate is possible. / Pull-down) output driver.

In general, a semiconductor memory device such as DRAM receives an externally applied X and Y address signal, selects one of a plurality of cell capacitors, and converts the stored charge into a voltage to be amplified through a series of amplification processes. Then pass it to the outside.

In addition, at the same time as the address, the voltage input corresponding to the data from the outside is stored in a designated cell capacitor in the form of a charge.

The DRAM includes various circuits of various paths to quickly and accurately amplify a minute signal by quickly accessing a desired cell among a plurality of cell capacitors.

For example, in order to export data amplified by reading from a memory cell to a global input / output (GIO) signal during a DRAM read operation, data DQ and data are required as a main data output driver is required. An output driver is always required to drive the strobe DQS.

1 is a block diagram illustrating an output driver for driving internal data input during a read operation of a DRAM.

Referring to Fig. 1, pre-drivers 10 and 12 and output drivers 11 and 13 are provided for outputting data DQ read out from a cell, and they are also pull-up and have high-level data. Pull-up pre-driver 10 and pull-up driver 11 for outputting only, pull-down pre-driver 12 and pull-down driver 13 for outputting only low-level data in a pull-down manner. Are each made of.

On the other hand, the DRAM has a maximum and minimum driving current (ie, threshold of power consumption) so as to meet both the use of the main memory (Main memory) or graphics memory (Graphic memory). Therefore, the outputs of the pre-drivers 10 and 12 are divided into up1b, up2b and up3b, and dn1, dn2 and dn3, respectively, so as to be selectively used according to each use.

Thus, when used as main memory, all three outputs of the predriver can be used, and when used as graphics memory, only up2b and up3b and dn2 and dn3 can be used. For example, in DRAM, up1b and dn1 have more drive current than the other two outputs plus.

FIG. 2 is a detailed circuit diagram illustrating the pull-up pre-driver and the pull-up output driver of FIG. 1 according to the prior art.

Referring to FIG. 2, the pull-up pre-driver 10 is a PMOS transistor P1, P2, P3 having an inverter structure, an NMOS transistor N1, N2, N3, and a series of pull-ups connected between these two transistors. Resistors R1 and R2 (R3 and R4 or R5) that cause the signals up1b, up2b, and up3b to transition to a low level when the signal (or input data; up1, up2, up3) transition to a high level; R6), the pull-up signals up1, up2, up3 are input to the gates of the PMOS transistors P1, P2, P3 and the NMOS transistors N1, N2, N3.

Accordingly, the pull-up pre-driver 10 includes a first pre-driver 10a outputting up1b, a second pre-driver 10b outputting up2b and a third pre-driver 10c outputting up3b.

The pull-up output driver 11 is made up of a PMOS transistor having up1b, up2b and up3b as gate inputs, a source of which is connected to a power supply voltage terminal VDDQ, and outputting an output signal DQ (data) to a drain.

The first output driver 11a is composed of four PMOS transistors P4, P5, P6, and P7 whose gate input is up1b, and the second output driver 11b has two PMOS transistors whose gate input is up2b ( It consists of P8 and P9, and the 3rd output driver 11c consists of two PMOS transistors P10 and P11 which use up3b as a gate input.

Here, the output of the first pre-driver 10a is connected to the gates of more PMOS transistors than the second pre-driver 10b and the third pre-driver 10c, and thus the capacitance thereof is large. Therefore, it is common to increase the resistance values of R3, R4, R5 and R6 larger than R1 and R2 in order to match the time constant (R * C).

DQ (data) is transitioned to high level, i.e., pulled up with a constant slew rate when up1 transitions from low level to high level.

On the other hand, between the resistors R1 and R2, R3 and R4, and R5 and R6, switches S1 to S6 are connected in parallel to each resistor.

Therefore, when the up signal transitions to a high level through the on-off of the switch, the falling slope of the upb signal can be adjusted by adjusting the amount of current flowing through the NMOS transistor to the ground voltage terminal VSSQ.

The operation of the first pre-driver 10a will be described.

First, when up1 is at the low level, N1 is turned off and P1 is turned on, so up1b is maintained at the high level. Subsequently, when up1 transitions from low level to high level, P1 is turned off and N1 is turned on so that the voltage level of up1b through the current path flowing through R1, R2 and N1 to VSS is a constant slope (i.e., slew rate). Transitions to low level (pull-down).

At this time, if S1 is closed, a current path passing through R2 and N1 is formed, and up1b transitions to a lower level faster than passing through both R1 and R2. If both S1 and S2 are closed, up1b does not go through the resistor immediately. A current path is formed with VSSQ to transition from high level to low level with little slope (right angle).

Therefore, the slew rate can be adjusted through the on-off operation of the switch.

3 is a detailed circuit diagram illustrating the pull-down pre-driver and pull-down output driver of FIG. 1 according to the prior art.

Referring to FIG. 3, the pull-down pre-driver 12 is connected in series between the PMOS transistors P12, P13, and P14 having the inverter structure and the NMOS transistors N4, N5, and N6 and these two transistors, and is pull-downed. When the signals (or input data; dn1b, dn2b, dn3b) are transitioned to have a low level, the resistors R7 and R8 (R9 and R10 or R11 and so that the signals dn1, dn2 and dn3 that transition to a low level have a constant slew rate; R12), pull-down signals dn1b, dn2b, and dn3b are input to the gates of the PMOS transistors P12, P13, and P14 and the NMOS transistors N4, N5, and N6.

Accordingly, the pull-down pre-driver 12 includes a fourth pre-driver 12a for outputting dn1, a fifth pre-driver 12b for outputting dn2, and a sixth pre-driver 12c for outputting dn3.

The pull-down output driver 14 is composed of NMOS transistors having dn1, dn2 and dn3 as gate inputs, a source connected to a ground voltage terminal VSSQ, and outputting an output signal DQ (data) to a drain.

The fourth output driver 13a is composed of four NMOS transistors N7, N8, N9, N10 having dn1 as a gate input, and the fifth output driver 13b has two NMOS transistors having dn2 as a gate input. N11 and N12, and the sixth output driver 13c includes two NMOS transistors N13 and N14 having dn3 as a gate input.

Here, the output of the fourth pre-driver 12a is connected to the gates of more NMOS transistors than the fifth pre-driver 12b and the sixth pre-driver 12c, and thus the capacitance thereof is large. Therefore, it is common to increase the resistance of R9, R10 and R11 and R12 larger than R7 and R8 in order to match the time constant (R * C).

Thus, when dn1b transitions from high level to low level, the DQ (data) transitions to the low level with a constant slew rate, i.e., pulls down, by the resistors R7 and R8 connected in series.

On the other hand, between the resistors R7 and R8, R9 and R10, and R11 and R12, switches S7 to S12 are connected in parallel to each resistor.

Therefore, when the dnb signal transitions to the low level through the on-off of the switch, the rising slope of the dn signal can be controlled by adjusting the amount of current flowing through the PMOS transistor to the power supply voltage terminal VDD.

The operation of the fourth pre-driver 12a will be described.

First, when dn1b is high level, P12 is turned off and N4 is turned on, so dn1 maintains a low level. Subsequently, when dn1b transitions from high level to low level, N4 is turned off and P12 is turned on so that the voltage level of dn1 has a constant slope (i.e., slew rate) through the current path flowing through R7, R8 and P12 to VDDQ. Transitions to a high level with ().

At this time, if S8 is closed, a current path passing through R7 and P12 is formed, and dn1 transitions to a higher level faster than passing through both R7 and R8, and closing both S7 and S8 causes dn1 to go straight through without resistance. A current path is formed with VDDQ to transition from low level to high level with little slope (right angle).

Therefore, the slew rate can be adjusted through the on-off operation of the switch.

FIG. 4 is a timing diagram illustrating rising and falling of data and data strobes during data read in DRAM.

Referring to FIG. 4, when data read by a read command is output while the voltage VTT level of the high impedance is initially output, the rising and falling are repeatedly output.

At this time, the data can be seen that the movement with a constant slope when rising and falling, as shown in Fig. A indicates the slope at the time of rising, B is the slope at the time of falling, the magnitude of this slope immediately represents the slew rate.

That is, the larger the slew rate, the larger the magnitude of the slope, and the smaller the slew rate, the smaller the magnitude of the slope.

This slew rate can be controlled by adjusting the inclination of the output of the pre-driver in FIGS. 2 and 3 described above, and in FIGS. 2 and 3 through short circuits of resistors connected in series and switches connected in parallel with each resistor. Controlled.

However, the method described above is greatly inferior in precision. That is, the amount of change in the slew rate is large depending on whether the resistor is connected or disconnected.

Therefore, it is difficult to control the slew rate to the specification, and if you want to control the slew rate more precisely through the above-described conventional method, the resistance connected to the drain of the transistor is further refined, It would be possible to make many switch options parallel to the resistor.

However, when using such a method, the area occupied by the circuit becomes too large, resulting in a problem of lowering the degree of integration.

The present invention has been proposed to solve the conventional problems as described above, and provides a pull-up pre-driver and a pull-down pre-driver of a semiconductor device to enable fine adjustment of the slew rate without degrading the density. For that purpose.

1 is a block diagram showing an output driver for driving internal data input during a read operation of a DRAM.

FIG. 2 is a detailed circuit diagram illustrating the pull-up pre-driver and pull-up output driver of FIG. 1 according to the prior art. FIG.

3 is a detailed circuit diagram illustrating the pull-down pre-driver and pull-down output driver of FIG. 1 according to the prior art.

Fig. 4 is a timing chart showing rise and fall of data and data strobes during data read in DRAM.

5 is a detailed circuit diagram illustrating a pull-up pre-driver and a pull-up output driver according to an embodiment of the present invention.

6 is a detailed circuit diagram illustrating a pull-down pre-driver and a pull-down output driver according to an embodiment of the present invention.

7 is a timing diagram illustrating the operation of the pull-up and pull-down drivers of FIGS. 5 and 6 and the output driver of FIG. 1 including them;

* Explanation of symbols for the main parts of the drawings

50: pull-up pre-driver 51: pull-up output driver

60: pull-down pre-driver 61: pull-down output driver

A first PMOS transistor and a first NMOS transistor having a pull-up signal as a common gate input and each source connected between a power supply voltage terminal and a ground voltage terminal to form an inverter structure for achieving the above object; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And a drain connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source connected to a ground voltage terminal, and the pull-up signal serving as a gate input. A pull-up pre-driver of a semiconductor device including a 2NMOS transistor is provided.

In addition, the present invention for achieving the above object, the pull-up signal as a common gate input, each source is connected between the power supply voltage terminal and the ground voltage terminal, the first PMOS transistor and the first NMOS transistor; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And a drain is connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source is connected to a ground voltage terminal, and the pull-up signal is input to a common gate input. A pull-up pre-driver of a semiconductor device including a plurality of second NMOS transistors is provided.

In addition, the present invention for achieving the above object, the first PMOS transistor and the first NMOS transistor having a pull-down signal as a common gate input, each source is connected between the power supply voltage terminal and the ground voltage terminal to form an inverter structure; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And a drain connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source connected to a power supply voltage terminal, and the pull-down signal serving as a gate input. A pull-down pre-driver of a semiconductor device including a 2NMOS transistor is provided.

In addition, the present invention for achieving the above object, the first PMOS transistor and the first NMOS transistor having a pull-down signal as a common gate input, each source is connected between the power supply voltage terminal and the ground voltage terminal; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And a drain is connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source is connected to a power supply voltage terminal, and the pull-down signal is input to a common gate input. A pull-down pre-driver of a semiconductor device including a plurality of second NMOS transistors is provided.

According to the present invention, by adding a drain of a pull-up and pull-down pre-driver having an inverter structure or a plurality of transistors having a drain connected between series connected resistors, not only the value of the resistor, the number of resistors, and the number of switches are available. Rather, simple transistors allow fine tuning of the output driver's slew rate.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

5 is a detailed circuit diagram illustrating a pull-up pre-driver and a pull-up output driver according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the inverted signal upb of the pull-up signal is output by using the pull-up signal up, and a plurality of fine slew rates can be finely adjusted when the pull-up signal is high level. A pull-up pre-driver 50 including a series connected resistors R51 to R54 and switches S51 to S54 and a plurality of NMOS transistors N51 to N53 connected in parallel to correspond to the respective resistors. A plurality of PMOS transistors P52 having an output signal upb of the up pre-driver 50 as a common gate input, a source commonly connected to the power supply voltage terminal VDDQ, and a drain commonly connected to the output terminal to output a pull-up DQ (data) signal. A pull-up output driver 51 including P55) is provided.

Specifically, the pull-up pre-driver 50 uses a pull-up signal as a common gate input, and a PMOS transistor P51 (hereinafter referred to as P51) and an NMOS in which each source is connected between VDDQ and VSSQ to form an inverter structure. The plurality of resistors R51 to R54 connected in series between the transistor N51 (hereinafter referred to as N51), the drain of P51 and the drain of N51, and the plurality of switches S51 to S54 connected in parallel to the resistors R51 to R54. And a drain connected to a drain of P51, a source connected to VSSQ, and a NMOS transistor N53 (hereinafter referred to as N53) having a pull-up signal up as a gate input, and a drain connected to a node between R52 and R53. It includes an NMOS transistor N52 (hereinafter referred to as N52) that is connected to VSSQ and whose pull-up signal up is the gate input.

6 is a detailed circuit diagram illustrating a pull-down pre-driver and a pull-down output driver according to an embodiment of the present invention.

Referring to FIG. 6, an inverted signal dn of the pull-down signal is output by using the pull-down signal dnb as an input, and fine adjustment of the rising slew rate when the pull-down signal dnb is low level is possible. A pull-down pre-driver 60 including a plurality of series-connected resistors R61 to R64 and switches S61 to S64 connected in parallel to correspond to the respective resistors, and a plurality of PMOS transistors P61 to P63; A plurality of NMOS transistors outputting a pull-down DQ (data) signal by using the output signal dn of the down-down pre-driver 60 as a common gate input, a source commonly connected to the ground voltage terminal VDDQ, and a drain commonly connected to the output terminal. A pull-down output driver 61 including (N62 to N65) is provided.

Specifically, the pull-down pre-driver 60 uses a pull-down signal dnb as a common gate input, and a PMOS transistor P61 (hereinafter referred to as P61) in which each source is connected between VDDQ and VSSQ to form an inverter structure, and NMOS transistor N61 (hereinafter referred to as N61), a plurality of resistors R61 to R64 connected in series between the drain of P61 and the drain of N61, and a plurality of switches S61 to S64 connected in parallel to the resistors R61 to R64. ), A drain is connected to a drain of N61, a source is connected to VDDQ, a PMOS transistor P63 (hereinafter referred to as P63) having a pull-down signal dnb as a gate input, and a drain is connected to a node between R62 and R63. Is connected to VDDQ and includes a PMOS transistor P62 (hereinafter referred to as P62) whose gate input is the pull-down signal dnb.

7 is a timing diagram illustrating the operation of the pull-up and pull-down drivers of FIGS. 5 and 6 and the output driver of FIG. 1 including them.

First, the operation of the pull-up pre-driver 50 and the pull-up output driver 51 of FIG. 5 will be described with reference to FIG. 7.

When up is low level, N51 is turned off and P51 is turned on, so upb remains high.

Subsequently, when up transitions from low level to high level, P51 is turned off and N51, N52 and N53 are turned on so that the paths of R51 to R54 and N51, the paths of R51, R52 and N52, and 3 only through N53 A current path is formed through the branch path so that the voltage level of upb transitions (pulls down) to a low level with a constant slope (ie, slew rate). At this time, since the current path of N53 has a small resistance, this current path plays a leading role.

On the other hand, in the absence of N53, the paths of R51, R52, and N52 will be dominant. At this time, if S51 is closed, a current path through only R52 and N52 will be formed, and upb will go low faster than both R51 and R52. When both S1 and S2 are closed, the upb transitions from high level to low level with almost no inclination (perpendicularly) as with the current path through N53, as upb immediately forms a current path through VSSQ without going through a resistor. .

Therefore, not only the on-off operation of the conventionally connected resistors R51 to R54 and the switches S51 to S54, but also the slew rate can be adjusted through N51 to N53, so that finer adjustment is possible. In FIG. 7, it can be seen that the upb changes the slew rate in the direction of the arrow according to the increase in the resistance component in the current path when the up signal is generated. At this time, P52 to P55 are turned on and pulled up to have a constant (adjustable) slab. It can be seen that a DQ (data) signal having a run rate is output.

Next, the operation of the pull-down pre-driver 60 and the pull-down output driver 61 of FIG. 6 will be described with reference to FIG. 7.

When dnb is high level, P61 is turned off and N61 is turned on, so dn remains low.

Subsequently, when dnb transitions from high level to low level, N61 is turned off and P61, P62, and P63 are turned on, so that the path passes through P61, R61 through R64 at VDDQ, and passes through P62, R63, and R64 at VDDQ. And a current path is formed through the three paths through P63 only at VDDQ so that the voltage level of dn transitions (pulls up) to a high level with a constant slope (ie, slew rate). At this time, since the current path of P63 has a small resistance, this current path plays a leading role.

On the other hand, if there is no P63, the path through P62, R63, and R64 will be dominant. At this time, if S63 is closed, a current path passing through only P62 and R64 is formed, so that dn is faster than going through both R63 and R64. When both S63 and S64 are closed, dn is immediately passed through VDDQ without any resistance, and transitions from low level to high level with almost no inclination (right angle), similar to the current path through P63. do.

Therefore, the slew rate can be adjusted not only through the on-off operation of the resistors R61 to R64 and the switches S61 to S64 connected in series, but also to fine adjustment. In FIG. 7, dn shows that the slew rate changes in the direction of the arrow as the resistance component in the current path increases when the dnb signal is generated. In this case, N62 to N65 are turned on, pull-down, and a constant (adjustable) slab. It can be seen that a DQ (data) signal having a run rate is output.

Therefore, the output DQO of the output driver using the pull-up / pull-down method of FIG. 1 has a time delay tSL1 corresponding to the slew rate due to the pull-up on the rise, as shown in FIG. It has a time delay tSL2 corresponding to the slew rate by the pull-down.

In addition, the slew rate may be adjusted by varying the resistance values of the series resistors of FIGS. 5 and 6.

According to the present invention made up of the above, the output of the output driver without increasing the switch option by adding a drain of the pull-up and pull-down pre-driver having the inverter structure or a drain connected between the series-connected resistor. It was found through the examples that the slew rate can be fine tuned.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

According to the present invention, the slew rate of the output driver can be finely adjusted so that the slew rate can be easily satisfied with the specification, thereby reducing the time and cost for fail analysis of the slew rate. You can expect the effect.

Claims (6)

A first PMOS transistor and a first NMOS transistor having a pull-up signal as a common gate input and each source connected between a power supply voltage terminal and a ground voltage terminal to form an inverter structure; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And A second NMOS having a drain connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source connected to a ground voltage terminal, and a pull-up signal serving as a gate input; transistor Pull-up pre-driver of the semiconductor device comprising a. A first PMOS transistor and a first NMOS transistor having a pull-up signal as a common gate input and each source connected between a power supply voltage terminal and a ground voltage terminal to form an inverter structure; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And Each drain is connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, and a source is connected to a ground voltage terminal, and the pull-up signal is connected to a common gate input. A plurality of second NMOS transistors Pull-up pre-driver of the semiconductor device comprising a. The method according to claim 1 or 2, And a plurality of switches connected in parallel to the plurality of resistors. A first PMOS transistor and a first NMOS transistor having a pull-down signal as a common gate input and each source connected between a power supply voltage terminal and a ground voltage terminal to form an inverter structure; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And A second NMOS having a drain connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source connected to a power supply voltage terminal, and the pull-down signal serving as a gate input; transistor Pull-down pre-driver of the semiconductor device comprising a. A first PMOS transistor and a first NMOS transistor having a pull-down signal as a common gate input and each source connected between a power supply voltage terminal and a ground voltage terminal to form an inverter structure; A plurality of resistors connected in series between the drain of the first PMOS transistor and the drain of the first NMOS transistor; And Each drain is connected to any one of a drain of the first PMOS transistor, a drain of the first NMOS transistor, or a connection node between the respective resistors, a source is connected to a power supply voltage terminal, and the pull-down signal is connected to a common gate input. A plurality of second NMOS transistors Pull-down pre-driver of the semiconductor device comprising a. The method according to claim 4 or 5, And a plurality of switches connected in parallel to the plurality of resistors.