JP3289428B2 - Bus systems and integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of integrated circuits each having a signal input / output terminal connected to an output terminal of an output circuit composed of a tristate circuit (ternary logic circuit) connected to a common bus line. And the terminal of the bus line is terminated with a terminating resistor to which a terminating voltage of the same or substantially the same voltage as the reference voltage used for determining the logic of the signal input to the signal input / output terminal is supplied. The present invention relates to a bus system and an integrated circuit suitable for use in such a bus system.

[0002]

2. Description of the Related Art FIG. 1 shows a main part of an example of a bus system.
t), 2 to 5 are SDRAMs (sync) adapted to take in various signals in synchronization with a clock signal supplied from the outside.
hronous dynamic random access memory), 6 is a bus line.

In recent years, as a small signal transmission method used in such a bus system, T-LVTTL has been used.
(Terminated low voltage transisitor transisitor l
ogic) transmission method or CTT (center tapped termin)
ation) A small signal transmission method called a transmission method has been proposed.

FIG. 25 is a circuit diagram showing a T-LVTTL transmission system. In the figure, reference numeral 8 denotes an integrated circuit for transmitting a signal, 9 denotes a push-pull circuit which is a final stage of an output circuit comprising a tri-state circuit, and 10 denotes a signal output terminal.

In the push-pull circuit 9, 11
Is a VCC power supply line for supplying 3 [V] as a power supply voltage VCC, 12 is an enhancement type pMOS transistor serving as a pull-up element, and 13 is an enhancement type nMOS transistor serving as a pull-down element.

Reference numeral 14 denotes a bus line forming a signal transmission path;
Reference numeral 5 denotes a terminating resistor, for example, a resistor of 50Ω, and 16 denotes a terminating voltage line for supplying 1.5 [V] as a terminating voltage VTT.

Reference numeral 17 denotes an integrated circuit for receiving a signal, reference numeral 18 denotes a signal input terminal, and reference numeral 19 denotes a reference voltage Vref used to determine the logic of a signal input to the signal input terminal 1. A reference voltage input terminal to which 5 [V] is input.

Reference numeral 20 denotes an input circuit composed of a differential amplifier circuit, reference numeral 21 denotes a VCC power supply line, and reference numerals 22 and 23 denote enhancement-type pMOS transistors constituting a current mirror circuit.

Reference numerals 24 and 25 denote an enhancement type nMOS transistor which forms a driving transistor, 26 denotes an enhancement type nMOS transistor which forms a constant current source, and 27 denotes an inverter for waveform shaping.

Here, in the integrated circuit 8, when the pMOS transistor 12 is turned on (conduction) and the nMOS transistor 13 is turned off (nonconduction), the signal output terminal 10
Is output as 1.5 [V] +0.4 [V] = 1.9 [V].

Further, the pMOS transistor 12 = off,
When the nMOS transistor 13 is turned on, the signal output terminal 10 has 1.5 [V] -0.4 [V] = 1.1.
[V] is output.

Also, the pMOS transistor 12 = off,
When the nMOS transistor 13 is turned off, the output state of the push-pull circuit 9 is set to a high impedance state.

As described above, the T-LVTTL transmission method is as follows.
By setting the intermediate voltage to 1.5 [V], a small signal of ± 0.4 [V] is transmitted, and the signal output terminal 10 of the integrated circuit 8 is brought into a high impedance state as required.

In the T-LVTTL transmission system, even when the transmission frequency of a small signal to be transmitted becomes high and the signal waveform becomes dull due to the parasitic capacitance of the bus line 14 or the like, the push-pull circuit 9 has an intermediate circuit. Voltage 1.5
Since the pull-down operation and the pull-up operation centered on [V] are performed, there is an advantage that a constant duty ratio can be ensured and transmission can be speeded up.

[0015]

However, this T-LV
In the TTL transmission system, when the output state of the push-pull circuit 9 is set to a high impedance state, the integrated circuit 17
The terminal voltage VTT = 1.5 [V], which is the same voltage as the reference voltage Vref, is supplied to the signal input terminal 18 via the resistor 15.

In this case, the input circuit 20 of the integrated circuit 17
26, since it is composed of a differential amplifier circuit, attempts to amplify the voltage of the bus line 14 having no transmission signal. As a result, as shown in FIG. And the L level are repeated, which may cause a malfunction.

Here, for example, when the T-LVTTL transmission system is adopted in the bus system shown in FIG. 24, an output circuit connected to a control signal output terminal such as a row address strobe signal of the CPU 1, , CP
When the output state of the output circuit connected to U1 and the data input / output terminals of the SDRAMs 2 to 5 is set to the high impedance state, the noises cause the SDRAMs 2 to 5 to accidentally receive the write command. There are cases.

In this case, the input circuits connected to the data input / output terminals of the SDRAMs 2 to 5 transfer data based on noise to the write circuit, which may destroy legitimate data. was there.

In view of the above, the present invention has a plurality of integrated circuits each having a signal input / output terminal connected to an output terminal of an output circuit formed of a tristate circuit connected to a common bus line, and A bus system in which the terminating end of a bus line is terminated by a terminating resistor supplied with a terminating voltage of the same or substantially the same voltage as a reference voltage used to determine the logic of a signal input to a signal input / output terminal Even when the output state of the output circuit connected to the common bus line via the signal input / output terminal is all set to the high impedance state, malfunction does not occur and reliability is reduced. A bus system that can be enhanced; and
An object of the present invention is to provide an integrated circuit suitable for use in a bus system.

[0020]

FIG. 1 is a diagram illustrating the principle of a bus system according to the present invention. In the figure, 29 and 30 are integrated circuits, 31 and 32 are signal input / output terminals,
4 is an input circuit.

Reference voltage input terminals 35 and 36 receive a reference voltage Vref used to determine the logic of a signal input through the signal input / output terminals 31 and 32 in the input circuits 33 and 34. It is.

Reference numerals 37 and 38 denote output circuits comprising tristate circuits, and HiZ denotes a high impedance control signal for controlling the output state of the output circuits 37 and 38 to a high impedance state.

Reference numeral 39 denotes a bus line to which the signal input / output terminals 31 and 32 are commonly connected, 40 denotes a terminating resistor on the integrated circuit 29 side, 41 denotes a terminating resistor on the integrated circuit 30 side, and 42 and 43 denote reference voltages Vref. Termination voltage VTT of the same or almost the same voltage as
Is a terminating voltage line that supplies

Reference numeral 44 denotes a reference voltage line for supplying the reference voltage Vref, reference numeral 45 denotes a reference voltage generation circuit for generating the reference voltage Vref, and reference numeral 46 denotes a reference when the output state of the output circuits 37 and 38 is set to a high impedance state. Voltage input terminal 35,
A reference voltage control circuit that controls the reference voltage Vref to be supplied to 36 so as to be different from the voltage value when the signal is transmitted via the bus line 39, that is, different from the voltage value output from the reference voltage generation circuit 45. is there.

That is, in the bus system according to the present invention, the signal input / output terminals 31 and 32 to which the output terminals of the output circuits 37 and 38 are connected to the common bus line 39 and the signal input / output terminals are connected. Signal input / output terminals 31 and 32 are connected to the other input terminals of input circuits 33 and 34 each including a differential amplifier circuit having one input terminal connected to output terminals 31 and 32.
, A plurality of integrated circuits, for example, two integrated circuits 29, to which a reference voltage Vref for judging the logic of a signal inputted through the reference voltage input terminals 35 and 36 is inputted.
30 and the terminal of the bus line 39 is connected to the reference voltage Vre.
The present invention is to improve a bus system which is terminated by terminating resistors 40 and 41 to which a terminating voltage VTT having the same or substantially the same voltage as f is supplied, and all output states of output circuits 37 and 38 are set to a high impedance state. In this case, the reference voltage Vref supplied to the reference voltage input terminals 35 and 36 is
And a reference voltage control circuit 46 for controlling the voltage value to be different from that when a signal is transmitted through the control circuit.

The reference voltage generation circuit 45 and the reference voltage control circuit 46 can be formed separately from the integrated circuits 29 and 30, and can be incorporated in any of the integrated circuits 29 and 30.

[0027]

In the bus system according to the present invention, when all the output states of the output circuits 37 and 38 are set to the high impedance state, the reference voltage supplied to the reference voltage input terminals 35 and 36 by the reference voltage control circuit 46. Vref is controlled to have a different voltage value from the case where signal transmission is performed via the bus line 39.

Here, the reference voltage Vref is equal to the termination voltage VTT.
In a case where the signal input / output terminal 3
1 and 32, and a reference voltage Vre.
f, and the output values of the input circuits 33 and 34 are fixed at H level or L level.

Therefore, in this case, the output circuit 3
Even when the output states of the circuits 7 and 38 are all set to the high impedance state, the noises input to the input circuits 33 and 34 via the signal input / output terminals 31 and 32 cause the outputs of the input circuits 33 and 34 to be random. Since the H level and the L level are not repeated, malfunction can be prevented.

Further, even when the reference voltage Vref also serves as the termination voltage VTT, the reference voltage Vref is no longer the optimum bias voltage for the input circuits 33 and 34. Can be prevented.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 2 to 23, the present invention will be described with reference to the first to sixth embodiments, the first application example, and the second application example of the bus system according to the present invention. An example in which the present invention is applied to a bus system employing a transmission method will be described, including an integrated circuit suitable for use in the bus system according to the present invention.

FIG. 2 is a circuit diagram showing a main part of a first embodiment of a bus system according to the present invention. In FIG. 2, 47 is a CPU, and 48 to 51 are CPUs.
Is an SDRAM.

The CPU 47 and the SDRAMs 48 to 5
1, 52 to 56 are data input / output terminals, and 57 to 6
An input circuit 1 determines the logic of data input to the data input / output terminals 52 to 56.

The reference circuits 62 to 66 receive 1.5 [V] as reference voltages Vref used to determine the logic of data input to the data input / output terminals 52 to 56 in the input circuits 57 to 61. This is a reference voltage input terminal.

The input circuits 57 to 61 are constituted by differential amplifier circuits as shown in the circuit diagram of FIG.
In the drawing, reference numeral 68 denotes a VCC power supply line for supplying 3 [V] as a power supply voltage VCC, and reference numerals 69 and 70 denote enhancement-type pMOS transistors constituting a current mirror circuit.

Reference numerals 71 and 72 denote enhancement-type pMOS transistors for fixing the output to the H level when inactive, and reference numerals 73 and 74 denote enhancement-type nMOS transistors serving as drive transistors.

Reference numeral 75 denotes an enhancement-type nMOS transistor serving as a constant current source whose on / off is controlled by the reference voltage Vref. V _IN is the voltage of the input data D _IN .

This input circuit has a reference voltage Vref = 1.5.
In the case of [V], the pMOS transistors 71 and 72 are turned off, and the nMOS transistor 75 is turned on to be activated.

In this case, when data voltage V _IN > reference voltage Vref, node 76 is set to L level, and when data voltage V _IN <reference voltage Vref, node 76 = L level.
H level.

As will be described later, the reference voltage Vref =
When the voltage is set to 0 [V], the nMOS transistor 75 =
When it is off, it becomes inactive and the pMOS transistors 71 and 72 are turned on, and the node 76 is fixed at the H level.

In FIG. 2, reference numerals 77 to 81 denote output circuits composed of tristate circuits. These output circuits 77 to 81 are configured as shown in the circuit diagram of FIG.

This output circuit has a slew rate (slew rat
e) That is, the output voltage rising speed or the falling speed can be selected from three types.
In the following, when the slew rate is intermediate, normal mode (normal mode), when the slew rate is lower than intermediate, slow mode (slow mode), greater than when the slew rate is intermediate If the first
It is called a mode (fast mode).

FIG. 5 shows the output waveform of this output circuit. Solid lines 83 and 84 show changes in the output waveform when the slow mode is selected, and broken lines 85 and 86 show the outputs when the normal mode is selected. Change in waveform, two-dot chain line 87, 88
Indicates a change in the output waveform when the fast mode is selected.

In FIG. 4, reference numeral 90 denotes a main push-pull circuit; 91, a VCC power supply line; 92, an enhancement pMOS transistor as a pull-up element; and 93, an enhancement nMOS transistor as a pull-down element. is there.

Reference numeral 94 denotes a push-pull control circuit for controlling the output of the push-pull circuit 90;
D circuit, 96 is a NOR circuit, 97 is an inverter.

Reference numeral 98 denotes a push-pull circuit for adjusting a slew rate; 99, a VCC power supply line; 100, an enhancement-type pMOS transistor as a pull-up element; and 101, an enhancement-type nMOS transistor as a pull-down element. .

A push-pull control circuit 102 controls the output of the push-pull circuit 98.
05 is an inverter, 106 to 109 are NAND circuits, 1
10 to 113 are NOR circuits.

MS1 to MS4 are slew rate mode selection signals for selecting a slew rate mode;
DATA is a data signal to be output.

In this output circuit, when the high impedance state is selected as the output state, the high impedance control signal HiZ = H level as shown in FIG.

As a result, the output of the inverter 97 becomes L level, the output of the NAND circuit 95 becomes H level, the output of the NAND circuit 109 becomes H level, and the pMOS transistor 92 is turned off and the pMOS transistor 100 is turned off.

In this case, the output of the NOR circuit 96 goes low, the output of the NOR circuit 113 goes low, and the nMOS transistor 93 is turned off and the nMOS transistor 101 is turned off.

As described above, the high impedance control signal H
When iZ = H level, the pMOS transistor 92
= Off, nMOS transistor 93 = off, pMOS transistor 100 = off, nMOS transistor 101
= Off, and the output state is set to a high impedance state.

When operating the push-pull circuits 90 and 98, the high impedance control signal HiZ = L
In this case, the relationship between the logic of the slew rate mode selection signals MS1 to MS4 and the selected slew rate mode is as shown in Table 1.

[0054]

[Table 1]

Here, for example, when the slow mode is selected, as shown in FIG. 7, high impedance control signal HiZ = L level, slew rate mode selection signal MS1 = L level, slew rate mode Select signal MS2 = L level, slew rate mode select signal MS
3 = H level, slew rate mode selection signal MS4 =
H level.

As a result, the output of the inverter 97 = H level, the output of the NAND circuit 106 = H level, the output of the NAND circuit 107 = H level, the output of the NOR circuit 110 =
L level, the output of the NOR circuit 111 is fixed at L level.

In this case, a one-shot pulse generation circuit composed of NAND circuits 108 and 109 is constructed, and a one-shot pulse generation circuit composed of NOR circuits 112 and 113 is constructed.

FIG. 8 shows the data signal DATA in this state.
FIG. 8A is a time chart showing the operation when the signal changes from the H level to the L level, and FIG. 8A shows the data signal DATA.

FIG. 8B shows the output of the NAND circuit 95,
FIG. 8C shows the ON / OFF state of the pMOS transistor 92,
8D shows the output of the NOR circuit 96, and FIG. 8E shows the on / off state of the nMOS transistor 93.

8F shows the output of the NAND circuit 108, FIG. 8G shows the output of the NAND circuit 109, and FIG.
The on / off state of the OS transistor 100, FIG.
8J shows the output of the NOR circuit 113, and FIG. 8K shows the on / off state of the nMOS transistor 101.

When the data signal DATA is at the H level, the output of the NAND circuit 95 is at the L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 is at the L level, the nMOS transistor 93 is turned off.

When the output of the NAND circuit 108 is at the L level and the output of the NAND circuit 109 is at the H level, the pMOS
The transistor 100 is turned off, the output of the NOR circuit 112 is L level, and the output of the NOR circuit 113 is L
At the level, the nMOS transistor 101 is turned off.

Therefore, in this case, the output voltage of this output circuit is set to H level by pMOS transistor 92.
The level will be maintained.

Here, when the data signal DATA changes from H level to L level, the output of the NAND circuit 95 = H
Level, the pMOS transistor 92 is turned off, and the output of the NOR circuit 96 is set to the H level.
The OS transistor 93 is turned on.

Also, the output of the NAND circuit 108 goes high, but in this case, the output of the NAND circuit 108 goes low.
The timing of changing from level to H level, the data signal DATA is delayed by delay time [Delta] T ₁₀₈ of NAND circuit 108 to the timing changing from H level to L level.

Therefore, in this case, the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA.
9 is maintained at the H level, and the pMOS transistor 1
00 = maintain off.

On the other hand, the output of the NOR circuit 112 becomes H level. In this case, the timing at which the output of the NOR circuit 112 changes from L level to H level is determined by the data signal D.
It is delayed by the delay time ΔT ₁₁₂ of the NOR circuit 112 from the timing when ATA changes from H level to L level.

As a result, when the data signal DATA changes from the H level to the L level, the output of the NOR circuit 113 becomes NO after the delay time ΔT ₁₁₃ of the NOR circuit _{113 has} elapsed.
Only delay time [Delta] T ₁₁₂ of R circuit 112 becomes H level, then returns to the L level.

Therefore, nMOS transistor 101
When the data signal DATA changes from the H level to the L level, the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses.
Only delay time [Delta] T ₁₁₂ of NOR circuit 112 turns on, then returns to the off.

As described above, when the slow mode is selected, when the data signal DATA changes from H level to L level,
The pMOS transistor 92 is off and the nMOS transistor 93 is on.

The pMOS transistor 100 maintains the off state, and the nMOS transistor 101
Only delay time [Delta] T ₁₁₂ of R circuit 112 turns on, then returns to the off.

Therefore, in this case, the output of the output circuit changes from the H level to the L level in accordance with the change of the data signal DATA, but from the H level to the L level by the delay time ΔT ₁₁₂ of the NOR circuit 112. Is accelerated, and changes as shown by a solid line 83 in FIG.

FIG. 9 is a time chart showing the operation when data signal DATA changes from L level to H level when slow mode is selected.
Indicates a data signal DATA.

FIG. 9B shows the output of the NAND circuit 95,
FIG. 9C shows the ON / OFF state of the pMOS transistor 92,
9D shows the output of the NOR circuit 96, and FIG. 9E shows the on / off state of the nMOS transistor 93.

FIG. 9F shows the output of the NAND circuit 108, FIG. 9G shows the output of the NAND circuit 109, and FIG.
The on / off state of the OS transistor 100, FIG.
9J shows the output of the NOR circuit 113, and FIG. 9K shows the on / off state of the nMOS transistor 101.

Here, when the data signal DATA is at the L level, the output of the NAND circuit 95 is at the H level, the pMOS transistor 92 is turned off, and
When the output of the NOR circuit 96 is at the H level, the nMOS transistor 93 is turned on.

When the output of the NAND circuit 108 is at the H level and the output of the NAND circuit 109 is at the H level, the pMOS
Transistor 100 = OFF and NOR
When the output of the circuit 112 is H level and the output of the NOR circuit 113 is L level, the nMOS transistor 101 is turned off.

Therefore, in this case, the output voltage of this output circuit is set to L level by nMOS transistor 93.
The level will be maintained.

Here, when the data signal DATA changes from L level to H level, the output of the NAND circuit 95 becomes L = L.
Level, the pMOS transistor 92 is turned on, and the output of the NOR circuit 96 is at L level, and nM
The OS transistor 93 is turned off.

The output of the NAND circuit 108 goes low, but in this case, the output of the NAND circuit 108 goes high.
The timing of the change from the level to the L level is later than the timing of the change of the data signal DATA from the L level to the H level by a delay time ΔT ₁₀₈ of the NAND circuit 108.

As a result, the output of NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, N
Only delay time [Delta] T ₁₀₈ of the AND circuit 108 becomes the L level, then returns to the H level.

Therefore, pMOS transistor 100
When the data signal DATA is changed from L level to H level, after a delay time [Delta] T ₁₀₉ elapses from the NAND circuit 109, turns on only the delay time [Delta] T ₁₀₈ of the NAND circuit 108, then returns to the off.

On the other hand, the output of the NOR circuit 112 is at the L level. In this case, the timing at which the output of the NOR circuit 112 changes from the H level to the L level is determined by the data signal D.
It is delayed by the delay time ΔT ₁₁₂ of the NOR circuit 112 from the timing when ATA changes from the L level to the H level.

As a result, in this case, the NOR circuit 11
3, the H level is input to the input side of the NOR circuit 1 before and after the change of the data signal DATA.
13 is kept at the L level, and the nMOS transistor 101 is kept off.

As described above, when the slow mode is selected, when the data signal DATA changes from L level to H level,
The pMOS transistor 92 is turned on, and the nMOS transistor 93 is turned off.

The pMOS transistor 100 has N
Only delay time [Delta] T ₁₀₈ of the AND circuit 108 turns on, then, returns to off, nMOS transistors 1
01 maintains the off state.

Therefore, in this case, the output of this output circuit changes from the L level to the H level in accordance with the change of data signal DATA, but from the L level to the H level for delay time ΔT ₁₀₈ of NAND circuit 108. Is accelerated, and changes as shown by a solid line 84 in FIG.

When the normal mode is selected, as shown in FIG. 10, high impedance control signal HiZ = L level, slew rate mode selection signal MS
1 = H level, slew rate mode selection signal MS2 =
L level, slew rate mode selection signal MS3 = L level, slew rate mode selection signal MS4 = H level.

As a result, the output of the inverter 97 is fixed at H level, the output of the NAND circuit 107 is fixed at H level, and the output of the NOR circuit 111 is fixed at L level.

In this case, a one-shot pulse generating circuit composed of inverter 103 and NAND circuits 106, 108, and 109 is constructed, and inverter 103,
A one-shot pulse generation circuit including NOR circuits 110, 112, and 113 is configured.

FIG. 11 is a time chart showing the operation when data signal DATA changes from H level to L level in this state, and FIG. 11A shows data signal D.
ATA is shown.

FIG. 11B shows the output of the NAND circuit 95, FIG. 11C shows the on / off state of the pMOS transistor 92, FIG. 11D shows the output of the NOR circuit 96, and FIG.
The ON and OFF states of the MOS transistor 93 are shown.

FIG. 11F shows the output of the NAND circuit 108, FIG. 11G shows the output of the NAND circuit 109, FIG. 11H shows the on / off state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG.
13K shows the ON / OFF state of the nMOS transistor 101. FIG.

Here, when the data signal DATA is at the H level, the output of the NAND circuit 95 is at the L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 is at the L level, the nMOS transistor 93 is turned off.

Further, the output of the inverter 103 becomes L level, the output of the NAND circuit 106 becomes H level, the output of the NAND circuit 108 becomes L level, the output of the NAND circuit 109 becomes H level, and the pMOS transistor 100 is turned off.

Further, the output of the NOR circuit 110 = H level, the output of the NOR circuit 112 = L level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off.

Therefore, in this case, the output voltage of this output circuit is set to H level by pMOS transistor 92.
The level will be maintained.

Here, when the data signal DATA changes from H level to L level, the output of the NAND circuit 95 = H
Level, the pMOS transistor 92 is turned off, and the output of the NOR circuit 96 is set to the H level.
The OS transistor 93 is turned on.

When the output of the inverter 103 = H level and the output of the NAND circuit 106 = L level, the NAND
The output of the circuit 108 becomes H level.

In this case, the output of NAND circuit 108 is L
The timing of changing from level to H level, the timing at which the data signal DATA is changed from H level to L level, delay time of the inverter 103 [Delta] T ₁₀₃ + NA
The delay time of the ND circuit 106 [Delta] T ₁₀₆ + NAND circuit 10
8 delay time ΔT ₁₀₈ .

Therefore, in this case, the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA.
9 is maintained at the H level, and the pMOS transistor 1
00 = maintain off.

On the other hand, the output of the NOR circuit 110 goes low and the output of the NOR circuit 112 goes high.

In this case, the timing at which the output of the NOR circuit 112 changes from L level to H level is longer than the timing at which the data signal DATA changes from H level to L level, which is the delay time ΔT ₁₀₃ + NOR of the inverter 103.
Delayed by a delay time period [Delta] T ₁₁₂ of the delay time of the circuit 110 [Delta] T ₁₁₀ + NOR circuit 112.

[0104] As a result, the output of NOR circuit 113, the data signal DATA is changed from H level to L level, after a delay time [Delta] T ₁₁₃ elapses from the NOR circuit 113, the delay time of the delay time [Delta] T ₁₀₃ + NOR circuit 110 of the inverter 103 ΔT ₁₁₀ + the delay time ΔT of the NOR circuit 112
_It goes to the H level by ₁₁₂ and thereafter returns to the L level.

Therefore, nMOS transistor 101
When the data signal DATA changes from the H level to the L level, the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses .
Delay time of the inverter 103 [Delta] T ₁₀₃ + NOR circuit 11
Only delay time [Delta] T ₁₁₂ of the delay time of 0 [Delta] T ₁₁₀ + NOR circuit 112 turns on, then returns to the off.

As described above, when the normal mode is selected, when the data signal DATA changes from the H level to the L level, the pMOS transistor 92 is turned off and the nMOS transistor 93 is turned on.

Further, the pMOS transistor 100 is kept off, and the nMOS transistor 101 has the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT _{110 of the} NOR circuit ₁₁₀ + the delay time ΔT 112 of the NOR circuit _112.
Only turns on, and then returns to off.

Therefore, in this case, the output of this output circuit changes from the H level to the L level in accordance with the change of data signal DATA, but the delay time of inverter 103 ΔT ₁₀₃ + the delay time of NOR circuit 110 ΔT ₁₁₀ + N
Only delay time [Delta] T ₁₁₂ of the OR circuit 112, changes from H level L level is accelerated, changes as shown by the broken line 85 shown in FIG.

FIG. 12 is a time chart showing the operation when the data signal DATA changes from the L level to the H level when the normal mode is selected. FIG. 12A shows the data signal DATA.

FIG. 12B shows the output of the NAND circuit 95, FIG. 12C shows the on / off state of the pMOS transistor 92, FIG. 8D shows the output of the NOR circuit 96, and FIG.
The on and off states of the OS transistor 93 are shown.

12F shows the output of the NAND circuit 108, FIG. 12G shows the output of the NAND circuit 109, FIG. 12H shows the on / off state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG.
13K shows the on / off state of the nMOS transistor 101. FIG.

When the data signal DATA is at the L level, the output of the NAND circuit 95 is at the H level, the pMOS transistor 92 is turned off, and
When the output of the NOR circuit 96 is at the H level, the nMOS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the NAND circuit 106 = L level, the output of the NAND circuit 108 = H level, the output of the NAND circuit 109 = H level, and the pMOS transistor 100 is turned off. .

Also, the output of the NOR circuit 110 = L level, the output of the NOR circuit 112 = H level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off.

Therefore, in this case, the output voltage of this output circuit is set to L level by nMOS transistor 93.
The level will be maintained.

Here, when the data signal DATA changes from L level to H level, the output of the NAND circuit 95 = L
Level, the pMOS transistor 92 is turned on, and the output of the NOR circuit 96 is at L level, and nM
The OS transistor 93 is turned off.

The output of the inverter 103 becomes L level, the output of the NAND circuit 106 becomes H level, and the output of the NAND circuit 108 becomes L level.

In this case, the output of NAND circuit 108 is H
The timing when the level changes from the L level to the L level is longer than the timing when the data signal DATA changes from the L level to the H level than the delay time ΔT ₁₀₃ + NA of the inverter 103.
The delay time of the ND circuit 106 [Delta] T ₁₀₆ + NAND circuit 10
8 delay time ΔT ₁₀₈ .

As a result, the output of NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses and then the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the NAND circuit 10
Only delay time [Delta] T ₁₀₈ of the delay time [Delta] T ₁₀₆ + NAND circuit 108 of 6 to the L level, then returns to the H level.

Therefore, pMOS transistor 100
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT _{106 of the} NAND circuit ₁₀₆ + the delay time ΔT 108 of the NAND circuit ₁₀₈ Only turns on, and then returns to off.

On the other hand, the output of the NOR circuit 110 goes high and the output of the NOR circuit 112 goes low.

In this case, the timing at which the output of the NOR circuit 112 changes from H level to L level is longer than the timing at which the data signal DATA changes from L level to H level, by the delay time ΔT ₁₀₃ + NOR of the inverter 103.
Delayed by a delay time period [Delta] T ₁₁₂ of the delay time of the circuit 110 [Delta] T ₁₁₀ + NOR circuit 112.

As a result, in this case, the NOR circuit 11
3 is input to the input side of the NOR circuit 1 before and after the change of the data signal DATA.
13 is maintained at the L level, and the nMOS transistor 101 is kept off.

As described above, when the normal mode is selected, when the data signal DATA changes from the L level to the H level, the pMOS transistor 92 is turned on and the nMOS transistor 93 is turned off.

The pMOS transistor 100 is connected to the delay time ΔT ₁₀₃ + NAND circuit 10 of the inverter 103.
Only delay time [Delta] T ₁₀₈ of the delay time [Delta] T ₁₀₆ + NAND circuit 108 of 6 turned on, thereafter, returns to OFF,
The nMOS transistor 101 maintains the off state.

Therefore, in this case, the output of this output circuit changes from the L level to the H level in accordance with the change in data signal DATA. However, the delay time ΔT _{103 of} inverter ₁₀₃ + the delay time ΔT _{106 of} NAND circuit ₁₀₆ +
Only delay time [Delta] T ₁₀₈ of the NAND circuit 108, a change in H level is accelerated from the L level, the broken lines shown in FIG. 5 86
It changes like

When the fast mode is selected, as shown in FIG. 13, high impedance control signal HiZ = L level, slew rate mode selection signal M
S1 = L level, slew rate mode selection signal MS2
= H level, slew rate mode selection signal MS3 = H
The level and the slew rate mode selection signal MS4 are set to L level.

As a result, the output of the inverter 97 is fixed at H level, the output of the NAND circuit 106 is fixed at H level, and the output of the NOR circuit 110 is fixed at L level.

In this case, inverters 103 to 105, N
A one-shot pulse generation circuit composed of AND circuits 107 to 109 is configured, and inverters 103 to 109 are formed.
A one-shot pulse generation circuit 105 includes the NOR circuits 111 to 113.

FIG. 14 is a time chart showing the operation when data signal DATA changes from H level to L level in this state. FIG. 14A shows data signal D.
ATA is shown.

14B shows the output of the NAND circuit 95, FIG. 14C shows the on / off state of the pMOS transistor 92, FIG. 14D shows the output of the NOR circuit 96, and FIG.
The ON and OFF states of the MOS transistor 93 are shown.

14F shows the output of the NAND circuit 108, FIG. 14G shows the output of the NAND circuit 109, FIG. 14H shows the on / off state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG.
13 shows the on / off state of the nMOS transistor 101. FIG.

Here, when the data signal DATA is at the H level, the output of the NAND circuit 95 is at the L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 is at the L level, the nMOS transistor 93 is turned off.

The output of the inverter 103 = L level, the output of the inverter 104 = H level,
05 = L level, NAND circuit 107 output = H
Level, output of NAND circuit 108 = L level, NAN
When the output of the D circuit 109 is at the H level, the pMOS transistor 100 is turned off.

Further, the output of the NOR circuit 111 = H level, the output of the NOR circuit 112 = L level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off.

Therefore, in this case, the output voltage of this output circuit is set to H level by pMOS transistor 92.
The level will be maintained.

Here, when the data signal DATA changes from H level to L level, the output of the NAND circuit 95 = H
Level, the pMOS transistor 92 is turned off, and the output of the NOR circuit 96 is set to the H level.
The OS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the inverter 104 = L level,
05 = H level, NAND circuit 107 output = L
Level, the output of the NAND circuit 108 becomes H level.

In this case, the timing at which the output of NAND circuit 108 changes from L level to H level is longer than the timing at which data signal DATA changes from H level to L level, by delay time ΔT ₁₀₃ +
Inverter 104 delay time ΔT ₁₀₄ + inverter 10
The delay time of the delay time of 5 [Delta] T ₁₀₅ + NAND circuit 107 [Delta] T ₁₀₇ + delayed by a delay time period [Delta] T ₁₀₈ of the NAND circuit 108.

Therefore, the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA, so that the output of the NAND circuit 109 becomes H level, and the pMOS transistor 100 is kept off.

On the other hand, the output of the NOR circuit 111 goes low and the output of the NOR circuit 112 goes high.

[0142] In this case, the timing at which the output of the NOR circuit 112 is changed from L level to H level, the data signal DATA is than the timing of changing from H level to L level, the delay time [Delta] T ₁₀₃ + inverter 104 of the inverter 103 the delay time of the delay time [Delta] T ₁₀₅ + NOR circuit 111 of the delay time [Delta] T ₁₀₄ + inverter 105 [Delta] T ₁₁₁ +
Delayed by a delay time ΔT ₁₁₂ of the NOR circuit 112.

[0143] As a result, the output of NOR circuit 113, the data signal DATA is changed from H level to L level, after a delay time [Delta] T ₁₁₃ elapses from the NOR circuit 113, the delay time of the delay time [Delta] T ₁₀₃ + inverter 104 of the inverter 103 ΔT ₁₀₄ + delay time of inverter 105 ΔT ₁₀₅
+ NOR circuit 111 delay time ΔT ₁₁₁ + NOR circuit 1
The H level is attained by the delay time ΔT _{112 for} 12 times, and thereafter, returns to the L level.

Therefore, nMOS transistor 101
When the data signal DATA changes from the H level to the L level, the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses .
Inverter 103 delay time ΔT ₁₀₃ + inverter 10
4 delay time ΔT ₁₀₄ + delay time Δ of inverter 105
Only turned on delay time [Delta] T ₁₁₂ a delay time of T ₁₀₅ + NOR circuit 111 [Delta] T ₁₁₁ + NOR circuit 112, then returns to the off.

As described above, when the fast mode is selected,
When the data signal DATA changes from H level to L level, the pMOS transistor 92 turns off and the nMOS transistor 93 turns on.

The pMOS transistor 100 is kept off, and the nMOS transistor 101 is connected to the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + the delay time ΔT _{105 of the} inverter ₁₀₅ +
Delay time ΔT _{111 of} NOR circuit ₁₁₁ + NOR circuit 11
It turns on only for the delay time ΔT _{112 of} 2, and then returns to off.

Therefore, in this case, the output of this output circuit changes from the H level to the L level in accordance with the change of data signal DATA. However, the delay time ΔT _{103 of} inverter ₁₀₃ + the delay time ΔT _{104 of} inverter ₁₀₄ + delay time of the inverter 105 [Delta] T ₁₀₅ + NOR circuit 111
Delay time ΔT ₁₁₁ + delay time Δ of NOR circuit 112
Only T _112, changes from H level L level is accelerated,
It changes like the two-dot chain line 87 shown in FIG.

FIG. 15 is a time chart showing an operation when data signal DATA changes from L level to H level when the first mode is selected.
FIG. 15A shows the data signal DATA.

FIG. 15B shows the output of the NAND circuit 95, FIG. 15C shows the on / off state of the pMOS transistor 92, FIG. 15D shows the output of the NOR circuit 96, and FIG.
The ON and OFF states of the MOS transistor 93 are shown.

15F shows the output of the NAND circuit 108, FIG. 15G shows the output of the NAND circuit 109, FIG. 15H shows the on / off state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG.
FIG. 15K shows the on / off state of the nMOS transistor 101.

When the data signal DATA is at the L level, the output of the NAND circuit 95 is at the H level, the pMOS transistor 92 is turned off, and
When the output of the NOR circuit 96 is at the H level, the nMOS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the inverter 104 = L level,
05 = H level, NAND circuit 107 output = L
Level, output of NAND circuit 108 = H level, NAN
When the output of the D circuit 109 is at the H level, the pMOS transistor 100 is turned off.

Further, the output of the NOR circuit 111 = L level, the output of the NOR circuit 112 = H level, the NOR circuit 1
13 output = H level, the nMOS transistor 101
= Off.

Therefore, in this case, the output voltage of this output circuit is set to L level by nMOS transistor 93.
The level will be maintained.

Here, when the data signal DATA changes from L level to H level, the output of the NAND circuit 95 = L
Level, the pMOS transistor 92 is turned on, and the output of the NOR circuit 96 is at L level, and nM
The OS transistor 93 is turned off.

Also, the output of the inverter 103 = L level, the output of the inverter 104 = H level,
05 = L level, NAND circuit 107 output = H
Level, the output of the NAND circuit 108 becomes L level.

In this case, the timing at which the output of NAND circuit 108 changes from H level to L level is longer than the timing at which data signal DATA changes from L level to H level, by delay time ΔT ₁₀₃ +
Inverter 104 delay time ΔT ₁₀₄ + inverter 10
The delay time of the delay time of 5 [Delta] T ₁₀₅ + NAND circuit 107 [Delta] T ₁₀₇ + delayed by a delay time period [Delta] T ₁₀₈ of the NAND circuit 108.

As a result, the output of NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, and then the delay time ΔT _{103 of the} inverter ₁₀₃ + the inverter 104
Delay time ΔT ₁₀₄ + delay time ΔT of inverter 105
₁₀₅ + delay time ΔT ₁₀₇ of NAND circuit ₁₀₇ + NAND
Delayed by a delay time period [Delta] T ₁₀₈ of the circuit 108.

Therefore, pMOS transistor 100
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit 109 has elapsed, the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + the delay time ΔT _{105 of the} inverter ₁₀₅ + NAND Delay time ΔT ₁₀₇ + N of circuit 107
Only delay time [Delta] T ₁₀₈ of the AND circuit 108 turns on, then returns to the off.

On the other hand, the output of the NOR circuit 111 goes high and the output of the NOR circuit 112 goes low.

[0161] In this case, the timing at which the output of the NOR circuit 112 is changed from H level to L level, than when the data signal DATA is changed from L level to H level, the delay time [Delta] T ₁₀₃ + inverter 104 of the inverter 103 the delay time of the delay time [Delta] T ₁₀₅ + NOR circuit 111 of the delay time [Delta] T ₁₀₄ + inverter 105 [Delta] T ₁₁₁ +
Delayed by a delay time ΔT ₁₁₂ of the NOR circuit 112.

As a result, the H level is input to the input side of the NOR circuit 113 before and after the change of the data signal DATA, so that the output of the NOR circuit 113 = L
The level is maintained, and the nMOS transistor 101 is kept off.

As described above, when the fast mode is selected,
When the data signal DATA changes from L level to H level, the pMOS transistor 92 is turned on and the nMOS transistor 93 is turned off.

Further, the pMOS transistor 100 is composed of the delay time ΔT _{103 of the} inverter ₁₀₃ + the inverter 104
Delay time ΔT ₁₀₄ + delay time ΔT of inverter 105
₁₀₅ + delay time ΔT ₁₀₇ of NAND circuit ₁₀₇ + NAND
Turned on by the delay time [Delta] T _{1 08} of circuit 108, then, returns to off, nMOS transistor 101 is kept off.

Therefore, in this case, the output of this output circuit changes from the L level to the H level in accordance with the change of data signal DATA. However, the delay time ΔT _{103 of} inverter ₁₀₃ + the delay time ΔT _{104 of} inverter ₁₀₄ + delay time of the inverter 105 [Delta] T ₁₀₅ + NAND circuit 10
Only delay time [Delta] T ₁₀₈ of the delay time [Delta] T ₁₀₇ + NAND circuit 108 of 7, changes from L level H level is accelerated, changes as indicated by two-dot chain line 88 shown in FIG.

In FIG. 2, reference numeral 115 denotes the output circuit 7.
7 is an output state signal output terminal for outputting an output state signal / OE indicating whether or not the output state is in a high impedance state.

Here, when the output state signal / OE = H level, the output state of the output circuit 77 is in a high impedance state, and when the output state signal / OE = L level, the output circuit 77 Means a data output state.

Reference numeral 116 denotes a data output inhibition signal output terminal for outputting a data output inhibition signal DQM1 for setting the output state of the output circuit 78 of the SDRAM 48 to a high impedance state and inhibiting data output from the data input / output terminal 53; 117 is a data output inhibit signal input terminal to which the data output inhibit signal DQM1 is input.

Here, data output inhibit signal DQM1 = H
When the level is at the level, the output state of the output circuit 78 is set to the high impedance state, and when the data output inhibition signal DQM1 is at the L level, the output circuit 78 is set to the data output state.

A data output prohibition signal output terminal 119 outputs a data output prohibition signal DQM2 for prohibiting the output of data from the data input / output terminal 54 by setting the output state of the output circuit 79 of the SDRAM 49 to a high impedance state. Is a data output inhibition signal input terminal to which the data output inhibition signal DQM2 is input.

Here, data output inhibit signal DQM2 = H
When the level is at the level, the output state of the output circuit 79 is set to the high impedance state, and when the data output inhibition signal DQM2 is at the L level, the output circuit 79 is set to the data output state.

A data output inhibition signal output terminal 120 outputs a data output inhibition signal DQM3 for inhibiting the output of data from the data input / output terminal 55 by setting the output state of the output circuit 80 of the SDRAM 50 to a high impedance state. Is a data output inhibition signal input terminal to which the data output inhibition signal DQM3 is input.

Here, data output inhibit signal DQM3 = H
When the level is at the level, the output state of the output circuit 80 is set to the high impedance state. When the data output inhibition signal DQM3 is at the L level, the output circuit 80 is set to the data output state.

Reference numeral 122 denotes a data output inhibition signal output terminal for outputting a data output inhibition signal DQM4 for inhibiting the output of data from the data input / output terminal 56 by setting the output state of the output circuit 81 of the SDRAM 51 to a high impedance state; Is a data output inhibition signal input terminal to which the data output inhibition signal DQM4 is input.

Here, data output inhibit signal DQM4 = H
When the level is at the level, the output state of the output circuit 81 is set to the high impedance state, and when the data output inhibition signal DQM4 is at the L level, the output circuit 81 is set to the data output state.

Reference numeral 124 denotes a CPU 47 and an SDRAM
A bus line to which data input / output terminals 52 to 56 of 48 to 51 are commonly connected, 125 is a terminating resistor on the CPU 47 side,
Reference numeral 6 denotes a terminating resistor on the side of the SDRAMs 48 to 51, and 127 denotes a reference voltage line for supplying a reference voltage Vref also serving as a terminating voltage.

Reference numeral 128 denotes a reference voltage Vref of 1.5.
A reference voltage generation circuit 129 that outputs [V] is a reference voltage control circuit that controls a reference voltage Vref to be supplied to the reference voltage line 127.

In reference voltage control circuit 129, 1
An output state determination circuit 30 determines whether or not the output states of the output circuits 77 to 81 of the CPU 47 and the SDRAMs 48 to 51 are all in the high impedance state.

Here, reference numeral 131 denotes an N to which the output state signal / OE and the data output inhibit signals DQM1 to DQM4 are input.
An AND circuit 132 is an inverter for inverting the output of the NAND circuit 131.

Reference numeral 133 denotes a reference voltage switching circuit for switching the voltage value of the reference voltage Vref to be supplied to the reference voltage line 127. Reference numerals 134 and 135 denote an enhancement type n.
The MOS transistors 136 and 137 are enhancement-type pMOS transistors.

That is, the nMOS transistor 134 and pM
The OS transistor 136 forms one analog switch, and the nMOS transistor 135 and the pMOS transistor 137 form one analog switch.

Here, when one of output state signal / OE and data output inhibit signal DQM1 to DQM4 is at the L level, that is, a state where data is output from any of data input / output terminals 52 to 56 is set. If present, NA
The output of the ND circuit 131 goes high, and the output of the inverter 132 goes low.

As a result, the nMOS transistor 134 =
ON, pMOS transistor 136 = ON, nMOS transistor 135 = OFF, pMOS transistor 137
= Off.

Therefore, the reference voltage Vref of 1.5 [V] output from the reference voltage generating circuit 128 is applied to the reference voltage line 1
The signal is supplied to the CPU 47 and reference voltage input terminals 62 to 66 of the SDRAMs 48 to 51 via the CPU 27.

On the other hand, when output state signal / OE = H level and data output inhibit signals DQM1 to DQM4 = H level, that is, CPU 47 and SDRAMs 48 to 51
When all the output states of the output circuits 77 to 81 are in the high impedance state, the output of the NAND circuit 131
L level, output of inverter 132 = H level.

As a result, the nMOS transistor 134 =
Off, pMOS transistor 136 = off, nMOS transistor 135 = on, pMOS transistor 137
= ON.

Therefore, the reference voltage line 127 is nMO
S transistor 135 and pMOS transistor 137
And the CPU 47 and the SDRAMs 48 to 5
The ground voltage 0 [V] is applied to the reference voltage input terminals 62 to 66 of No. 1.
Is supplied, the input circuits 57 to 61 are deactivated, and the output is fixed at the H level as described above.

As described above, according to the first embodiment, the data input / output terminals 52 to 5 connected to the bus line 124 are connected.
Even when the output states of the output circuits 77 to 81 whose output terminals are connected to 6 are all in the high impedance state, malfunction due to noise input to the input circuits 57 to 61 can be prevented, and the reliability can be improved. Can be improved.

Also, in the first embodiment, the CPU
47 and input circuits 57 to 61 of SDRAMs 48 to 51
Is configured to be inactive when the supplied reference voltage Vref is set to 0 [V], so that unnecessary current can be prevented from flowing and power consumption can be reduced. Can be planned.

In the first embodiment, the CPU
47 and the output circuits 77 to 81 of the SDRAMs 48 to 51 can be selected so that the parasitic capacitance around the data input / output terminals 52 to 56 depends on the chip mounting method and the board design. Even when the value differs from the expected value, the output waveform can be optimized.

FIG. 16 is a circuit diagram showing a main part of a second embodiment of the bus system according to the present invention. The second embodiment is provided in the first embodiment. A reference voltage control circuit 139 having a circuit configuration different from that of the reference voltage control circuit 129 is provided.
The configuration is the same as that of the first embodiment.

The reference voltage control circuit 139 includes a reference voltage switching circuit 140 having a different circuit configuration from the reference voltage switching circuit 133 provided in the reference voltage control circuit 129, and the other components are the same as those of the reference voltage control circuit 129. It is composed.

Here, in the reference voltage switching circuit 140, reference numeral 141 denotes an inverter for setting the power supply voltage on the high voltage side to the reference voltage Vref and setting the power supply voltage on the low voltage side to the ground voltage 0 [V], and 142 denotes an enhancement-type power supply. A pMOS transistor 143 is an enhancement type nMOS transistor.

Here, when one of output state signal / OE and data output inhibit signal DQM1 to DQM4 is at L level, that is, data is output from any of data input / output terminals 52 to 56. If present, NA
The output of the ND circuit 131 goes high, and the output of the inverter 132 goes low.

As a result, pMOS transistor 142 =
On, the nMOS transistor 143 is turned off, and 1.5 [V] is supplied to the reference voltage input terminals 62 to 66 via the reference voltage line 127 as the reference voltage Vref.

On the other hand, when output state signal / OE = H level and data output inhibit signals DQM1 to DQM4 = H level, that is, CPU 47 and SDRAMs 48 to 51
When all the output states of the output circuits 77 to 81 are in the high impedance state, the output of the NAND circuit 131
L level, output of inverter 132 = H level.

As a result, pMOS transistor 142 =
The reference voltage input terminals 62 to 66 are supplied with the ground voltage 0 [V] as the reference voltage Vref to the reference voltage input terminals 62 to 66 via the reference voltage line 127.

Therefore, also in the second embodiment,
As in the case of the first embodiment, it is possible to prevent malfunction due to noise input to the input circuits 57 to 61 when all the output states of the output circuits 77 to 81 are set to the high impedance state, and to reduce power consumption. Thus, the output waveform can be optimized.

Third Embodiment FIG. 17 FIG. 17 is a circuit diagram showing a main part of a third embodiment of the bus system according to the present invention. In the third embodiment, the CPU 47 and the SDRAMs 48 to 48 shown in FIG. The input circuits 57 to 61 mounted on 51 are configured as shown in the circuit diagram of FIG. 17, and the other configuration is the same as that of the first embodiment shown in FIG.

The input circuit shown in FIG. 17 comprises a drain of an nMOS transistor 73, an nMOS transistor 7
4, a noise canceling capacitor 145 is connected between the gates and the other components are configured similarly to the input circuit shown in FIG.

When so-called differential noise, which rises sharply and falls sharply, is input to the nMOS transistor 73, this differential noise is generated by the gate-source capacitance of the nMOS transistor 73 and the source-gate capacitance of the nMOS transistor 74. Through the gate of the nMOS transistor 74, as shown by the broken line 146,
It may be transmitted to the reference voltage system.

According to the input circuit shown in FIG. 17, however, the differential noise obtained by inverting the differential noise input to the gate of the nMOS transistor 73 appears at the drain of the nMOS transistor 73. As shown in FIG.
The signal can be transmitted to the gate of the S transistor 74.

As a result, the differential noise transmitted to the gate of the nMOS transistor 74 via the capacitor 145 can cancel the noise mixed in the reference voltage system as shown by the broken line 146.

Therefore, according to the third embodiment, as in the case of the first embodiment, the signals are input to the input circuits 57 to 61 when the output states of the output circuits 77 to 81 are all set to the high impedance state. In addition to preventing malfunctions due to noise, reducing power consumption and optimizing output waveforms, the input circuits 57 to 6 can be used during data transmission.
A malfunction due to the differential noise input to 1 can be prevented.

Fourth Embodiment FIG. 18 FIG. 18 is a circuit diagram showing a main part of a fourth embodiment of the bus system according to the present invention. In the fourth embodiment, the CPU 47 and the SDRAMs 48 to 48 shown in FIG. The input circuits 57 to 61 mounted on 51 are configured as shown in the circuit diagram of FIG. 18, and the other configuration is the same as that of the first embodiment shown in FIG.

The input circuit shown in FIG. 18 uses a pMOS transistor 6 instead of connecting the gate of pMOS transistor 70 to the drain of nMOS transistor 74.
9 is connected to the drain of the nMOS transistor 73, and the output is obtained not from the drain of the nMOS transistor 73 but from the drain of the nMOS transistor 74.
It has the same configuration as the input circuit shown in FIG.

In the input circuit shown in FIG.
When differential noise having a large slew rate is input to the MOS transistor 73, the differential noise passes through the gate-source capacitance of the nMOS transistor 73 and the source-gate capacitance of the nMOS transistor 74, as indicated by a broken line 146. , May be transmitted to the gate of the nMOS transistor 74, that is, the reference voltage system.

According to the input circuit shown in FIG. 18, however, a differential noise obtained by inverting the differential noise input to the gate of the nMOS transistor 73 appears at the drain of the nMOS transistor 73. As shown in FIG.
The signal can be transmitted to the gate of the S transistor 74.

As a result, due to the differential noise transmitted to the gate of the nMOS transistor 74 via the capacitor 145, noise mixed in the reference voltage system can be canceled as shown by a broken line 146.

Therefore, according to the fourth embodiment, as in the case of the first embodiment, the signals are input to the input circuits 57 to 61 when the output states of the output circuits 77 to 81 are all set to the high impedance state. This can prevent malfunction due to noise, reduce power consumption, and optimize output waveforms.

According to the fourth embodiment, similarly to the third embodiment, it is possible to prevent malfunction due to differential noise input to the input circuits 57 to 61 during data transmission.

Fifth Embodiment FIGS. 19 and 20 FIG. 19 is a circuit diagram showing a main part of a fifth embodiment of the bus system according to the present invention. In the fifth embodiment, the CPU 47 shown in FIG. The input circuits 57 to 61 mounted on the SDRAMs 48 to 51 are configured as shown in the circuit diagram of FIG. 19, and the other components are configured in the same manner as the first embodiment shown in FIG.

The input circuit shown in FIG. 19 can be applied to a signal transmission system in which a voltage lower than the intermediate voltage in the T-LVTTL transmission system is used as a driving transistor. For example, depletion type nMOS transistors 148 and 149 having a negative threshold voltage are provided, and the others are configured in the same manner as the input circuit shown in FIG.

The gain-bandwidth product GBW of the input circuit shown in FIG. 19 is as shown by a solid line X in FIG. The broken line Y indicates the gain / bandwidth product GBW when an enhancement-type nMOS transistor is used as the driving transistor.

Therefore, in the input circuit shown in FIG. 19, when the reference voltage Vref is set to 1.5 [V], the intermediate voltage is set to 1.5 [V] and the minute voltage of ± 0.4 [V] is set. It can be used in a T-LVTTL transmission scheme for transmitting signals.

When the reference voltage Vref is set to 0.8 [V], the intermediate voltage is set to 0.8 [V] and ± 0.4.
GTL (Gunning) trying to transmit a small signal of [V]
(Tran-sisitor Logic) transmission method.

According to the fifth embodiment, as in the case of the first embodiment, the input circuits 57 to 81 when the output states of the output circuits 77 to 81 are all set to the high impedance state.
It is possible to prevent malfunction due to noise input to the input terminal 61, reduce power consumption, and optimize output waveforms, and use a highly convenient integrated circuit.

Sixth Embodiment FIG. 21 FIG. 21 is a circuit diagram showing a main part of a sixth embodiment of the bus system according to the present invention. This sixth embodiment is based on the SDRAMs 48 to 51 shown in FIG. The output circuit and the like are configured as shown in FIG. 21, and the others are configured as shown in FIG.

In the figure, reference numeral 150 denotes an output circuit;
153 is a push-pull circuit constituting the output circuit 150. The output circuit 150 can select an output resistance by selecting a push-pull circuit to be used.

In these push-pull circuits 151 to 153, 154 to 156 are pMOs serving as pull-up elements.
The S transistors 157 to 159 are nMOS transistors serving as pull-down elements.

Here, for example, pMOS transistor 154 has W (channel width = gate length) / L (channel length = gate width) = 400 μm / 1 μm, and pMOS transistor 155 has W / L = 200 μm / 1 μm and pMO
The S transistor 156 has W / L = 200 μm / 1 μm
It has been.

Also, for example, nMOS transistor 1
57, W / L = 200 μm / 1 μm, nMOS transistor 158, W / L = 100 μm / 1 μm, n MO
S transistor 159 has W / L = 100 μm / 1 μm
It has been.

Reference numerals 160 to 162 denote push-pull control circuits for controlling the outputs of the push-pull circuits 151 to 153, respectively.
69 and 170 are NAND circuits, 171 and 172 are NOR
The circuits 173 and 174 are flag registers (F1, F
2).

Reference numeral 175 denotes an output data latch circuit for latching output data DATA.
When TA = H level, output Q1 = H level, output Q2
= H level and when output data DATA = L level, output Q1 = L level and output Q2 = L level.

Here, when the value stored in the flag register 173 = H level, the output of the inverter 165 = L level, the output of the NAND circuit 169 = H level, and the pMOS
When the transistor 154 is turned off and the output of the NOR circuit 171 is at L level, the nMOS transistor 15
7 = OFF, and the push-pull circuit 151 is deactivated.

On the other hand, when the value stored in flag register 173 is at L level, the output of inverter 165 is at H level, and NAND circuit 169 outputs an inverter to output Q1 of output data latch circuit 175. And the NOR circuit 171 outputs the output data
It operates as an inverter for the output Q2 of the latch circuit 175.

Therefore, when output data DATA = H level, output Q1 = H level, and output Q2 = H level, the output of NAND circuit 169 = L level and pMOS
When the transistor 154 is turned on and the output of the NOR circuit 171 is at L level, the nMOS transistor 15
7 = OFF, and the output of the push-pull circuit 151 becomes H level.

On the other hand, when output data DATA = L level, output Q1 = L level, and output Q2 = L level, output of NAND circuit 169 = H level and pMOS
When the transistor 154 is turned off and the output of the NOR circuit 171 is at the H level, the nMOS transistor 15
7 = ON, the output of the push-pull circuit 151 becomes L level.

The value stored in flag register 174 =
In the case of the H level, the output of the inverter 166 = L level,
When the output of the NAND circuit 170 is at the H level, the pMOS transistor 155 is turned off and the NOR circuit 17 is turned off.
2 = L level, and the nMOS transistor 158 =
The switch is turned off, and the push-pull circuit 152 is deactivated.

On the other hand, when the value stored in flag register 174 = L level, the output of inverter 166 = H
Level, NAND circuit 170 is configured to operate as an inverter for the output Q1 of the output data latch circuit 175, NOR circuits 172 operates as an inverter for the output Q2 of the output data latch circuit 175
To be.

Therefore, when output data DATA = H level, output Q1 = H level and output Q2 = H level, the output of NAND circuit 170 = L level and pMOS
When the transistor 155 is turned on and the output of the NOR circuit 172 is at L level, the nMOS transistor 15
8 = OFF, and the output of the push-pull circuit 152 becomes H level.

On the other hand, when the output data DATA = L level, the output Q1 = L level, and the output Q2 = L level, the output of the NAND circuit 170 goes high and the pMOS
When the transistor 155 is turned off and the output of the NOR circuit 172 is at H level, the nMOS transistor 15
8 = ON, and the output of the push-pull circuit 152 becomes L level.

The push-pull circuit 153 outputs the output of the inverter 167 when the output data DATA = H level, the output Q1 = H level, and the output Q2 = H level regardless of the values stored in the flag registers 173 and 174. = L level, the pMOS transistor 156 is turned on, and the output of the inverter 168 = L level, the nMOS transistor 159 is turned off.
The output of 3 becomes H level.

On the other hand, when the output data DATA = L level, the output Q1 = L level, and the output Q2 = L level, the output of the inverter 167 = H level, the pMOS transistor 156 is turned off, and the inverter 1
68 output = H level, the nMOS transistor 159
= ON, and the output of the push-pull circuit 153 goes to L level.

Here, the flag registers 173, 174
, The state of the push-pull circuits 151 to 153, the combined value of W / L of the pMOS transistors used among the pMOS transistors 154 to 156, nMO
NM used among S transistors 157 to 159
Table 2 shows the relationship between the W / L of the OS transistor and the combined value.

[0236]

[Table 2]

In addition, CKE, / CS, / RAS, / CA
S, / WE, and CLK are signals supplied from the outside,
CKE is the clock enable signal, / CS is the chip enable signal.
Select signal, / RAS is a row address strobe signal, / CAS is a column address strobe signal, / W
E is a write enable signal, and CLK is a clock signal.

Reference numerals 176 to 179 capture the chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE using the clock enable signal CKE as a gate signal. Is a NAND circuit.

A decoder 180 fetches and decodes the outputs of the NAND circuits 176 to 179 in synchronization with the clock signal CLK, decodes them, and outputs a 16-bit decode signal.

Here, this decoder 180 has clock enable signal CKE = H level, chip select signal / CS = L level, row address strobe signal / RAS = L level, and column address strobe signal / CAS = L level, write enable signal / WE
When L = L level, the output at address 0 is set to H level.

181 is a shift register for shifting the clock signal CLK by one, and 182 is a decoder 180
Is a NAND circuit to which the output of address 0 and the output of the shift register 181 are input.

Reference numeral 183 denotes a 12-bit mode register for taking in addresses A _{0 to} A _11. The mode register 183 outputs the output of the NAND circuit 182 at the L level, that is, outputs the address 0 of the decoder 180 at the H level. level,
When the output of the shift register 181 is at the H level, address signals A _{0 to} A ₁₁ are fetched.

Reference numerals 183 _{0 to} 183 ₁₁ denote 1-bit registers for receiving address signals A _{0 to} A ₁₁ .
MA _{0 to} MA ₈ are 1-bit register portions 183 ₀ to 18
Is a stored value of 3 _8.

184 and 185 are NOR circuits, 18
6 is an encryption decoder, and 187 is a NAND circuit.

Here, in this SDRAM, MA
_{When 7} = H level and MA ₈ = H level, the user can uniquely define and use MA _{0 to} MA ₆ .

[0246] Therefore, in this sixth embodiment, the cipher decoder 186 for decoding the encrypted MA ₂ to MA ₆ provided encryption MA ₂ to MA ₆ cases only a special logic, the output H level of the cipher decoder 186 I am trying to be.

Also, MA ₇ , MA ₈ and encryption decoder 18
6 and the NOR circuit 18 to which MA ₀ and the output of the NAND circuit 187 are input.
4 and a NOR circuit 185 to which the output of the MA ₁ and the NAND circuit 187 is input.
4 is stored in the flag register 173, and the output of the NOR circuit 185 is stored in the flag register 174.

Here, the output of NAND circuit 187 is M
A ₇ = H level, MA ₈ = H level, encryption decoder 186
Therefore, when MA ₀ = L level, the output of the NOR circuit 184 can be set to H level, the H level can be written to the flag register 173, and MA ₀ = H level. In the case, the NOR circuit 18
4 = L level, and the flag register 173 outputs L level.
You can write levels.

When MA ₁ = L level,
The output of the NOR circuit 185 can be set to the H level, the H level can be written to the flag register 174, and MA ₁ =
In the case of H level, the output of the NOR circuit 174 = L
Level, and the L level can be written to the flag register 174.

According to the sixth embodiment, as in the case of the first embodiment, the input circuits 57 to 81 when the output states of the output circuits 77 to 81 are all set to the high impedance state are set.
It is possible to prevent malfunction due to noise input to the input terminal 61, reduce power consumption, and optimize an output waveform.

The CPU 47 and the SDRAMs 48 to 5
Since the output resistance of the output circuit of No. 1 can be selected,
The amplitude of the signal on the bus line 124 is set to the specified amplitude regardless of whether the bus line 124 is terminated on one side, on both ends, or when the terminating resistance is set to a value other than 50Ω. And good signal transmission can be performed.

First Application Example FIG. 22 FIG. 22 is a circuit diagram showing an example of an input circuit obtained by applying the input circuit shown in FIG. 17. In the case of the GTL transmission system, the input circuit is used for data transmission. 1 shows an input circuit configured to cancel differential noise input to the input circuit.

In the figure, reference numeral 190 denotes a power supply voltage VCC of 1.
VCC power supply line for supplying 2 [V], 191 is a reference voltage V
This is an enhancement-type pMOS transistor serving as a constant current source whose on / off is controlled by ref.

Reference numeral 192 denotes an enhancement type pMO as a driving transistor to which the data signal D _IN is inputted.
The S-transistor 193 is an enhancement-type pMOS transistor serving as a driving transistor to which 0.8 [V] is input as a reference voltage Vref during data transmission.

Reference numerals 194 and 195 denote enhancement-type nMOS transistors constituting a current mirror circuit, and reference numeral 196 denotes a noise canceling capacitor.

Here, when so-called differential noise having sharp rising and falling edges is input to the gate of the pMOS transistor 192, this differential noise is
Gate-source capacitance and pMO of transistor 192
As shown by a broken line 197, the pMOS transistor 1 is connected via the source-gate capacitance of the S transistor 193.
In some cases, the signal is transmitted to the gate 93, that is, the reference voltage system.

According to the input circuit shown in FIG. 22, however, the differential noise obtained by inverting the differential noise input to the gate of the pMOS transistor 192 appears at the drain of the pMOS transistor 192.
As shown by arrow 198, p
The signal can be transmitted to the gate of the MOS transistor 193.

As a result, the noise mixed into the reference voltage system as shown by the broken line 197 can be canceled by the differential noise transmitted to the gate of the pMOS transistor 193 via the capacitor 196.

FIG. 23 is a circuit diagram showing another example of an input circuit obtained by applying the input circuit shown in FIG. 17, which is used for data transmission in the case of the GTL transmission method. 5 shows an input circuit configured to cancel differential noise input to the input circuit.

In the input circuit shown in FIG. 23, the gate of nMOS transistor 194 is connected to pMOS transistor 19
2 is connected to the drain of the pMOS transistor 193, and the output is connected to the pMOS transistor 193.
PMOS transistor, not from the drain of 193
192 is obtained from the drain, and the rest is configured similarly to the input circuit shown in FIG.

In the input circuit shown in FIG. 23 as well, noise introduced into the reference voltage system as shown by broken line 197 is canceled by differential noise transmitted to the gate of pMOS transistor 193 via capacitor 196. Can be.

[0262]

According to the bus system of the present invention,
When the output states of the output circuits (37, 38) connected to the common bus line (39) via the signal input / output terminals (31, 32) are all in the high impedance state, the reference voltage control circuit By (46), the reference voltage input terminal (3
5, 36), the reference voltage (Vref) supplied to the bus line (39) is controlled so as to have a different voltage value from the case where the signal is transmitted. An output circuit (37, 40) whose end is connected to a common bus line (39) via signal input / output terminals (31, 32).
Even when all the output states of 38) are set to the high impedance state, the influence of noise input to the input circuits (33, 34) via the signal input / output terminals (31, 32) is eliminated, and malfunction is prevented. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a bus system according to the present invention.

FIG. 2 is a circuit diagram showing a main part of a first embodiment of the bus system according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of an input circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of an output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 5 is a waveform diagram for explaining a slew rate of an output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 6 is a circuit diagram for explaining a case where an output state of an output circuit provided in the first embodiment of the bus system according to the present invention is set to a high impedance state.

FIG. 7 is a circuit diagram for explaining an operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the slow mode is selected;

FIG. 8 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the slow mode is selected.

FIG. 9 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the slow mode is selected;

FIG. 10 is a circuit diagram for explaining an operation of the output circuit provided in the first embodiment of the bus system according to the present invention when a normal mode is selected.

FIG. 11 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the normal mode is selected.

FIG. 12 is a time chart for explaining an operation of the output circuit provided in the first embodiment of the bus system according to the present invention when a normal mode is selected;

FIG. 13 is a circuit diagram for explaining an operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the fast mode is selected.

FIG. 14 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the fast mode is selected.

FIG. 15 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the fast mode is selected.

FIG. 16 is a circuit diagram showing a main part of a second embodiment of the bus system according to the present invention.

FIG. 17 is a circuit diagram showing a main part (input circuit) of a third embodiment of the bus system according to the present invention.

FIG. 18 is a circuit diagram showing a main part (input circuit) of a fourth embodiment of the bus system according to the present invention.

FIG. 19 is a circuit diagram showing a main part (input circuit) of a fifth embodiment of the bus system according to the present invention.

FIG. 20 is a diagram illustrating a gain-bandwidth product of an input circuit.

FIG. 21 is a circuit diagram showing a main part (main part of an SDRAM) of a sixth embodiment of the bus system according to the present invention.

FIG. 22 is a circuit diagram showing an example of an input circuit obtained by applying the input circuit shown in FIG.

FIG. 23 is a circuit diagram showing another example of the input circuit obtained by applying the input circuit shown in FIG. 17;

FIG. 24 is a block diagram showing a main part of an example of a bus system.

FIG. 25 is a circuit diagram showing a T-LVTTL transmission scheme.

FIG. 26 is a diagram illustrating a problem of the T-LVTTL transmission scheme.

[Explanation of symbols]

 29, 30 Integrated circuits 31, 32 Data input / output terminals 33, 34 Input circuits 35, 36 Reference voltage input terminals. 37, 38 Output circuit 39 Bus line 40, 41 Termination resistor 42, 43 Termination voltage line 44 Reference voltage line 45 Reference voltage generation circuit 46 Reference voltage control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/40 H03K 19/0175 H04L 25/02

Claims (6)

(57) [Claims] 1. A terminal connected to a bus line terminated to a terminal voltage.
One input terminal and the other input terminal connected to the reference voltage line
And compares the voltage levels of the one and the other input terminals.
An input circuit including a differential circuit, and when a signal is transmitted through the bus line,
The reference voltage line has a first reference level and is connected via the bus line.
If no signal is transmitted, the reference voltage line
Have a second reference level different from the first reference level
And an integrated circuit. 2. An output having an output terminal connected to the bus line.
A power circuit for transmitting a signal via the bus line.
When not performed, the output of the output circuit is high impedance.
2. The integrated circuit according to claim 1, wherein
Road. 3. A high-impedance reference voltage control circuit, comprising:
Response to the output status signal and data mask signal indicating the
And outputting the second reference level.
The integrated circuit according to claim 2. 4. The system according to claim 1, wherein said first reference level is transmitted through said bus line.
Corresponding to an intermediate level of the amplitude of the transmitted signal,
2 reference level is ground voltage level or power supply voltage level
The integrated circuit according to claim 1, wherein: 5. The first reference level is equal to the termination voltage.
The integrated circuit according to claim 1, wherein 6. An input circuit according to claim 1 , wherein said input circuit is connected to said second reference level.
A switch for deactivating the differential circuit in response.
The integrated circuit according to claim 1, further comprising: