JP3449343B2 - Bus systems and integrated circuits - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of integrated circuits in which signal input / output terminals to which output terminals of an output circuit composed of a tri-state circuit (three-valued logic circuit) are connected are connected to a common bus line. And terminating the end portion of the bus line with a terminating resistor to which a terminating voltage having the same or substantially the same voltage as the reference voltage used to judge the logic of the signal input to the signal input / output terminal is supplied. And a integrated circuit suitable for use in such a bus system.

[0002]

2. Description of the Related Art FIG. 24 shows an essential part of an example of a bus system, where 1 is a CPU (central processing unit).
t), 2 to 5 are SDRAMs (syncs) that receive various signals in synchronization with clock signals supplied from the outside.
hronous dynamic random access memory), 6 is a bus line.

In recent years, T-LVTTL has been used as a minute signal transmission method used in such a bus system.
(Terminated low voltage transisitor transisitor l
ogic) transmission method or CTT (center tapped termin)
A small signal transmission system called transmission system has been proposed.

FIG. 25 is a circuit diagram showing a T-LVTTL transmission system. In the figure, 8 is an integrated circuit on the signal sending side, 9 is a push-pull circuit forming the final stage of the output circuit consisting of a tri-state circuit, and 10 is a signal output terminal.

In the push-pull circuit 9, 11
Is a VCC power supply line that supplies 3 [V] as a power supply voltage VCC, 12 is an enhancement-type pMOS transistor that forms a pull-up element, and 13 is an enhancement-type nMOS transistor that forms a pull-down element.

Further, 14 is a bus line forming a signal transmission path, 1
Reference numeral 5 is a terminating resistance, for example, a resistance of 50Ω, and 16 is a terminating voltage line for supplying 1.5 [V] as a terminating voltage VTT.

Further, 17 is an integrated circuit on the signal receiving side, 18 is a signal input terminal, and 19 is 1.1 as a reference voltage Vref used for judging the logic of the signal input to the signal input terminal 18. This is a reference voltage input terminal to which 5 [V] is input.

Reference numeral 20 is an input circuit composed of a differential amplifier circuit, 21 is a VCC power supply line, and 22 and 23 are enhancement type pMOS transistors forming a current mirror circuit.

Further, 24 and 25 are enhancement type nMOS transistors which form a driving transistor, 26 is an enhancement type nMOS transistor which is a constant current source, and 27 is an inverter for waveform shaping.

Here, in the integrated circuit 8, when the pMOS transistor 12 = on (conductive) and the nMOS transistor 13 = off (nonconductive), the signal output terminal 10
Outputs 1.5 [V] +0.4 [V] = 1.9 [V].

Further, the pMOS transistor 12 = off,
When the nMOS transistor 13 is turned on, the signal output terminal 10 has 1.5 [V] -0.4 [V] = 1.1.
[V] is output.

Further, the pMOS transistor 12 = off,
When the nMOS transistor 13 is turned off, the output state of the push-pull circuit 9 is in the high impedance state.

As described above, the T-LVTTL transmission system is
The intermediate voltage is set to 1.5 [V], a minute signal of ± 0.4 [V] is transmitted, and the signal output terminal 10 of the integrated circuit 8 is set to a high impedance state if necessary.

In the T-LVTTL transmission method, even when the transmission frequency of a minute signal to be transmitted becomes high and the signal waveform becomes dull due to the parasitic capacitance of the bus line 14, etc., the push-pull circuit 9 has an intermediate value. Voltage 1.5
Since the pull-down operation and pull-up operation centered on [V] are performed, there is an advantage that a constant duty ratio can be secured and the transmission speed can be increased.

[0015]

[Problems to be Solved by the Invention] However, this T-LV
In the TTL transmission method, when the output state of the push-pull circuit 9 is set to the high impedance state, the integrated circuit 17
The terminal voltage VTT = 1.5 [V], which is the same voltage as the reference voltage Vref, is supplied to the signal input terminal 18 through the resistor 15.

In this case, the input circuit 20 of the integrated circuit 17
Since it is composed of a differential amplifier circuit, it tries to amplify the voltage of the bus line 14 having no transmission signal. As a result, as shown in FIG. And the L level are repeatedly determined, which may cause a malfunction.

Here, for example, in the case where the T-LVTTL transmission system is adopted in the bus system shown in FIG. 24, an output circuit connected to a control signal output terminal such as a row address strobe signal of the CPU 1 or , CP
When the output state of the output circuit connected to U1 and the data input / output terminals of SDRAMs 2 to 5 is set to a high impedance state, noise causes SDRAMs 2 to 5 to accidentally capture the write command. There are cases.

In this case, the input circuit connected to the data input / output terminals of the SDRAMs 2 to 5 may transfer the noise-based data to the write circuit, possibly destroying the valid data. was there.

In view of the above point, the present invention has a plurality of integrated circuits in which the signal input / output terminals to which the output ends of the output circuits formed of tristate circuits are connected are connected to a common bus line, and A bus system in which a terminal end of a bus line is terminated by a terminating resistor that is supplied with a terminating voltage that is the same or substantially the same as a reference voltage used to determine the logic of a signal input to a signal input / output terminal. Therefore, even if all the output states of the output circuits whose output terminals are connected to the common bus line via the signal input / output terminals are in the high impedance state, malfunction does not occur and reliability is improved. A bus system that can be upgraded, and
The object is to provide an integrated circuit suitable for use in a bus system.

[0020]

FIG. 1 is a diagram illustrating the principle of a bus system according to the present invention. In the figure, 29 and 30 are integrated circuits, 31 and 32 are signal input / output terminals, and 33 and 3.
Reference numeral 4 is an input circuit.

Reference numerals 35 and 36 are reference voltage input terminals to which a reference voltage Vref used for determining the logic of a signal input through the signal input / output terminals 31 and 32 in the input circuits 33 and 34 is input. Is.

Further, 37 and 38 are output circuits composed of tri-state circuits, and HiZ is a high impedance control signal for controlling the output states of the output circuits 37 and 38 to a high impedance state.

Further, 39 is a bus line to which the signal input / output terminals 31 and 32 are commonly connected, 40 is a termination resistor on the integrated circuit 29 side, 41 is a termination resistor on the integrated circuit 30 side, and 42 and 43 are reference voltages Vref. Terminal voltage VTT that is the same or approximately the same voltage as
It is a terminal voltage line for supplying.

Reference numeral 44 is a reference voltage line for supplying the reference voltage Vref, 45 is a reference voltage generating circuit for generating the reference voltage Vref, and 46 is a reference when the output states of the output circuits 37 and 38 are in the high impedance state. Voltage input terminal 35,
A reference voltage control circuit that controls the reference voltage Vref supplied to the control circuit 36 so that the reference voltage Vref is different from the voltage value when the signal is transmitted through the bus line 39, that is, the voltage value output from the reference voltage generation circuit 45. is there.

That is, in the bus system according to the present invention, the signal input / output terminals 31 and 32, to which the output terminals of the output circuits 37 and 38 formed of the tri-state circuit are connected, are connected to the common bus line 39, and the signal input. The signal input / output terminals 31, 32 are connected to the other input terminals of the input circuits 33, 34, which are differential amplifier circuits, one input terminal of which is connected to the output terminals 31, 32.
A plurality of integrated circuits, for example, two integrated circuits 29, to which the reference voltage Vref for determining the logic of the signal input via the reference voltage input terminals 35 and 36 is input.
30 and has the terminal end of the bus line 39 at the reference voltage Vre.
This is to improve a bus system which is terminated by terminating resistors 40 and 41 which are supplied with a terminating voltage VTT which is the same or substantially the same voltage as f, and the output states of the output circuits 37 and 38 are all in a high impedance state. In this case, the reference voltage Vref supplied to the reference voltage input terminals 35 and 36 is set to the bus line 39.
The reference voltage control circuit 46 is provided to control the voltage value so that the voltage value is different from that when the signal is transmitted via the.

The reference voltage generating circuit 45 and the reference voltage control circuit 46 can be constructed separately from the integrated circuits 29 and 30, or can be built in either of the integrated circuits 29 and 30.

[0027]

In the bus system according to the present invention, when the output states of the output circuits 37 and 38 are all set to the high impedance state, the reference voltage supplied to the reference voltage input terminals 35 and 36 by the reference voltage control circuit 46. Vref is controlled to have a voltage value different from that when a signal is transmitted via the bus line 39.

Here, the reference voltage Vref is the termination voltage VTT.
If it is configured so as not to double as a signal input / output terminal 3
The terminal voltage VTT supplied to the terminals 1 and 32 and the reference voltage Vre
The value is different from f, and the output values of the input circuits 33 and 34 are fixed to H level or L level.

Therefore, in this case, the output circuit 3
Even when the output states of 7 and 38 are all set to the high impedance state, the noises input to the input circuits 33 and 34 through the signal input / output terminals 31 and 32 cause the outputs of the input circuits 33 and 34 to randomly output. Since the H level and the L level are not repeated, malfunction can be prevented.

Further, even when the reference voltage Vref is configured so as to also serve as the termination voltage VTT, the reference voltage Vref is not the optimum bias voltage of the input circuits 33 and 34, so that the influence of noise is eliminated and malfunction occurs. Can be prevented.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, referring to FIGS. 2 to 23, the present invention will be described with respect to the first to sixth embodiments of the bus system according to the present invention and the first and second application examples. The integrated circuit suitable for use in the bus system according to the present invention will be described below by taking the case of application to a bus system adopting a transmission method as an example.

First Embodiment ... FIGS. 2 to 15 FIG. 2 is a circuit diagram showing a main part of a first embodiment of a bus system according to the present invention. In the figure, 47 is a CPU and 48 to 51.
Is SDRAM.

These CPU 47 and SDRAMs 48-5
1, data input / output terminals 52 to 56 and 57 to 6
An input circuit 1 determines the logic of data input to the data input / output terminals 52 to 56.

Further, reference numerals 62 to 66 are input with 1.5 [V] as a reference voltage Vref used for judging the logic of the data input to the data input / output terminals 52 to 56 in the input circuits 57 to 61. This is a reference voltage input terminal.

The input circuits 57 to 61 are composed of differential amplifier circuits whose circuit diagram is shown in FIG.
In the figure, 68 is a VCC power supply line for supplying 3 [V] as a power supply voltage VCC, and 69 and 70 are enhancement type pMOS transistors that form a current mirror circuit.

Further, 71 and 72 are enhancement type pMOS transistors for fixing the output to the H level when they are inactive, and 73 and 74 are enhancement type nMOS transistors forming drive transistors.

Reference numeral 75 is an enhancement type nMOS transistor which forms a constant current source whose on / off is controlled by the reference voltage Vref. V _IN is the voltage of the input data D _IN .

This input circuit has a reference voltage Vref = 1.5.
In the case of [V], the pMOS transistors 71 and 72 are turned off, and the nMOS transistor 75 is turned on and activated.

In this case, when the data voltage V _IN > the reference voltage Vref, the node 76 = L level, and when the data voltage V _IN <the reference voltage Vref, the node 76 =
It is set to H level.

As will be described later, the reference voltage Vref =
In the case of 0 [V], the nMOS transistor 75 =
When it is off, it is inactivated, and the pMOS transistors 71 and 72 are turned on, and the node 76 is fixed to the H level.

Further, in FIG. 2, reference numerals 77 to 81 are output circuits composed of tri-state circuits, and these output circuits 77 to 81 are constructed as shown in the circuit diagram of FIG.

This output circuit has a slew rate (slew rat
e), that is, the rising speed or the falling speed of the output voltage can be selected from three types,
In the following, the case where the slew rate is intermediate is the normal mode, and the case where the slew rate is smaller than the middle is larger than the slow mode and the case where the slew rate is intermediate. If the first
It is called a fast mode.

FIG. 5 shows the output waveform of this output circuit. The solid lines 83 and 84 show changes in the output waveform when the slow mode is selected, and the broken lines 85 and 86 show the output when the normal mode is selected. Waveform change, two-dot chain line 87, 88
Shows the change in the output waveform when the fast mode is selected.

In FIG. 4, 90 is a main push-pull circuit, 91 is a VCC power supply line, 92 is an enhancement type pMOS transistor which forms a pull-up element, and 93 is an enhancement type nMOS transistor which forms a pull-down element. is there.

A push-pull control circuit 94 controls the output of the push-pull circuit 90, and a NAN 95.
D circuit, 96 is a NOR circuit, and 97 is an inverter.

Further, 98 is a push-pull circuit for slew rate adjustment, 99 is a VCC power supply line, 100 is an enhancement type pMOS transistor which forms a pull-up element, and 101 is an enhancement type nMOS transistor which forms a pull-down element. .

Further, 102 is a push-pull control circuit for controlling the output of the push-pull circuit 98, and 103 to 1
Reference numeral 05 is an inverter, 106 to 109 are NAND circuits, 1
Reference numerals 10 to 113 are NOR circuits.

MS1 to MS4 are slew rate mode selection signals for selecting a slew rate mode,
DATA is a data signal to be output.

In this output circuit, when the high impedance state is selected as the output state, the high impedance control signal HiZ = H level, as shown in FIG.

As a result, the output of the inverter 97 = L level, the output of the NAND circuit 95 = H level, the output of the NAND circuit 109 = H level, and the pMOS transistor 92 = OFF and the pMOS transistor 100 = OFF.

In this case, the output of the NOR circuit 96 is L level, the output of the NOR circuit 113 is L level, and the nMOS transistor 93 is off and the nMOS transistor 101 is off.

Thus, the high impedance control signal H
When iZ = H level, the pMOS transistor 92
= Off, nMOS transistor 93 = off, pMOS transistor 100 = off, nMOS transistor 101
= OFF, the output state is a high impedance state.

When operating the push-pull circuits 90 and 98, the high impedance control signal HiZ = L.
In this case, the relationship between the logic of the slew rate mode selection signals MS1 to MS4 and the selected slew rate mode is as shown in Table 1.

[0054]

[Table 1]

Here, for example, when the slow mode is selected, as shown in FIG. 7, high impedance control signal HiZ = L level, slew rate mode selection signal MS1 = L level, slew rate mode. Selection signal MS2 = L level, slew rate mode selection signal MS
3 = H level, slew rate mode selection signal MS4 =
It is set to H level.

As a result, the output of the inverter 97 = H level, the output of the NAND circuit 106 = H level, the output of the NAND circuit 107 = H level, the output of the NOR circuit 110 =
The L level and the output of the NOR circuit 111 are fixed to the L level.

In this case, a one-shot pulse generation circuit composed of NAND circuits 108 and 109 is constructed, and a one-shot pulse generation circuit composed of NOR circuits 112 and 113 is constructed.

FIG. 8 shows the data signal DATA in this state.
8A is a time chart showing an operation when H level changes from H level to L level, and FIG. 8A shows a data signal DATA.

Further, FIG. 8B shows the output of the NAND circuit 95,
FIG. 8C shows the ON / OFF state of the pMOS transistor 92.
8D shows the output of the NOR circuit 96, and FIG. 8E shows the ON / OFF state of the nMOS transistor 93.

8F shows the output of the NAND circuit 108, FIG. 8G shows the output of the NAND circuit 109, and FIG. 8H shows the pM.
The on / off state of the OS transistor 100, N in FIG.
The output of the OR circuit 112, FIG. 8J shows the output of the NOR circuit 113, and FIG. 8K shows the ON / OFF state of the nMOS transistor 101.

When the data signal DATA = H level, the output of the NAND circuit 95 = L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 = L level, the nMOS transistor 93 is turned off.

When the output of the NAND circuit 108 is L level and the output of the NAND circuit 109 is H level, the pMOS is
The transistor 100 is turned off, the output of the NOR circuit 112 is L level, and the output of the NOR circuit 113 is L.
At the level, the nMOS transistor 101 is turned off.

Therefore, in this case, the output voltage of this output circuit is set to H level by the pMOS transistor 92.
The level will be maintained.

When the data signal DATA changes from H level to L level, the output of the NAND circuit 95 = H.
Level, the pMOS transistor 92 is turned off, the output of the NOR circuit 96 is set to H level, and nM
The OS transistor 93 is turned on.

Further, the output of the NAND circuit 108 becomes H level, but in this case, the output of the NAND circuit 108 is L level.
The timing of changing from the level to the H level is delayed from the timing of changing the data signal DATA from the H level to the L level by the delay time ΔT ₁₀₈ of the NAND circuit 108.

Therefore, in this case, since the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA, the NAND circuit 10
9 output = H level, pMOS transistor 1
00 = Keep off.

On the other hand, the output of the NOR circuit 112 becomes H level. In this case, the timing when the output of the NOR circuit 112 changes from L level to H level is the data signal D.
It is delayed by the delay time ΔT ₁₁₂ of the NOR circuit 112 from the timing when ATA changes from the H level to the L level.

As a result, when the data signal DATA changes from the H level to the L level, the output of the NOR circuit 113 is NO after the delay time ΔT ₁₁₃ of the NOR circuit _{113 has} elapsed.
Only delay time [Delta] T ₁₁₂ of R circuit 112 becomes H level, then returns to the L level.

Therefore, the nMOS transistor 101
When the data signal DATA changes from the H level to the L level, after the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses,
The NOR circuit 112 is turned on for the delay time ΔT ₁₁₂ , and then turned off.

As described above, when the data signal DATA changes from the H level to the L level when the slow mode is selected,
The pMOS transistor 92 = off and the nMOS transistor 93 = on.

Further, the pMOS transistor 100 maintains the off state, and the nMOS transistor 101 is NO.
The delay time of the R circuit 112 is turned on by ΔT ₁₁₂ , and thereafter, it is turned off again.

Therefore, in this case, the output of this output circuit changes from the H level to the L level according to the change of the data signal DATA, but from the H level to the L level by the delay time ΔT ₁₁₂ of the NOR circuit 112. Is accelerated and changes as shown by a solid line 83 in FIG.

FIG. 9 is a time chart showing the operation when the data signal DATA changes from the L level to the H level in the slow mode selection.
Indicates the data signal DATA.

Further, FIG. 9B shows the output of the NAND circuit 95,
FIG. 9C shows an ON / OFF state of the pMOS transistor 92.
9D shows the output of the NOR circuit 96, and FIG. 9E shows the ON / OFF state of the nMOS transistor 93.

9F shows the output of the NAND circuit 108, FIG. 9G shows the output of the NAND circuit 109, and FIG. 9H shows the pM.
The on / off state of the OS transistor 100, N in FIG. 9I
The output of the OR circuit 112, FIG. 9J shows the output of the NOR circuit 113, and FIG. 9K shows the ON / OFF state of the nMOS transistor 101.

When the data signal DATA = L level, the output of the NAND circuit 95 = H level, the pMOS transistor 92 is turned off, and
When the output of the NOR circuit 96 = H level, the nMOS transistor 93 is turned on.

When the output of the NAND circuit 108 is H level and the output of the NAND circuit 109 is H level, the pMOS
Transistor 100 = off and NOR
The output of the circuit 112 = H level, the output of the NOR circuit 113 = L level, and the nMOS transistor 101 is turned off.

Therefore, in this case, the output voltage of this output circuit is L level by the nMOS transistor 93.
The level will be maintained.

When the data signal DATA changes from the L level to the H level, the output of the NAND circuit 95 = L.
And the pMOS transistor 92 is turned on, the output of the NOR circuit 96 is set to L level, and nM
The OS transistor 93 is turned off.

Further, the output of the NAND circuit 108 becomes L level, but in this case, the output of the NAND circuit 108 becomes H level.
The timing of changing from the level to the L level is delayed by the delay time ΔT ₁₀₈ of the NAND circuit 108 from the timing of changing the data signal DATA from the L level to the H level.

As a result, the output of the NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses and then N
Only delay time [Delta] T ₁₀₈ of the AND circuit 108 becomes the L level, then returns to the H level.

Therefore, the pMOS transistor 100
When the data signal DATA changes from the L level to the H level, after the delay time ΔT _{109 of} the NAND circuit ₁₀₉ elapses, the NAND circuit 108 is turned on for the delay time ΔT ₁₀₈ , and then returned to the off state.

On the other hand, the output of the NOR circuit 112 becomes L level. In this case, the timing when the output of the NOR circuit 112 changes from H level to L level is the data signal D.
The timing at which ATA changes from L level to H level is delayed by the delay time ΔT ₁₁₂ of the NOR circuit 112.

As a result, in this case, the NOR circuit 11
Since the H level is input to the input side of 3 before and after the change of the data signal DATA, the NOR circuit 1
The output of 13 = L level is maintained and the nMOS transistor 101 = OFF is maintained.

As described above, when the data signal DATA changes from the L level to the H level when the slow mode is selected,
The pMOS transistor 92 = on and the nMOS transistor 93 = off.

Further, the pMOS transistor 100 has N
Only delay time [Delta] T ₁₀₈ of the AND circuit 108 turns on, then, returns to off, nMOS transistors 1
01 remains off.

Therefore, in this case, the output of the output circuit changes from the L level to the H level according to the change of the data signal DATA, but the delay time ΔT ₁₀₈ of the NAND circuit 108 changes from the L level to the H level. Is accelerated and changes as shown by a solid line 84 in FIG.

When the normal mode is selected, as shown in FIG. 10, the high impedance control signal HiZ = L level, the slew rate mode selection signal MS.
1 = H level, slew rate mode selection signal MS2 =
L level, slew rate mode selection signal MS3 = L level, slew rate mode selection signal MS4 = H level.

As a result, the output of the inverter 97 is fixed to the H level, the output of the NAND circuit 107 is fixed to the H level, and the output of the NOR circuit 111 is fixed to the L level.

In this case, the one-shot pulse generating circuit including the inverter 103 and the NAND circuits 106, 108, and 109 is configured, and the inverter 103,
A one-shot pulse generation circuit composed of NOR circuits 110, 112, 113 is configured.

FIG. 11 is a time chart showing the operation when the data signal DATA changes from the H level to the L level in this state, and FIG. 11A shows the data signal D.
It shows ATA.

11B shows the output of the NAND circuit 95, FIG. 11C shows the ON / OFF state of the pMOS transistor 92, FIG. 11D shows the output of the NOR circuit 96, and FIG. 11E shows n.
The ON and OFF states of the MOS transistor 93 are shown.

11F shows the output of the NAND circuit 108, FIG. 11G shows the output of the NAND circuit 109, and FIG. 11H shows the ON / OFF state of the pMOS transistor 100.
I is the output of the NOR circuit 112, and FIG. 11J is the NOR circuit 1
13K, FIG. 11K shows the on / off state of the nMOS transistor 101.

Here, when the data signal DATA = H level, the output of the NAND circuit 95 = L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 = L level, the nMOS transistor 93 is turned off.

The output of the inverter 103 = L level, the output of the NAND circuit 106 = H level, the output of the NAND circuit 108 = L level, the output of the NAND circuit 109 = H level, and the pMOS transistor 100 = OFF.

The output of the NOR circuit 110 = H level, the output of the NOR circuit 112 = L level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off

Therefore, in this case, the output voltage of this output circuit is set to H level by the pMOS transistor 92.
The level will be maintained.

When the data signal DATA changes from the H level to the L level, the output of the NAND circuit 95 = H.
Level, the pMOS transistor 92 is turned off, the output of the NOR circuit 96 is set to H level, and nM
The OS transistor 93 is turned on.

When the output of the inverter 103 = H level and the output of the NAND circuit 106 = L level,
The output of the circuit 108 = H level.

In this case, the output of the NAND circuit 108 is L
The timing at which the level changes from H level to the H level is longer than the delay time ΔT ₁₀₃ + NA of the inverter 103 than the timing at which the data signal DATA changes from H level to L level.
Delay time of ND circuit 106 ΔT ₁₀₆ + NAND circuit 10
It is delayed by ΔT _{108 by} the delay time of 8.

Therefore, in this case, since the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA, the NAND circuit 10
9 output = H level, pMOS transistor 1
00 = Keep off.

On the other hand, the output of the NOR circuit 110 = L level and the output of the NOR circuit 112 = H level.

In this case, the timing at which the output of the NOR circuit 112 changes from the L level to the H level is longer than the timing at which the data signal DATA changes from the H level to the L level by the delay time ΔT ₁₀₃ + NOR of the inverter 103.
The delay time of the circuit 110 is ΔT ₁₁₀ + the delay time of the NOR circuit 112 is delayed by ΔT ₁₁₂ .

As a result, when the data signal DATA changes from the H level to the L level, the output of the NOR circuit 113 outputs the delay time ΔT 103 of the inverter ₁₀₃ + the delay time of the NOR circuit 110 after the delay time ΔT ₁₁₃ of the NOR circuit 113 has elapsed. ΔT ₁₁₀ + ΔT of delay time of NOR circuit 112
Only ₁₁₂ goes to H level, and then returns to L level.

Therefore, the nMOS transistor 101
When the data signal DATA changes from the H level to the L level, after the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses ,
Delay time of inverter 103 ΔT ₁₀₃ + NOR circuit 11
Only delay time [Delta] T ₁₁₂ of the delay time of 0 [Delta] T ₁₁₀ + NOR circuit 112 turns on, then returns to the off.

As described above, in the normal mode selection, when the data signal DATA changes from the H level to the L level, the pMOS transistor 92 = off and the nMOS transistor 93 = on.

Further, the pMOS transistor 100 maintains the off state, and the nMOS transistor 101 has the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT _{110 of the} NOR circuit ₁₁₀ + the delay time ΔT 112 of the NOR circuit _112.
Only turned on and then turned off again.

Therefore, in this case, the output of this output circuit changes from the H level to the L level in accordance with the change of the data signal DATA, but the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT ₁₁₀ + N of the NOR circuit 110.
Only delay time [Delta] T ₁₁₂ of the OR circuit 112, changes from H level L level is accelerated, changes as shown by the broken line 85 shown in FIG.

FIG. 12 is a time chart showing the operation when the data signal DATA changes from the L level to the H level in the normal mode selection, and FIG. 12A shows the data signal DATA.

12B shows the output of the NAND circuit 95, FIG. 12C shows the ON / OFF state of the pMOS transistor 92, FIG. 8D shows the output of the NOR circuit 96, and FIG. 12E shows nM.
The ON and OFF states of the OS transistor 93 are shown.

12F shows the output of the NAND circuit 108, FIG. 12G shows the output of the NAND circuit 109, FIG. 12H shows the ON / OFF state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG. 12J is the NOR circuit 1
13K, FIG. 12K shows the on / off state of the nMOS transistor 101.

Here, when the data signal DATA = L level, the output of the NAND circuit 95 = H level, the pMOS transistor 92 = OFF, and
When the output of the NOR circuit 96 = H level, the nMOS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the NAND circuit 106 = L level, the output of the NAND circuit 108 = H level, the output of the NAND circuit 109 = H level, and the pMOS transistor 100 = OFF. .

The output of the NOR circuit 110 = L level, the output of the NOR circuit 112 = H level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off

Therefore, in this case, the output voltage of this output circuit is L level by the nMOS transistor 93.
The level will be maintained.

When the data signal DATA changes from the L level to the H level, the output of the NAND circuit 95 = L.
And the pMOS transistor 92 is turned on, the output of the NOR circuit 96 is set to L level, and nM
The OS transistor 93 is turned off.

Further, the output of the inverter 103 = L level, the output of the NAND circuit 106 = H level, and the output of the NAND circuit 108 = L level.

In this case, the output of the NAND circuit 108 is H
The timing of changing from the level to the L level is the delay time ΔT ₁₀₃ + NA of the inverter 103 than the timing of changing the data signal DATA from the L level to the H level.
Delay time of ND circuit 106 ΔT ₁₀₆ + NAND circuit 10
It is delayed by ΔT _{108 by} the delay time of 8.

As a result, the output of the NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit 109 has elapsed, the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the NAND circuit 10
The delay time ΔT _{106 of} 6 + ΔT ₁₀₈ corresponding to the delay time of the NAND circuit 108 becomes the L level, and then returns to the H level.

Therefore, the pMOS transistor 100
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT _{106 of the} NAND circuit ₁₀₆ + the delay time ΔT 108 of the NAND circuit _108. Only turned on and then turned off again.

On the other hand, the output of the NOR circuit 110 = H level and the output of the NOR circuit 112 = L level.

In this case, the timing when the output of the NOR circuit 112 changes from the H level to the L level is longer than the timing when the data signal DATA changes from the L level to the H level by the delay time ΔT ₁₀₃ + NOR of the inverter 103.
The delay time of the circuit 110 is ΔT ₁₁₀ + the delay time of the NOR circuit 112 is delayed by ΔT ₁₁₂ .

As a result, in this case, the NOR circuit 11
Since the H level is input to the input side of 3 before and after the change of the data signal DATA, the NOR circuit 1
The output of 13 = L level is maintained and the nMOS transistor 101 = OFF is maintained.

As described above, in the normal mode selection, when the data signal DATA changes from the L level to the H level, the pMOS transistor 92 = on and the nMOS transistor 93 = off.

Further, the pMOS transistor 100 has the delay time ΔT ₁₀₃ + NAND circuit 10 of the inverter 103.
Only delay time [Delta] T ₁₀₈ of the delay time [Delta] T ₁₀₆ + NAND circuit 108 of 6 turned on, thereafter, returns to OFF,
The nMOS transistor 101 maintains the off state.

Therefore, in this case, the output of this output circuit changes from the L level to the H level according to the change of the data signal DATA, but the delay time ΔT ₁₀₃ of the inverter ₁₀₃ + the delay time ΔT _{106 of the} NAND circuit _106. +
Only delay time [Delta] T ₁₀₈ of the NAND circuit 108, a change in H level is accelerated from the L level, the broken lines shown in FIG. 5 86
It changes like.

When the fast mode is selected, as shown in FIG. 13, the high impedance control signal HiZ = L level, the slew rate mode selection signal M.
S1 = L level, slew rate mode selection signal MS2
= H level, slew rate mode selection signal MS3 = H
Level, slew rate mode selection signal MS4 = L level.

As a result, the output of the inverter 97 is fixed at the H level, the output of the NAND circuit 106 is fixed at the H level, and the output of the NOR circuit 110 is fixed at the L level.

In this case, the inverters 103 to 105, N
A one-shot pulse generation circuit composed of AND circuits 107-109 is constructed, and inverters 103-
A one-shot pulse generation circuit including 105 and NOR circuits 111 to 113 is configured.

FIG. 14 is a time chart showing the operation when the data signal DATA changes from the H level to the L level in this state, and FIG. 14A shows the data signal D.
It shows ATA.

14B shows the output of the NAND circuit 95, FIG. 14C shows the ON / OFF state of the pMOS transistor 92, FIG. 14D shows the output of the NOR circuit 96, and FIG. 14E shows n.
The ON and OFF states of the MOS transistor 93 are shown.

FIG. 14F shows the output of the NAND circuit 108, FIG. 14G shows the output of the NAND circuit 109, and FIG. 14H shows the ON / OFF state of the pMOS transistor 100.
I is the output of the NOR circuit 112, and FIG. 14J is the NOR circuit 1
13K, FIG. 14K shows the on / off state of the nMOS transistor 101.

Here, when the data signal DATA = H level, the output of the NAND circuit 95 = L level, the pMOS transistor 92 is turned on, and
When the output of the NOR circuit 96 = L level, the nMOS transistor 93 is turned off.

The output of the inverter 103 = L level, the output of the inverter 104 = H level, the inverter 1
05 output = L level, NAND circuit 107 output = H
Level, output of NAND circuit 108 = L level, NAN
When the output of the D circuit 109 = H level, the pMOS transistor 100 = OFF.

The output of the NOR circuit 111 = H level, the output of the NOR circuit 112 = L level, the NOR circuit 1
13 output = L level, the nMOS transistor 101
= Off

Therefore, in this case, the output voltage of this output circuit is set to H level by the pMOS transistor 92.
The level will be maintained.

When the data signal DATA changes from the H level to the L level, the output of the NAND circuit 95 = H.
Level, the pMOS transistor 92 is turned off, the output of the NOR circuit 96 is set to H level, and nM
The OS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the inverter 104 = L level, the inverter 1
05 output = H level, NAND circuit 107 output = L
Level, the output of the NAND circuit 108 = H level.

In this case, the timing at which the output of the NAND circuit 108 changes from the L level to the H level is delayed by the delay time ΔT ₁₀₃ + of the inverter 103 rather than the timing at which the data signal DATA changes from the H level to the L level.
Delay time of inverter 104 ΔT ₁₀₄ + inverter 10
5 delay time ΔT ₁₀₅ + NAND circuit 107 delay time ΔT ₁₀₇ + NAND circuit 108 delay time ΔT ₁₀₈ .

Therefore, since the L level is input to the input side of the NAND circuit 109 before and after the change of the data signal DATA, the output of the NAND circuit 109 becomes the H level and the pMOS transistor 100 maintains the off state.

On the other hand, the output of the NOR circuit 111 = L level and the output of the NOR circuit 112 = H level.

In this case, the timing when the output of the NOR circuit 112 changes from the L level to the H level is longer than the timing when the data signal DATA changes from the H level to the L level by the delay time ΔT ₁₀₃ + inverter 104 of the inverter ₁₀₃ . Delay time ΔT ₁₀₄ + Delay time of inverter 105 ΔT ₁₀₅ + Delay time of NOR circuit 111 ΔT ₁₁₁ +
The delay time of the NOR circuit 112 is delayed by ΔT ₁₁₂ .

As a result, when the data signal DATA changes from the H level to the L level, the output of the NOR circuit 113 outputs the delay time ΔT ₁₀₃ + the delay time of the inverter 104 after the delay time ΔT ₁₁₃ of the NOR circuit 113 has elapsed. ΔT ₁₀₄ + delay time of inverter 105 ΔT ₁₀₅
+ NOR circuit 111 delay time ΔT ₁₁₁ + NOR circuit 1
After the delay time of 12, ΔT _{112, the} H level is reached, and then the L level is restored.

Therefore, the nMOS transistor 101
When the data signal DATA changes from the H level to the L level, after the delay time ΔT ₁₁₃ of the NOR circuit ₁₁₃ elapses ,
Inverter 103 delay time ΔT ₁₀₃ + inverter 10
4 delay time ΔT ₁₀₄ + inverter 105 delay time Δ
Only turned on delay time [Delta] T ₁₁₂ a delay time of T ₁₀₅ + NOR circuit 111 [Delta] T ₁₁₁ + NOR circuit 112, then returns to the off.

Thus, when the first mode is selected,
When the data signal DATA changes from the H level to the L level, the pMOS transistor 92 = off and the nMOS transistor 93 = on.

Further, the pMOS transistor 100 maintains the off state, and the nMOS transistor 101 has the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + the delay time ΔT ₁₀₅ + of the inverter 105.
NOR circuit 111 delay time ΔT ₁₁₁ + NOR circuit 11
After the delay time of 2, ΔT _{112 is} turned on, and then it is turned off again.

Therefore, in this case, the output of this output circuit changes from the H level to the L level according to the change of the data signal DATA, but the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + Inverter 105 delay time ΔT ₁₀₅ + NOR circuit 111
Delay time ΔT ₁₁₁ + the delay time of NOR circuit 112 Δ
Only at T ₁₁₂ , the change from H level to L level is accelerated,
It changes like the alternate long and two short dashes line 87 shown in FIG.

FIG. 15 is a time chart showing the operation when the data signal DATA changes from the L level to the H level when the fast mode is selected.
FIG. 15A shows the data signal DATA.

15B shows the output of the NAND circuit 95, FIG. 15C shows the ON / OFF state of the pMOS transistor 92, FIG. 15D shows the output of the NOR circuit 96, and FIG. 15E shows n.
The ON and OFF states of the MOS transistor 93 are shown.

15F shows the output of the NAND circuit 108, FIG. 15G shows the output of the NAND circuit 109, FIG. 15H shows the ON / OFF state of the pMOS transistor 100, and FIG.
I is the output of the NOR circuit 112, and FIG. 15J is the NOR circuit 1
13K, FIG. 15K shows the ON / OFF state of the nMOS transistor 101.

When the data signal DATA = L level, the output of the NAND circuit 95 = H level, the pMOS transistor 92 is turned off, and
When the output of the NOR circuit 96 = H level, the nMOS transistor 93 is turned on.

The output of the inverter 103 = H level, the output of the inverter 104 = L level, the inverter 1
05 output = H level, NAND circuit 107 output = L
Level, output of NAND circuit 108 = H level, NAN
When the output of the D circuit 109 = H level, the pMOS transistor 100 = OFF.

The output of the NOR circuit 111 = L level, the output of the NOR circuit 112 = H level, the NOR circuit 1
13 output = H level, the nMOS transistor 101
= Off

Therefore, in this case, the output voltage of this output circuit is L level by the nMOS transistor 93.
The level will be maintained.

When the data signal DATA changes from the L level to the H level, the output of the NAND circuit 95 = L.
And the pMOS transistor 92 is turned on, the output of the NOR circuit 96 is set to L level, and nM
The OS transistor 93 is turned off.

The output of the inverter 103 = L level, the output of the inverter 104 = H level, the inverter 1
05 output = L level, NAND circuit 107 output = H
At the level, the output of the NAND circuit 108 becomes the L level.

In this case, the timing when the output of the NAND circuit 108 changes from the H level to the L level is longer than the timing when the data signal DATA changes from the L level to the H level by the delay time ΔT ₁₀₃ + of the inverter 103.
Delay time of inverter 104 ΔT ₁₀₄ + inverter 10
5 delay time ΔT ₁₀₅ + NAND circuit 107 delay time ΔT ₁₀₇ + NAND circuit 108 delay time ΔT ₁₀₈ .

As a result, the output of the NAND circuit 109 is
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, the delay time ΔT _{103 of the} inverter ₁₀₃ + the inverter 104
Delay time ΔT ₁₀₄ + inverter 105 delay time ΔT
₁₀₅ + NAND circuit 107 delay time ΔT ₁₀₇ + NAND
The delay time of the circuit 108 is delayed by ΔT ₁₀₈ .

Therefore, the pMOS transistor 100
When the data signal DATA changes from the L level to the H level, after the delay time ΔT ₁₀₉ of the NAND circuit ₁₀₉ elapses, the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + the delay time ΔT _{105 of the} inverter ₁₀₅ + NAND Delay time of circuit 107 ΔT ₁₀₇ + N
The AND circuit 108 is turned on for the delay time ΔT ₁₀₈ , and then turned off.

On the other hand, the output of the NOR circuit 111 = H level and the output of the NOR circuit 112 = L level.

In this case, the timing at which the output of the NOR circuit 112 changes from the H level to the L level is longer than the timing at which the data signal DATA changes from the L level to the H level by the delay time ΔT ₁₀₃ + inverter 104 of the inverter ₁₀₃ . Delay time ΔT ₁₀₄ + Delay time of inverter 105 ΔT ₁₀₅ + Delay time of NOR circuit 111 ΔT ₁₁₁ +
The delay time of the NOR circuit 112 is delayed by ΔT ₁₁₂ .

As a result, since the H level is input to the input side of the NOR circuit 113 before and after the change of the data signal DATA, the output of the NOR circuit 113 = L.
The level is maintained, and the nMOS transistor 101 = off state is maintained.

Thus, when the first mode is selected,
When the data signal DATA changes from the L level to the H level, the pMOS transistor 92 = on and the nMOS transistor 93 = off.

Further, the pMOS transistor 100 is
Delay time of inverter 103 ΔT₁₀₃+ Inverter 104
Delay time ΔT₁₀₄+ Delay time ΔT of the inverter 105
₁₀₅+ Delay time ΔT of NAND circuit 107₁₀₇+ NAND
Delay time ΔT of the circuit 108_{1 08}Only turned on and that
After that, the nMOS transistor 101 is turned off again.
To maintain a good condition.

Therefore, in this case, the output of this output circuit changes from the L level to the H level according to the change of the data signal DATA, but the delay time ΔT _{103 of the} inverter ₁₀₃ + the delay time ΔT _{104 of the} inverter ₁₀₄ + Inverter 105 delay time ΔT ₁₀₅ + NAND circuit 10
Only delay time [Delta] T ₁₀₈ of the delay time [Delta] T ₁₀₇ + NAND circuit 108 of 7, changes from L level H level is accelerated, changes as indicated by two-dot chain line 88 shown in FIG.

Further, in FIG. 2, 115 is the output circuit 7.
7 is an output state signal output terminal from which an output state signal / OE indicating whether or not the output state of 7 is in the high impedance state is output.

Here, when the output state signal / OE = H level, it means that the output state of the output circuit 77 is in the high impedance state, and when the output state signal / OE = L level, the output circuit 77. Means the data output state.

Reference numeral 116 denotes a data output prohibition signal output terminal for outputting the data output prohibition signal DQM1 for prohibiting the output of data from the data input / output terminal 53 by setting the output state of the output circuit 78 of the SDRAM 48 to the high impedance state. Reference numeral 117 is a data output prohibition signal input terminal to which the data output prohibition signal DQM1 is input.

Here, the data output inhibition signal DQM1 = H
In the case of the level, the output state of the output circuit 78 is in the high impedance state, and in the case of the data output inhibition signal DQM1 = L level, the output circuit 78 is in the data output state.

Reference numeral 118 denotes a data output prohibition signal output terminal 119 which outputs the data output prohibition signal DQM2 for prohibiting the output of data from the data input / output terminal 54 by setting the output state of the output circuit 79 of the SDRAM 49 to the high impedance state. Is a data output inhibition signal input terminal to which the data output inhibition signal DQM2 is input.

Here, the data output inhibition signal DQM2 = H
In the case of the level, the output state of the output circuit 79 is in the high impedance state, and in the case of the data output inhibition signal DQM2 = L level, the output circuit 79 is in the data output state.

Reference numeral 120 denotes a data output prohibition signal output terminal for outputting the data output prohibition signal DQM3 for prohibiting the output of data from the data input / output terminal 55 by setting the output state of the output circuit 80 of the SDRAM 50 to the high impedance state. Is a data output inhibit signal input terminal to which the data output inhibit signal DQM3 is input.

Here, the data output inhibition signal DQM3 = H
In the case of the level, the output state of the output circuit 80 is in the high impedance state, and in the case of the data output inhibition signal DQM3 = L level, the output circuit 80 is in the data output state.

Reference numeral 122 denotes a data output prohibition signal output terminal for outputting a data output prohibition signal DQM4 for prohibiting the output of data from the data input / output terminal 56 by setting the output state of the output circuit 81 of the SDRAM 51 to a high impedance state, 123. Is a data output inhibition signal input terminal to which the data output inhibition signal DQM4 is input.

Here, the data output inhibition signal DQM4 = H
In the case of the level, the output state of the output circuit 81 is in the high impedance state, and in the case of the data output inhibition signal DQM4 = L level, the output circuit 81 is in the data output state.

Reference numeral 124 is the CPU 47 and SDRAM.
A bus line to which the data input / output terminals 52 to 56 of 48 to 51 are commonly connected, 125 is a terminating resistor on the CPU 47 side, and 12
Reference numeral 6 is a terminating resistor on the side of the SDRAMs 48 to 51, and 127 is a reference voltage line for supplying a reference voltage Vref which also serves as a terminating voltage.

Further, 128 is 1.5 as the reference voltage Vref.
A reference voltage generation circuit 129 that outputs [V] is a reference voltage control circuit that controls the reference voltage Vref to be supplied to the reference voltage line 127.

In this reference voltage control circuit 129, 1
An output state determination circuit 30 determines whether the output states of the CPU 47 and the output circuits 77 to 81 of the SDRAMs 48 to 51 are all in the high impedance state.

Here, 131 is an N to which the output state signal / OE and the data output prohibition signals DQM1 to DQM4 are input.
An AND circuit, 132 is an inverter that inverts the output of the NAND circuit 131.

Further, 133 is a reference voltage switching circuit for switching the voltage value of the reference voltage Vref to be supplied to the reference voltage line 127, and 134 and 135 are enhancement type n.
The MOS transistors 136 and 137 are enhancement type pMOS transistors.

That is, the nMOS transistor 134 and pM
The OS transistor 136 forms one analog switch, and the nMOS transistor 135 and the pMOS transistor 137 form one analog switch.

Here, when any of the output state signal / OE and the data output inhibition signals DQM1 to DQM4 is at L level, that is, the data is output from any of the data input / output terminals 52 to 56. If yes, NA
The output of the ND circuit 131 = H level and the output of the inverter 132 = L level.

As a result, the nMOS transistor 134 =
ON, pMOS transistor 136 = ON, nMOS transistor 135 = OFF, pMOS transistor 137
= Off.

Therefore, the reference voltage Vref of 1.5 [V] output from the reference voltage generation circuit 128 is the reference voltage line 1
It is supplied to the reference voltage input terminals 62 to 66 of the CPU 47 and SDRAMs 48 to 51 via 27.

On the other hand, when the output state signal / OE = H level and the data output inhibition signals DQM1 to DQM4 = H level, that is, the CPU 47 and the SDRAMs 48 to 51.
When all the output states of the output circuits 77 to 81 are set to the high impedance state, the output of the NAND circuit 131 =
The L level and the output of the inverter 132 = H level.

As a result, the nMOS transistor 134 =
OFF, pMOS transistor 136 = OFF, nMOS transistor 135 = ON, pMOS transistor 137
= Turned on.

Therefore, the reference voltage line 127 is connected to nMO.
S transistor 135 and pMOS transistor 137
Grounded via the CPU 47 and SDRAMs 48-5.
Ground voltage 0 [V] is applied to the reference voltage input terminals 62 to 66 of No. 1
Is supplied, the input circuits 57 to 61 are deactivated, and the output is fixed to the H level as described above.

As described above, according to the first embodiment, the data input / output terminals 52 to 5 connected to the bus line 124 are connected.
Even if the output states of the output circuits 77 to 81 whose output terminals are connected to 6 are all in the high impedance state, malfunction due to noise input to the input circuits 57 to 61 can be prevented, and reliability is improved. Can be improved.

Further, in the first embodiment, the CPU
47 and SDRAM 48-51 input circuits 57-61
Is configured to be inactive when the supplied reference voltage Vref is set to 0 [V], so that it is possible to prevent unnecessary current from flowing and reduce power consumption. Can be planned.

Further, in the first embodiment, the CPU
47 and the output circuits 77 to 81 of the SDRAMs 48 to 51 are configured so that the slew rate can be selected. Therefore, the parasitic capacitance around the data input / output terminals 52 to 56 may vary depending on the chip mounting method and the board design. Even when the value is different from the expected value, the output waveform can be optimized.

Second Embodiment FIG. 16 FIG. 16 is a circuit diagram showing the essential parts of a second embodiment of the bus system according to the present invention. This second embodiment is provided with the first embodiment. A reference voltage control circuit 129 having a circuit configuration different from that of the reference voltage control circuit 129 is provided.
The configuration is similar to that of the first embodiment.

This reference voltage control circuit 139 is provided with a reference voltage switching circuit 133 having a circuit configuration different from that of the reference voltage switching circuit 133 provided in the reference voltage control circuit 129, and other points are similar to those of the reference voltage control circuit 129. It is composed.

Here, in the reference voltage switching circuit 140, 141 is an inverter having a high voltage side power supply voltage as a reference voltage Vref and a low voltage side power supply voltage as a ground voltage 0 [V], and 142 is an enhancement type. The pMOS transistor 143 is an enhancement type nMOS transistor.

Here, when any of the output state signal / OE and the data output inhibition signals DQM1 to DQM4 is at the L level, that is, the data is output from any of the data input / output terminals 52 to 56. If yes, NA
The output of the ND circuit 131 = H level and the output of the inverter 132 = L level.

As a result, the pMOS transistor 142 =
On, the nMOS transistor 143 is turned off, and 1.5 [V] is supplied as the reference voltage Vref to the reference voltage input terminals 62 to 66 via the reference voltage line 127.

On the other hand, when the output state signal / OE = H level and the data output inhibition signals DQM1 to DQM4 = H level, that is, the CPU 47 and the SDRAMs 48 to 51.
When all the output states of the output circuits 77 to 81 are set to the high impedance state, the output of the NAND circuit 131 =
The L level and the output of the inverter 132 = H level.

As a result, the pMOS transistor 142 =
The nMOS transistor 143 is turned off, and the reference voltage input terminals 62 to 66 are supplied with the ground voltage 0 [V] as the reference voltage Vref via the reference voltage line 127.

Therefore, also in this second embodiment,
As in the case of the first embodiment, when the output states of the output circuits 77 to 81 are all set to the high impedance state, malfunctions due to noise input to the input circuits 57 to 61 are prevented and power consumption is reduced. The output waveform can be optimized.

Third Embodiment FIG. 17 FIG. 17 is a circuit diagram showing an essential part of a third embodiment of the bus system according to the present invention. This third embodiment has CPU 47 and SDRAM 48 shown in FIG. The input circuits 57 to 61 mounted on 51 are configured as shown in the circuit diagram of FIG. 17, and the other components are configured similarly to the first embodiment shown in FIG.

The input circuit shown in FIG. 17 includes the drain of the nMOS transistor 73 and the nMOS transistor 7
A noise canceling capacitor 145 is connected between the gate and the gate of No. 4 and the other components are similar to those of the input circuit shown in FIG.

When the nMOS transistor 73 receives a so-called differential noise having a sharp rising and falling edge, the differential noise causes the gate-source capacitance of the nMOS transistor 73 and the source-gate capacitance of the nMOS transistor 74. Via the gate of the nMOS transistor 74, that is, as indicated by a broken line 146,
It may be transmitted to the reference voltage system.

However, according to the input circuit shown in FIG. 17, differential noise, which is the inversion of the differential noise input to the gate of the nMOS transistor 73, appears at the drain of the nMOS transistor 73. As shown in FIG.
It can be transmitted to the gate of the S-transistor 74.

As a result, differential noise transmitted to the gate of the nMOS transistor 74 via the capacitor 145 can cancel the noise mixed in the reference voltage system as shown by the broken line 146.

Therefore, according to the third embodiment, as in the case of the first embodiment, the output circuits 77 to 81 are input to the input circuits 57 to 61 when all the output states are in the high impedance state. It is possible to prevent malfunction due to noise, reduce power consumption, optimize output waveforms, and input circuits 57 to 6 during data transmission.
It is possible to prevent malfunction due to the differential noise input to 1.

Fourth Embodiment FIG. 18 FIG. 18 is a circuit diagram showing the essential parts of a fourth embodiment of the bus system according to the present invention. The fourth embodiment is the CPU 47 and SDRAM 48 shown in FIG. The input circuits 57 to 61 mounted on the 51 are configured as shown in the circuit diagram of FIG. 18, and the other components are configured similarly to the first embodiment shown in FIG.

In the input circuit shown in FIG. 18, instead of connecting the gate of pMOS transistor 70 to the drain of nMOS transistor 74, pMOS transistor 6
The gate of 9 is connected to the drain of the nMOS transistor 73, and the output is obtained not from the drain of the nMOS transistor 73 but from the drain of the nMOS transistor 74.
It is configured similarly to the input circuit shown in FIG.

Also in the input circuit shown in FIG. 18, n
When the differential noise having a large slew rate is input to the MOS transistor 73, the differential noise passes through the gate-source capacitance of the nMOS transistor 73 and the source-gate capacitance of the nMOS transistor 74 as shown by a broken line 146. , The gate of the nMOS transistor 74, that is, the reference voltage system may be transmitted.

However, according to the input circuit shown in FIG. 18, differential noise, which is the inverted differential noise input to the gate of the nMOS transistor 73, appears at the drain of the nMOS transistor 73. This differential noise is indicated by the arrow 147. As shown in FIG.
It can be transmitted to the gate of the S-transistor 74.

As a result, the differential noise transmitted to the gate of the nMOS transistor 74 via the capacitor 145 can cancel the noise mixed in the reference voltage system as shown by the broken line 146.

Therefore, according to the fourth embodiment, as in the case of the first embodiment, the output circuits 77 to 81 are input to the input circuits 57 to 61 when all the output states are in the high impedance state. It is possible to prevent malfunction due to noise, reduce power consumption, and optimize output waveform.

Further, according to the fourth embodiment, like the third embodiment, it is possible to prevent malfunction due to differential noise input to the input circuits 57 to 61 during data transmission.

Fifth Embodiment FIG. 19 and FIG. 20 FIG. 19 is a circuit diagram showing an essential part of a fifth embodiment of the bus system according to the present invention. This fifth embodiment is a CPU 47 shown in FIG. , The input circuits 57 to 61 mounted on the SDRAMs 48 to 51 are configured as shown in the circuit diagram of FIG. 19, and the others are configured similarly to the first embodiment shown in FIG.

The input circuit shown in FIG. 19 can be applied to a signal transmission system in which a voltage lower than the intermediate voltage in the T-LVTTL transmission system is used as the driving transistor. For example, depletion type nMOS transistors 148 and 149 having a negative threshold voltage are provided, and the other parts are configured similarly to the input circuit shown in FIG.

The gain-bandwidth product GBW of the input circuit shown in FIG. 19 is as shown by the solid line X in FIG. The broken line Y indicates the gain / bandwidth product GBW when an enhancement type nMOS transistor is used as the drive transistor.

Therefore, in the input circuit shown in FIG. 19, when the reference voltage Vref is set to 1.5 [V], the intermediate voltage is set to 1.5 [V], and a small amount of ± 0.4 [V] is set. It can be used in a T-LVTTL transmission method for transmitting a signal.

When the reference voltage Vref is set to 0.8 [V], the intermediate voltage is set to 0.8 [V] and ± 0.4.
GTL (Gunning) that attempts to transmit a minute signal of [V]
It can also be used for the Tran-sisitor Logic transmission method.

According to the fifth embodiment, as in the case of the first embodiment, the input circuits 57 to 81 when the output states of the output circuits 77 to 81 are all in the high impedance state.
A malfunction due to noise input to 61 can be prevented, power consumption can be reduced, an output waveform can be optimized, and a highly convenient integrated circuit can be used.

Sixth Embodiment FIG. 21 FIG. 21 is a circuit diagram showing an essential part of a sixth embodiment of the bus system according to the present invention. This sixth embodiment is one of the SDRAMs 48 to 51 shown in FIG. The output circuit and the like are configured as shown in FIG. 21, and the others are configured as shown in FIG.

In the figure, reference numeral 150 is an output circuit,
153 is a push-pull circuit that constitutes the output circuit 150. In this output circuit 150, the output resistance can be selected by selecting the push-pull circuit to be used.

In these push-pull circuits 151 to 153, 154 to 156 are pMOs forming pull-up elements.
S transistors 157 to 159 are nMOS transistors that form pull-down elements.

Here, for example, the pMOS transistor 154 has W (channel width = gate length) / L (channel length = gate width) = 400 μm / 1 μm, and the pMOS transistor 155 has W / L = 200 μm / 1 μm and pMO.
The S transistor 156 has W / L = 200 μm / 1 μm
It is said that.

In addition, for example, the nMOS transistor 1
57 is W / L = 200 μm / 1 μm, nMOS transistor 158 is W / L = 100 μm / 1 μm, n MO
The S transistor 159 has W / L = 100 μm / 1 μm
It is said that.

Further, 160 to 162 are push-pull control circuits for controlling the outputs of the push-pull circuits 151 to 153, respectively, and 165 to 168 are inverters and 1
69 and 170 are NAND circuits, and 171 and 172 are NOR circuits.
Circuits 173 and 174 are flag registers (F1, F
2).

Reference numeral 175 is an output data latch circuit for latching the output data DATA.
When TA = H level, output Q1 = H level, output Q2
= H level and output data DATA = L level, output Q1 = L level and output Q2 = L level.

When the value stored in the flag register 173 = H level, the output of the inverter 165 = L level, the output of the NAND circuit 169 = H level, and the pMOS
When the transistor 154 is turned off and the output of the NOR circuit 171 is at the L level, the nMOS transistor 15
7 = OFF, and the push-pull circuit 151 is deactivated.

On the other hand, when the value stored in the flag register 173 = L level, the output of the inverter 165 = H level, and the NAND circuit 169 outputs the output Q1 of the output data latch circuit 175 to the inverter Q1. NOR circuit 171 operates as the output data
The output Q2 of the latch circuit 175 operates as an inverter.

Therefore, when the output data DATA = H level, the output Q1 = H level and the output Q2 = H level, the output of the NAND circuit 169 = L level and the pMOS
When the transistor 154 is turned on and the output of the NOR circuit 171 is L level, the nMOS transistor 15
7 = OFF, and the output of the push-pull circuit 151 becomes H level.

On the other hand, when output data DATA = L level, output Q1 = L level, output Q2 = L level, output of NAND circuit 169 = H level, pMOS
The transistor 154 is turned off, the output of the NOR circuit 171 is set to the H level, and the nMOS transistor 15
7 = ON, and the output of the push-pull circuit 151 becomes L level.

The value stored in the flag register 174 =
In the case of H level, the output of the inverter 166 = L level,
When the output of the NAND circuit 170 = H level, the pMOS transistor 155 is turned off, and the NOR circuit 17
2 output = L level, nMOS transistor 158 =
The push-pull circuit 152 is turned off and the push-pull circuit 152 is deactivated.

On the other hand, when the value stored in the flag register 174 = L level, the output of the inverter 166 = H
Level, NAND circuit 170 is configured to operate as an inverter for the output Q1 of the output data latch circuit 175, NOR circuits 172 operates as an inverter for the output Q2 of the output data latch circuit 175
To be done.

Therefore, when output data DATA = H level, output Q1 = H level, output Q2 = H level, output of NAND circuit 170 = L level, pMOS
When the transistor 155 is turned on and the output of the NOR circuit 172 is L level, the nMOS transistor 15
8 = OFF, and the output of the push-pull circuit 152 becomes H level.

On the other hand, when output data DATA = L level, output Q1 = L level, output Q2 = L level, output of NAND circuit 170 = H level, pMOS
When the transistor 155 is turned off and the output of the NOR circuit 172 is H level, the nMOS transistor 15
8 = ON, and the output of the push-pull circuit 152 becomes L level.

The push-pull circuit 153 outputs the output of the inverter 167 when the output data DATA = H level, the output Q1 = H level, and the output Q2 = H level, regardless of the stored values of the flag registers 173 and 174. = L level, the pMOS transistor 156 is turned on, and the output of the inverter 168 = L level, the nMOS transistor 159 is turned off, and the push-pull circuit 15 is turned on.
3 output = H level.

On the other hand, when the output data DATA = L level, the output Q1 = L level and the output Q2 = L level, the output of the inverter 167 = H level, the pMOS transistor 156 = OFF, and the inverter 1
68 output = H level, nMOS transistor 159
= ON, and the output of the push-pull circuit 153 becomes L level.

Here, the flag registers 173, 174
Stored value, the states of the push-pull circuits 151 to 153, the combined value of W / L of the pMOS transistors used among the pMOS transistors 154 to 156, and nMO.
NM used among the S transistors 157 to 159
Table 2 shows the relationship with the combined value of W / L of the OS transistor.

[0236]

[Table 2]

Further, CKE, / CS, / RAS, / CA
S, / WE and CLK are signals supplied from the outside,
CKE is the clock enable signal, / CS is the chip
Select signal, / RAS is row address strobe signal, / CAS is column address strobe signal, / W
E is a write enable signal, and CLK is a clock signal.

176 to 179 take in the chip select signal / CS, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE using the clock enable signal CKE as a gate signal. Is a NAND circuit.

Reference numeral 180 is a decoder which fetches the outputs of the NAND circuits 176 to 179 in synchronization with the clock signal CLK, decodes them, and outputs a 16-bit decoded signal.

Here, the decoder 180 has a clock enable signal CKE = H level, a chip select signal / CS = L level, a row address strobe signal / RAS = L level, and a column address strobe signal / CAS =. L level, write enable signal / WE
== L level, the output of address 0 is set to H level.

Further, 181 is a shift register for shifting the clock signal CLK by one, and 182 is a decoder 180.
It is a NAND circuit to which the output of address 0 and the output of the shift register 181 are input.

Reference numeral 183 is a 12-bit mode register for taking in the addresses A _{0 to} A _11. The mode register 183 outputs the output of the NAND circuit 182 at the L level, that is, the output of address 0 of the decoder 180 = H. level,
When the output of the shift register 181 = H level, the address signals A _{0 to} A ₁₁ are taken in.

183 _{0 to} 183 ₁₁ are 1-bit register portions for taking in the address signals A _{0 to} A ₁₁ ,
MA _{0 to} MA ₈ are 1-bit register parts 183 ₀ to 18
This is the stored value of 3 ₈ .

Further, 184 and 185 are NOR circuits and 18
Reference numeral 6 is an encryption decoder, and 187 is a NAND circuit.

In this SDRAM, MA
₇ = H level, the case of MA ₈ = H level, the MA ₀ to MA ₆ user is to be able to use in association uniquely defined.

[0246] Therefore, in this sixth embodiment, the cipher decoder 186 for decoding the encrypted MA ₂ to MA ₆ provided encryption MA ₂ to MA ₆ cases only a special logic, the output H level of the cipher decoder 186 I am trying to become.

Further, MA ₇ , MA ₈ and cipher decoder 18
6 is input to the NAND circuit 187 and MA ₀ and the NOR circuit 18 to which the outputs of the NAND circuit 187 are input.
4 and the NOR circuit 185 to which MA ₁ and the output of the NAND circuit 187 are input.
4 is stored in the flag register 173, and the output of the NOR circuit 185 is stored in the flag register 174.

Here, the output of the NAND circuit 187 is M
A ₇ = H level, MA ₈ = H level, encryption decoder 186
Output = L level, therefore, when MA ₀ = L level, the output of the NOR circuit 184 = H level, the H level can be written in the flag register 173, and MA ₀ = H level. In this case, the NOR circuit 18
4 output = L level, and flag register 173 outputs L
You can write levels.

When MA ₁ = L level,
The output of the NOR circuit 185 can be set to the H level, and the H level can be written to the flag register 174. MA ₁ =
When the H level is set, the output of the NOR circuit 174 = L
It is possible to set the level and write the L level to the flag register 174.

According to the sixth embodiment, as in the case of the first embodiment, the input circuits 57 to 81 when the output states of the output circuits 77 to 81 are all in the high impedance state.
It is possible to prevent malfunction due to noise input to 61, reduce power consumption, and optimize the output waveform.

In addition, the CPU 47 and SDRAMs 48-5
Since the output resistance of the output circuit of 1 can be selected,
Regardless of whether the bus line 124 is terminated on one side, on both sides, or when the termination resistance is set to a value other than 50Ω, the amplitude of the signal on the bus line 124 is set to the specified amplitude. Therefore, good signal transmission can be performed.

First Application Example ... FIG. 22 FIG. 22 is a circuit diagram showing an example of an input circuit obtained by applying the input circuit shown in FIG. 17, and in the case of the GTL transmission system, the input circuit at the time of data transmission. 2 shows an input circuit capable of canceling differential noise input to.

In the figure, 190 is the power supply voltage VCC of 1.
VCC power supply line for supplying 2 [V], 191 is reference voltage V
It is an enhancement type pMOS transistor which forms a constant current source whose on / off is controlled by ref.

Reference numeral 192 denotes an enhancement type pMO forming a driving transistor to which the data signal D _IN is inputted.
The S-transistor 193 is an enhancement-type pMOS transistor which forms a drive transistor to which 0.8 [V] is input as the reference voltage Vref during data transmission.

Further, 194 and 195 are enhancement type nMOS transistors forming a current mirror circuit, and 196 is a noise canceling capacitor.

When a so-called differential noise having sharp rising and falling edges is input to the gate of the pMOS transistor 192, the differential noise is generated by the pMOS transistor 192.
Gate-source capacitance of transistor 192 and pMO
Through the source-gate capacitance of the S transistor 193, as shown by a broken line 197, the pMOS transistor 1
It may be transmitted to the gate of 93, that is, the reference voltage system.

According to the input circuit shown in FIG. 22, however, differential noise, which is the inverted differential noise input to the gate of the pMOS transistor 192, appears at the drain of the pMOS transistor 192.
As indicated by arrow 198, p
It can be transmitted to the gate of the MOS transistor 193.

As a result, differential noise transmitted to the gate of the pMOS transistor 193 via the capacitor 196 can cancel the noise mixed in the reference voltage system as shown by the broken line 197.

Second Application Example ... FIG. 23 FIG. 23 is a circuit diagram showing another example of an input circuit obtained by applying the input circuit shown in FIG. 17. In the case of the GTL transmission system, at the time of data transmission, 4 shows an input circuit that can cancel differential noise input to the input circuit.

In the input circuit shown in FIG. 23, the gate of the nMOS transistor 194 is connected to the pMOS transistor 19.
Instead of connecting to the drain of the nMOS transistor 195, the gate of the nMOS transistor 195 is connected to the drain of the pMOS transistor 193, and the output is connected to the pMOS transistor 193.
PMOS transistor, not from the drain of 193
It is obtained from the drain of 192 , and the other parts are configured similarly to the input circuit shown in FIG.

Also in the input circuit shown in FIG. 23, the noise mixed in the reference voltage system as indicated by the broken line 197 is canceled by the differential noise transmitted to the gate of the pMOS transistor 193 via the capacitor 196. You can

[0262]

According to the bus system of the present invention,
When all the output states of the output circuits (37, 38) whose output ends are connected to the common bus line (39) through the signal input / output terminals (31, 32) are set to the high impedance state, the reference voltage control circuit By (46), the reference voltage input terminal (3
5, 36), the reference voltage (Vref) supplied to the reference voltage (Vref) is controlled so as to have a voltage value different from that when the signal is transmitted via the bus line (39). An output circuit (37, whose end is connected to a common bus line (39) via signal input / output terminals (31, 32)
Even when all the output states of (38) are set to the high impedance state, the influence of noise input to the input circuit (33, 34) via the signal input / output terminals (31, 32) is eliminated and malfunction is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a bus system according to the present invention.

FIG. 2 is a circuit diagram showing an essential part of a first embodiment of a bus system according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of an input circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of an output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 5 is a waveform diagram for explaining the slew rate of the output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 6 is a circuit diagram for explaining a case where the output state of the output circuit provided in the first embodiment of the bus system according to the present invention is set to a high impedance state.

FIG. 7 is a circuit diagram for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the slow mode is selected.

FIG. 8 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the slow mode is selected.

FIG. 9 is a time chart for explaining the operation at the time of selecting the slow mode of the output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 10 is a circuit diagram for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the normal mode is selected.

FIG. 11 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the normal mode is selected.

FIG. 12 is a time chart for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the normal mode is selected.

FIG. 13 is a circuit diagram for explaining the operation of the output circuit provided in the first embodiment of the bus system according to the present invention when the fast mode is selected.

FIG. 14 is a time chart for explaining the operation when the fast mode is selected in the output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 15 is a time chart for explaining the operation at the time of selecting the first mode of the output circuit provided in the first embodiment of the bus system according to the present invention.

FIG. 16 is a circuit diagram showing an essential part of a second embodiment of the bus system according to the present invention.

FIG. 17 is a circuit diagram showing a main part (input circuit) of a third embodiment of the bus system according to the present invention.

FIG. 18 is a circuit diagram showing a main part (input circuit) of a fourth embodiment of the bus system according to the present invention.

FIG. 19 is a circuit diagram showing a main part (input circuit) of a fifth embodiment of the bus system according to the present invention.

FIG. 20 is a diagram showing a gain-bandwidth product of an input circuit.

FIG. 21 is a circuit diagram showing a main part (main part of SDRAM) of a sixth embodiment of the bus system according to the present invention.

22 is a circuit diagram showing an example of an input circuit obtained by applying the input circuit shown in FIG.

23 is a circuit diagram showing another example of an input circuit obtained by applying the input circuit shown in FIG.

FIG. 24 is a block diagram showing a main part of an example of a bus system.

FIG. 25 is a circuit diagram showing a T-LVTTL transmission system.

[Fig. 26] Fig. 26 is a diagram for describing a problem that the T-LVTTL transmission method has.

[Explanation of symbols]

29, 30 integrated circuit 31, 32 data input / output terminals 33, 34 Input circuit 35 and 36 are reference voltage input terminals. 37, 38 output circuit 39 bus line 40, 41 Terminator 42, 43 Termination voltage line 44 Reference voltage line 45 Reference voltage generation circuit 46 Reference voltage control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (4)

(57) [Claims] 1. A slew rate adjusting circuit, comprising: a main push-pull circuit; and a slew rate adjusting push-pull circuit having an output terminal connected to an output terminal of the main push-pull circuit, in response to a mode selection signal. Integrated circuit capable of selecting the slew rate of the output waveform at the output end by stepwise controlling the operation time of the push-pull circuit . 2. The mode selection signal is a slow mode,
Either normal mode or fast mode
2. The integrated circuit according to claim 1, characterized in that
Road . 3. A push-pull circuit used non-selectively.
And an output terminal of the push-pull circuit which is used non-selectively.
Multiple push-pull circuits connected to each output
And external information consisting of multiple bits in response to an external command
Mode register consisting of multiple 1-bit registers that hold
And some of the external information stored in this mode register.
Output enable signal only when bits are in specific combination
And the mode register which is used when the enable signal is output.
Value in response to the remaining bits of the external information held by
Is set and the push-pull to use based on that value
An integrated circuit having a flag register for selecting the number of circuits. 4. A circuit comprising the plurality of push-pull circuits.
Contractors characterized by different sizes of transistors
The integrated circuit according to claim 3.