KR20040093804A - Initializing signal generator in semiconductor memory device - Google Patents

Abstract

PURPOSE: A circuit for generating an initialization signal of a semiconductor memory device is provided to perform initialization under an initial state when a command is not applied. CONSTITUTION: An inverter(20) receives a power up signal(pwrup), and an inverter(21) receives a register setting command signal(rstcmd). A NAND gate(22) receives outputs of the two inverters(20,21). An inverter(23) receives an initialization section setting signal(ckelow). An inverter(24) receives an output of the inverter(23). An NOR gate(25) receives an output of the NAND gate(22) and an output of the inverter(24). And an inverter(26) outputs an initialization signal(rstreg) by receiving an output of the NOR gate(25).

Description

Initialization signal generation circuit for semiconductor memory devices {INITIALIZING SIGNAL GENERATOR IN SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit technology, and more particularly, to an initialization signal generating circuit of a semiconductor memory device.

The semiconductor memory device has an initialization section for a predetermined time after an external power source is applied. During this initialization period, the internal power supply and the clock are stabilized and the node of the register or latch inside the device is initialized to a certain level.

The semiconductor memory device generates an initialization signal necessary inside the device in a standardized initialization process, and a circuit necessary for this is called an initialization signal generation circuit.

1 is a configuration diagram of an initialization signal generation circuit of a semiconductor memory device according to the prior art.

Referring to FIG. 1, an initialization signal generation circuit of a semiconductor memory device according to the related art includes an inverter 10 which inputs a power-up signal pwrup and an inverter 11 which inputs a register setting command signal rstcmd. ), A NAND gate 12 that takes in the outputs of the two inverters 10 and 11, an inverter 13 that takes in the output of the NAND gate 12, and an output of the inverter 13 as an input. An inverter 14 for outputting an initialization signal rstreg is provided.

The illustrated initialization signal generating circuit exemplifies a case in which the power-up signal pwrup, the register setting command signal rstcmd, and the initialization signal rstreg are all high active signals, and in some cases, a logic gate may be implemented differently.

FIG. 2 is a timing diagram of the initialization signal generation circuit of FIG. 1. Hereinafter, a normalized initialization process will be described with reference to the timing diagram.

Referring to FIG. 2, in the standardized initialization process, first, the power-up signal pwrup is activated to a high level when the external power supply Vext is powered up from a low level to a high level voltage. When the power-up signal pwrup is activated, the initialization signal generation circuit of FIG. 1 activates the initialization signal rstreg to a high level by an active period of the power-up signal pwrup.

On the other hand, after the clock CLK and the clock enable signal CKE are applied and the register setting command RSET is applied to activate the register setting command signal rstcmd to a high level, the initialization signal rstreg is activated again. Initialize the registers in the device.

As such, the initialization signal rstreg is enabled at power-up and at register setting to initialize a node of a latch or register in the semiconductor memory device. That is, initialization must be performed even in a DC condition (a state in which only an external power source is applied) in which the clock CLK and the command CMD are not input.

However, in some cases, the power-up signal pwrup is not activated depending on the speed at which the external power supply Vext transitions from low to high level or process conditions. In this case, when the nodes of the internal register or the latch are set to an arbitrary level and the register setting command signal rstcmd is applied, the nodes are set to the initialization level and may cause unwanted noise. Such noise is a factor that causes the circuit to malfunction, especially in a circuit using a specific command mode that controls the internal power generator due to the analysis and test needs.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide an initialization signal generation circuit of a semiconductor memory device capable of stably performing initialization in an initial state where a command is not applied.

1 is a block diagram of an initialization signal generation circuit of a semiconductor memory device according to the prior art.

2 is a timing diagram of the initialization signal generation circuit of FIG.

3 is a configuration diagram of an initialization signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a timing diagram of the initialization signal generation circuit of FIG.

* Explanation of symbols for the main parts of the drawings

pwrup: power up signal

ckelow: Initialization section setting signal

rstcmd: register setting command signal

According to an aspect of the present invention for achieving the above technical problem, the initialization section for setting the power-up signal for notifying the application of the external power source, the interval in which the clock enable signal is activated from the clock stabilized state after power-up An initialization signal generation circuit of a semiconductor memory element for activating an initialization signal in response to a register setting command signal indicating the application of a signal and a register setting command is provided.

Further, according to another aspect of the invention, the first logical combination means for inputting the power-up signal for notifying the application of the external power supply and the register setting command signal for notifying the application of the register setting command, and the clock after the power-up is stabilized There is provided an initialization signal generation circuit for a semiconductor memory device comprising an initialization section setting signal for setting a section in which a clock enable signal is activated from the second section and a second logic combining section for inputting an output of the first logical combining section.

Advantageously, said first logic combining means comprises a NAND gate that accepts the inverted power-up signal and the inverted register setting command signal as inputs.

Preferably, the second logic combining means includes a NOR gate for inputting the output of the NAND gate and the initialization period setting signal.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

3 is a configuration diagram of an initialization signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the initialization signal generation circuit of the semiconductor memory device according to the present embodiment includes an inverter 20 for inputting a power-up signal pwrup and an inverter for inputting a register setting command signal rstcmd. 21, a NAND gate 22 which inputs the outputs of the two inverters 20 and 21, an inverter 23 which inputs an initialization section setting signal ckelow, and an output of the inverter 23 as inputs. Outputting an initialization signal rstreg by inputting the output of the inverter 24, the NAND gate 22 and the output of the inverter 24 and the output of the inverter 24 An inverter 26 is provided.

Here, the initialization section setting signal ckelow is a signal that maintains a high level during the deactivation section (low level section) of the clock enable signal CKE in a state where the clock is stabilized after the power-up of the external power supply.

That is, the present invention further provides the initialization using the initialization interval setting signal ckelow in addition to the initialization using the existing power-up signal pwrup in the initial state where the command CMD is not applied.

FIG. 4 is a timing diagram of the initialization signal generation circuit of FIG. 3. Hereinafter, an initialization process according to the present embodiment will be described with reference to the following.

Referring to FIG. 4, the initialization process according to the present embodiment first activates the power-up signal pwrup to a high level when the external power supply Vext is powered up from a low level to a high level voltage. . When the power-up signal pwrup is activated, the initialization signal generation circuit of FIG. 3 activates the initialization signal rstreg to a high level by the active period of the power-up signal pwrup.

Referring to FIG. 3, since the register setting command signal rstcmd and the initialization section setting signal ckelow are in the low level in the section where the power-up signal pwrup is at the high level, the NOR gate 25 operates like the inverter. , The initialization signal rstreg is at a high level.

On the other hand, after performing the initialization operation using the power-up signal pwrup as described above, the clock enable signal CKE is deactivated to a low level for a predetermined time (about 200 ms) even after the clock CLK is stabilized. Keep it. In this period, the semiconductor memory device does not operate substantially, and in this embodiment, when the clock enable signal CKE transitions to the high level from the first rising edge of the clock CLK after the clock CLK is stabilized. The initialization operation is performed once again by using an initialization section setting signal ckelow activated to a high level.

The initialization section setting signal ckelow is generated in synchronization with the clock CLK and detects the transition of the clock enable signal CKE. Since a variety of methods are known for generating such a signal, Description of circuits will be omitted.

Referring back to FIG. 3, since the register setting command signal rstcmd and the power-up signal pwrup are at a low level in the initialization section setting signal ckelow at a high level, the NOA gate 25 operates as an inverter to make a high level. The initialization signal rstreg of the level state is output.

Subsequently, when the register setting command RSET is applied while the clock enable signal CKE maintains the high level and the register setting command signal rstcmd is activated to the high level, the initialization signal rstreg is activated again. Initialize the registers in the table.

Referring back to FIG. 3, since the power-up signal pwrup and the initialization section setting signal ckelow are in the low level in the section in which the register setting command signal rstcmd is in the high level, the NOR gate 25 operates as an inverter to make a high level. The initialization signal rstreg of the level state is output.

As described above, according to the present invention, the initialization by the power-up signal pwrup, the initialization by the initialization section setting signal ckelow, and the initialization by the register setting command signal rstcmd are performed. Initialization is done for the nodes.

Therefore, even when initialization is not performed properly in the power-up operation due to the speed or process conditions at which the external power supply Vext transitions from low to high level, the initialization section setting signal ( Initialization can be performed by a ckelow to suppress the occurrence of unwanted noise upon subsequent application of the register setting command RSET.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the power-up signal pwrup, the initialization section setting signal ckelow, the register setting command signal rstcmd, and the initialization signal rstreg are all high active signals. Therefore, logic gates can be implemented differently.

The present invention described above has the effect of preventing the occurrence of unnecessary noise during the initialization operation, thereby lowering the failure rate of the semiconductor device.

Claims (4)

In response to a power-up signal informing that an external power supply is applied, an initialization section setting signal for setting a section in which a clock enable signal is activated after the clock is stabilized after power-up, and a register setting command signal indicative of application of a register setting command An initialization signal generation circuit of a semiconductor memory device that activates an initialization signal. First logic combining means for inputting a power-up signal for notifying application of an external power supply and a register-setting command signal for notifying the application of a register setting command; Second logic combining means for inputting an initialization interval setting signal for setting a period in which the clock enable signal is activated from a state where the clock is stabilized after power-up and the output of the first logic combining means. Initialization signal generation circuit of a semiconductor memory device having a The method of claim 2, And said first logic combining means comprises a NAND gate for inputting the inverted power-up signal and the inverted register setting command signal. The method of claim 3, And the second logic combining means comprises a noah gate for inputting the output of the NAND gate and the initialization period setting signal.