KR100854461B1 - Power-up signal controlling circuit - Google Patents

Power-up signal controlling circuit Download PDF

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KR100854461B1
KR100854461B1 KR1020070026583A KR20070026583A KR100854461B1 KR 100854461 B1 KR100854461 B1 KR 100854461B1 KR 1020070026583 A KR1020070026583 A KR 1020070026583A KR 20070026583 A KR20070026583 A KR 20070026583A KR 100854461 B1 KR100854461 B1 KR 100854461B1
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signal
power
block
counting
test mode
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Korean (ko)
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홍윤석
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor

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  • Semiconductor Integrated Circuits (AREA)

Abstract

A power-up signal controlling circuit is provided to find initial operation error, by performing initialization by a power-up signal by applying the power-up signal counted according to a test signal to each classified block. A power-up signal controlling circuit generates a block power-up signal to initialize blocks sequentially by receiving a power-up signal and a counting signal counted according to a test mode signal. The power-up signal controlling circuit includes a counter(10) and a block control part(11,12,13,14). The counter generates a counting signal according to the test mode signal. The block control part generates a block power-up signal by receiving the counting signal and the power-up signal. The counter generates a first and a second counting signal enabled sequentially by performing counting according to the test mode signal.

Description

파워업신호 제어회로{Power-up Signal Controlling Circuit}Power-up Signal Controlling Circuit

도 1은 본 발명에 의한 일실시에에 따른 파워업신호 제어회로의 구성을 도시한 것이다.1 is a block diagram of a power-up signal control circuit according to an embodiment of the present invention.

도 2는 도 1에 포함된 파워업 신호 제어부의 구성을 도시한 것이다.FIG. 2 illustrates a configuration of a power up signal controller included in FIG. 1.

본 발명은 파워업신호 제어회로에 관한 것으로, 더욱 구체적으로는 반도체 장치 내부를 다수개의 블럭으로 구분하고, 테스트 신호에 따라 카운팅된 파워업 신호를 상기 구분된 블럭별로 순차적으로 인가하여 파워업 신호에 의한 초기화를 진행함으로써, 초기화 동작 오류가 발생된 부분을 용이하게 찾을 수 있도록 하는 파워업신호 제어회로에 관한 것이다.The present invention relates to a power-up signal control circuit. More specifically, the inside of a semiconductor device is divided into a plurality of blocks, and a power-up signal counted according to a test signal is sequentially applied to each of the divided blocks to a power-up signal. The present invention relates to a power-up signal control circuit that makes it easy to find a portion where an initialization operation error occurs.

일반적으로, 반도체 장치에서 파워업 신호 생성회로는 반도체 장치의 초기화를 담당하는 회로를 의미한다. 한편, 반도체 장치를 동작시키기 위해서는 외부에서 외부전압(VDD)을 공급받는데, 외부전압(VDD)의 전압레벨은 0[V]로부터 시작하여 일정한 기울기를 가지고 목적 전압 레벨까지 상승하게 된다. 이때, 반도체 장치의 모든 회로는 이러한 외부전압(VDD)을 직접 인가받으면, 상승하는 외부전압에 영향을 받아 오동작을 일으키게 된다. 따라서, 이러한 칩의 오동작을 막기 위하여, 반도체 장치는 파워업 신호 생성회로를 구비하여 파워업 신호(Power-up signal)를 인에이블시킴으로써, 외부전압(VDD)이 안정적인 전압레벨이 된 이후에 각 회로에 공급되도록 하고 있다. 이와 같은 동작을 파워업에 의해 반도체 장치는 초기화된다.In general, the power-up signal generation circuit in the semiconductor device refers to a circuit that is responsible for initialization of the semiconductor device. In order to operate the semiconductor device, an external voltage VDD is externally supplied. The voltage level of the external voltage VDD starts from 0 [V] and rises to a target voltage level with a constant slope. At this time, when all the circuits of the semiconductor device are directly applied with the external voltage VDD, a malfunction occurs due to the influence of the rising external voltage. Therefore, in order to prevent such chip malfunction, the semiconductor device includes a power-up signal generating circuit to enable a power-up signal so that each circuit after the external voltage VDD reaches a stable voltage level. To be supplied. The semiconductor device is initialized by powering up such an operation.

그런데, 종래의 파워업 신호 생성회로에서 생성된 파워업 신호는 반도체 장치 전체에 일괄적으로 인가되기 때문에, 반도체 장치의 초기화 작업 동작오류(fail)가 발생되어도 반도체 장치 내부의 어느 부분에서 그 동작오류 발생 되었는지 쉽게 찾을 수 없는 문제가 있었다.However, since the power-up signal generated by the conventional power-up signal generation circuit is applied to the entire semiconductor device as a whole, even if an initialization operation error of the semiconductor device occurs, the operation error in any part of the semiconductor device occurs. There was a problem that I could not easily find out if it was occurring.

따라서, 본 발명이 이루고자 하는 기술적 과제는 반도체 장치 내부를 다수개의 블럭으로 구분하고, 테스트 신호에 따라 카운팅된 파워업 신호를 상기 구분된 블럭별로 순차적으로 인가하여 파워업 신호에 의한 초기화를 진행함으로써, 초기화 동작 오류가 발생된 부분을 용이하게 찾을 수 있도록 하는 파워업신호 제어회로를 제공하는 데 있다.Therefore, the technical problem to be achieved by the present invention is to divide the inside of the semiconductor device into a plurality of blocks, by sequentially applying a power-up signal counted according to the test signal for each of the divided blocks to proceed with the initialization by the power-up signal, An object of the present invention is to provide a power-up signal control circuit for easily finding a portion where an initialization operation error has occurred.

상기 기술적 과제를 달성하기 위하여, 본 발명은 테스트모드 신호에 따라 카운팅된 카운팅 신호와 파워업신호를 입력받아 블럭들을 순차적으로 초기화하기 위한 블럭 파워업신호를 생성하는 파워업신호 제어회로를 제공한다.In order to achieve the above technical problem, the present invention provides a power-up signal control circuit for generating a block power-up signal for sequentially initializing blocks by receiving a counting signal and a power-up signal counted according to a test mode signal.

또한, 본 발명은 테스트모드 신호에 따라 카운팅 신호를 생성하는 카운터; 및 상기 카운팅 신호와 파워업신호를 입력받아, 블럭 파워업신호를 생성하는 블럭제어부를 포함하는 파워업신호 제어회로를 제공한다.The present invention also provides a counter for generating a counting signal according to a test mode signal; And a block controller configured to receive the counting signal and the power up signal and generate a block power up signal.

본 발명에서, 상기 카운터는 상기 테스트모드 신호에 따라 카운팅하여 순차적으로 인에이블되는 제1 및 제2 카운팅 신호를 생성하는 것이 바람직하다.In the present invention, the counter may count based on the test mode signal to generate first and second counting signals that are sequentially enabled.

본 발명에서, 상기 블럭제어부는 상기 제1 카운팅 신호와 상기 파워업신호를 입력받아 제1 블럭을 초기화하기 위한 제1 블럭 파워업신호를 생성하는 제1 블럭제어부; 및 상기 제2 카운팅 신호와 상기 파워업신호를 입력받아 제2 블럭을 초기화하기 위한 제2 블럭 파워업신호를 생성하는 제2 블럭제어부를 포함한다.The block controller may include: a first block controller configured to receive the first counting signal and the power up signal and generate a first block power up signal for initializing a first block; And a second block controller configured to receive the second counting signal and the power up signal and generate a second block power up signal for initializing a second block.

본 발명에서, 상기 제1 블럭제어부는 상기 제1 카운팅 신호와 상기 파워업신호를 입력받아 논리합 연산을 수행하는 것이 바람직하다.In the present invention, it is preferable that the first block controller receives the first counting signal and the power-up signal to perform a logical sum operation.

본 발명에서, 상기 제2 블럭제어부는 상기 제2 카운팅 신호와 상기 파워업신호를 입력받아 논리합 연산을 수행하는 것이 바람직하다.In the present invention, it is preferable that the second block controller receives the second counting signal and the power-up signal to perform a logical sum operation.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

도 1은 본 발명에 의한 일실시에에 따른 파워업신호 제어회로의 구성을 도시한 것이고, 도 2는 도 1에 포함된 파워업 신호 제어부의 구성을 도시한 것이다.1 illustrates a configuration of a power up signal control circuit according to an embodiment of the present invention, and FIG. 2 illustrates a configuration of a power up signal controller included in FIG. 1.

도 1에 도시된 바와 같이, 본 발명에 의한 일실시에에 따른 파워업신호 제어회로는 테스트모드 신호(Power-up Tm signal)를 입력받아 카운팅 동작을 통해 순차적으로 인에이블되는 제1 내지 제4 카운팅 신호(1st, 2nd, 3rd, 4th counting signal)를 생성하는 카운터(10)와, 파워업 신호(Power-up signal)와 제1 카운팅 신호(1st counting signal)를 입력받아 로우 어드레스 퓨즈부(15)를 초기화하기 위한 제1 블럭 파워업신호(1st Block Power-up signal)를 생성하는 제1 블럭제어부(11)와, 파워업 신호(Power-up signal)와 제2 카운팅 신호(2nd counting signal)를 입력받아 컬럼 어드레스 퓨즈부(16)를 초기화하기 위한 제2 블럭 파워업신호(2nd Block Power-up signal)를 생성하는 제2 블럭제어부(12)와, 파워업 신호(Power-up signal)와 제3 카운팅 신호(3rd counting signal)를 입력받아 제1 페리 영역(PERI Left)을 초기화하기 위한 제3 블럭 파워업신호(3rd Block Power-up signal)를 생성하는 제3 블럭제어부(13)와, 파워업 신호(Power-up signal)와 제4 카운팅 신호(4th counting signal)를 입력받아 제2 페리 영역(PERI Right)을 초기화하기 위한 제4 블럭 파워업신호(4th Block Power-up signal)를 생성하는 제4 블럭제어부(14)를 포함한다.As shown in FIG. 1, the power-up signal control circuit according to an embodiment of the present invention receives a test mode signal (Power-up Tm signal) and is sequentially enabled through a counting operation. The row address fuse unit 15 receives a counter 10 that generates counting signals 1st, 2nd, 3rd, and 4th counting signals, a power-up signal, and a first counting signal. A first block controller 11 for generating a first block power-up signal for initializing the first block power-up signal, a power-up signal, and a second counting signal. A second block control unit 12 for generating a second block power-up signal for initializing the column address fuse unit 16, a power-up signal, A 3rd counting signal is input to initialize the first ferry area PERI Left. A second ferry receiving the third block controller 13 for generating a third block power-up signal, a power-up signal, and a fourth counting signal; And a fourth block controller 14 for generating a fourth block power-up signal for initializing the region PERI Right.

도2를 참고하면, 제1 내지 제4 블럭제어부(11-14)는 파워업 신호(Power-up signal)와 카운팅 신호(counting signal)를 입력받아 논리합 연산을 수행하여 블럭 파워업신호(Block Power-up signal)를 생성하는 노어게이트(NR20) 및 인버터(IV20)로 구성된다.Referring to FIG. 2, the first to fourth block controllers 11-14 receive a power-up signal and a counting signal and perform a logical sum operation to perform a block power-up signal. It consists of a NOR gate NR20 and an inverter IV20 generating a -up signal.

이와 같이 구성된 파워업신호 제어회로의 동작을 도1 및 도2를 참고하여 구체적으로 설명하면 다음과 같다.The operation of the power-up signal control circuit configured as described above will be described in detail with reference to FIGS. 1 and 2.

우선, 카운터(10)는 일반적인 카운터 회로로 구성되어, 테스트모드 신호(Power-up Tm signal)에 따라 카운팅 동작을 수행하여 제1 내지 제4 카운팅 신호(1st, 2nd, 3rd, 4th counting signal)를 생성한다. 예를 들어, 테스트모드 신호(Power-up Tm signal)가 입력되면 '0000', '0001', '0010'...'1110', '1111'과 같이 순차적으로 카운팅된 제1 내지 제4 카운팅 신호(1st, 2nd, 3rd, 4th counting signal)가 생성된다. 이때, '0001'의 경우 제1 카운팅 신호(1st counting signal)만이 하이레벨로 인에이블된 경우로, '0010'인 경우 제2 카운팅 신호(2nd counting signal)만 인에이블된 경우로 보아 본 실시예의 동작을 설명한다.First, the counter 10 includes a general counter circuit, and counts the first to fourth counting signals 1st, 2nd, 3rd, and 4th counting signals by performing a counting operation according to a test mode signal (Power-up Tm signal). Create For example, when a test mode signal (Power-up Tm signal) is input, the first to fourth counting sequentially counted as '0000', '0001', '0010' ... '1110', and '1111'. Signals 1st, 2nd, 3rd, and 4th counting signals are generated. In this case, in the case of '0001', only the first counting signal (1st counting signal) is enabled at a high level. In the case of '0010', only the second counting signal (2nd counting signal) is enabled. Describe the operation.

다음으로, 제1 내지 제4 블럭제어부(11-14)는 제1 내지 제4 카운팅 신호(1st, 2nd, 3rd, 4th counting signal)를 입력받아, 제1 내지 제4 블럭 파워업신호(1st, 2nd, 3rd, 4th Power-up signal)를 생성한다. 좀 더 구체적으로 제2 카운팅 신호(2nd counting signal)가 하이레벨로 인에이블된 경우를 예를 들어 살펴본다. 이때, 제1, 제3, 제4 카운팅 신호(1st, 3rd, 4th counting signal)는 로우레벨로 디스에이블된 상태이다. 제2 블럭제어부(12)는 하이레벨로 인에이블된 제2 카운팅 신호(2nd counting signal)를 입력받아, 인에이블된 제2 블럭파워업 신호(2nd Block Power-up signal)를 생성하여 출력하여 컬럼 어드레스 퓨즈부(16)에 대한 초기화를 진행시킨다. 즉, 제2 블럭제어부(12)에 입력되는 파워업 신호(Power-up signal)가 외부전압(VDD)의 안정화에 따라 하이레벨로 천이하면 파워업 신호(Power-up signal)와 제2 카운팅 신호(2nd counting signal)와의 논리합 연산에 의해 하이레벨로 인에이블되는 제2 블럭파워업 신호(2nd Block Power-up signal)가 생성된다. 제2 블럭파워업 신호(2nd Block Power-up signal)가 하이레벨로 인에이블되면 외부전압(VDD)이 컬럼 어드레스 퓨즈부(16)에 공급된다. 이때, 컬럼 어드레스 퓨즈부(16)에 입력되는 외부전압(VDD)이 안정적인 레벨에 이르지 못한 경우 동작 오류가 발생할 것이고, 이와 같은 오류가 확인된 경우 컬럼 어드레스 퓨즈부(16)의 초기화 동작에 오류가 발생되었음을 확인할 수 있게 된다.Next, the first to fourth block controllers 11-14 receive the first to fourth counting signals 1st, 2nd, 3rd, and 4th counting signals, and the first to fourth block power-up signals 1st, 2nd, 3rd, 4th Power-up Signal). More specifically, a case in which the second counting signal is enabled to a high level will be described as an example. In this case, the first, third, and fourth counting signals 1st, 3rd, and 4th counting signals are disabled at a low level. The second block control unit 12 receives a second counting signal (2nd counting signal) enabled at a high level, generates and outputs a second block power-up signal (2nd Block Power-up signal) enabled by the column. Initialization of the address fuse unit 16 is performed. That is, when the power-up signal input to the second block controller 12 transitions to the high level according to the stabilization of the external voltage VDD, the power-up signal and the second counting signal A second block power-up signal (2nd Block Power-up signal) that is enabled to a high level is generated by the OR operation with (2nd counting signal). When the second block power-up signal is enabled at a high level, the external voltage VDD is supplied to the column address fuse unit 16. At this time, when the external voltage VDD input to the column address fuse unit 16 does not reach a stable level, an operation error will occur. It can be confirmed that it occurred.

이와 같은 오류 확인 작업은 카운터(10)의 카운팅 동작에 의해 생성된 제1 내지 제4 카운팅 신호(1st, 2nd, 3rd, 4th counting signal)에 의해 제1 내지 제4 블럭 파워업신호(1st, 2nd, 3rd, 4th Power-up signal)를 순차적으로 인에이블 시키고, 이와 같이 블럭별로 구분된 제1 내지 제4 블럭 파워업신호(1st, 2nd, 3rd, 4th Power-up signal)에 의해 각각의 블럭(15-18)들을 순차적으로 초기화시키는 방식으로 진행된다. 따라서, 본 실시예에 의하면 블럭(15-18) 별로 구분하여 초기화를 진행시킬 수 있으므로 오류가 발생된 블럭을 용이하게 확인할 수 있다. The error checking operation is performed by the first to fourth counting signals 1st, 2nd, 3rd, and 4th counting signals generated by the counting operation of the counter 10, and the first to fourth block power up signals 1st and 2nd. , 3rd, 4th Power-up signal) are sequentially enabled, and each block (1st, 2nd, 3rd, 4th Power-up signal) divided by blocks in this way 15-18) are sequentially initialized. Therefore, according to the present exemplary embodiment, since the initialization may be performed according to the blocks 15-18, the block in which the error has occurred can be easily identified.

상기 실시예에서는 4개의 블럭으로 구분하고, 4개의 카운팅신호에 의해 순차적으로 인에이블되는 블럭 파워업신호에 의해 4개의 블럭을 순차적으로 초기화시키는 것을 예를 들어 설명했다. 본 발명은 상기 실시예에 한정되지 않고, 보다 세분 화되어 구분된 블럭에 대해 순차적으로 초기화를 진행해 초기화 동작시 발생되는 동작오류를 확인하는 경우까지 적용될 수 있다. In the above embodiment, the four blocks are divided and the four blocks are sequentially initialized by the block power-up signal which is sequentially enabled by the four counting signals. The present invention is not limited to the above embodiment, and may be applied until the operation error generated during the initialization operation is confirmed by sequentially performing the initialization on the more divided and divided blocks.

이상 설명한 바와 같이, 본 발명에 따른 파워업신호 제어회로는 반도체 장치 내부를 다수개의 블럭으로 구분하고, 테스트 신호에 따라 카운팅된 파워업 신호를 상기 구분된 블럭별로 순차적으로 인가하여 파워업 신호에 의한 초기화를 진행함으로써, 초기화 동작 오류가 발생된 부분을 용이하게 찾을 수 있는 효과가 있다.As described above, the power-up signal control circuit according to the present invention divides the inside of the semiconductor device into a plurality of blocks, and sequentially applies the power-up signal counted according to the test signal for each of the divided blocks to generate the power-up signal. By proceeding with the initialization, there is an effect that it is easy to find the portion where the initialization operation error occurred.

Claims (6)

테스트모드 신호에 따라 카운팅된 카운팅 신호와 파워업신호를 입력받아 블럭들을 순차적으로 초기화하기 위한 블럭 파워업신호를 생성하는 파워업신호 제어회로.A power up signal control circuit for receiving a counting signal and a power up signal counted according to the test mode signal and generating a block power up signal for sequentially initializing the blocks. 테스트모드 신호에 따라 카운팅 신호를 생성하는 카운터; 및A counter for generating a counting signal according to the test mode signal; And 상기 카운팅 신호와 파워업신호를 입력받아, 블럭 파워업신호를 생성하는 블럭제어부를 포함하는 파워업신호 제어회로.And a block controller configured to receive the counting signal and the power up signal and generate a block power up signal. 제 2 항에 있어서, 상기 카운터는 상기 테스트모드 신호에 따라 카운팅하여 순차적으로 인에이블되는 제1 및 제2 카운팅 신호를 생성하는 파워업신호 제어회로.The power up signal control circuit of claim 2, wherein the counter generates a first counting signal and a second counting signal which are sequentially enabled according to the test mode signal. 제 3 항에 있어서, 상기 블럭제어부는The method of claim 3, wherein the block control unit 상기 제1 카운팅 신호와 상기 파워업신호를 입력받아 제1 블럭을 초기화하기 위한 제1 블럭 파워업신호를 생성하는 제1 블럭제어부; 및A first block control unit receiving the first counting signal and the power up signal and generating a first block power up signal for initializing a first block; And 상기 제2 카운팅 신호와 상기 파워업신호를 입력받아 제2 블럭을 초기화하기 위한 제2 블럭 파워업신호를 생성하는 제2 블럭제어부를 포함하는 파워업신호 제어회로.And a second block controller configured to receive the second counting signal and the power up signal and generate a second block power up signal for initializing a second block. 제 4 항에 있어서, 상기 제1 블럭제어부는 상기 제1 카운팅 신호와 상기 파워업신호를 입력받아 논리합 연산을 수행하는 파워업신호 제어회로.The power up signal control circuit of claim 4, wherein the first block control unit receives the first counting signal and the power up signal and performs a logical sum operation. 제 4 항에 있어서, 상기 제2 블럭제어부는 상기 제2 카운팅 신호와 상기 파워업신호를 입력받아 논리합 연산을 수행하는 파워업신호 제어회로.The power up signal control circuit of claim 4, wherein the second block control unit receives the second counting signal and the power up signal and performs a logical sum operation.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040093804A (en) * 2003-04-30 2004-11-09 주식회사 하이닉스반도체 Initializing signal generator in semiconductor memory device
KR20040110317A (en) * 2003-06-18 2004-12-31 주식회사 하이닉스반도체 Circuit and method of generating power-up signal in a semiconductor device and method of testing the same
KR20060117469A (en) * 2005-05-11 2006-11-17 주식회사 하이닉스반도체 Method for testing a memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040093804A (en) * 2003-04-30 2004-11-09 주식회사 하이닉스반도체 Initializing signal generator in semiconductor memory device
KR20040110317A (en) * 2003-06-18 2004-12-31 주식회사 하이닉스반도체 Circuit and method of generating power-up signal in a semiconductor device and method of testing the same
KR20060117469A (en) * 2005-05-11 2006-11-17 주식회사 하이닉스반도체 Method for testing a memory device

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