KR20040093556A - Method for forming storage node contact of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a storage node contact is provided to improve SAC(Self-Aligned Contact) margin by forming the storage node contact with hole type instead of line type. CONSTITUTION: A first interlayer dielectric(2) having a poly plug is formed on a substrate(1). A conductive layer(4) and a nitride layer(5) as a hard mask are sequentially deposited on the first interlayer dielectric. By patterning the nitride layer and the conductive layer, bit lines(6) are formed. A second interlayer dielectric(7) and an anti-reflective coating are formed on the resultant structure. Contact holes(10) are formed to expose the poly plug. The remaining anti-reflective coating is removed. A spacer(11) is formed at both sidewalls of the contact holes. A storage node contact(12) of hole type is then formed by filling a polysilicon layer in the contact hole and by etch-back of the polysilicon layer.

Description

Method for forming storage node contact of semiconductor device

The present invention relates to a method of forming a storage node contact of a semiconductor device, and more particularly, to a method of forming a storage node contact in a hole type.

As the integration of semiconductor devices progresses, there is a difficulty in the electrical connection between the upper and lower patterns. Therefore, in the fabrication of a 0.20 占 퐉 semiconductor device, a storage node contact forming process for connecting a storage node to a lower portion has a low overlay margin of a mask operation, and thus self alignment using an etching selectivity between oxide and nitride layers. Self Aligned Contact process is applied.

In the case of having a line width of 0.14 μm or more, a self-aligned contact of a hole pattern is applied. However, in the development of a device having a line width of less than that, a mask alignment margin is insufficient to introduce a self-aligned contact technology of a line pattern.

Here, the hole type and line type storage node contact forming processes will be briefly described as follows.

First, the former process forms a contact hole exposing a lower pattern, that is, a poly plug, between the bit lines through the etching of the interlayer insulating film subsequently with bit lines having a nitride spacer and a hard mask nitride film formed thereon. Next, a conductive film, preferably a polysilicon film, is embedded in the contact hole to form a hole type storage node contact.

The latter process then forms a groove between the bit lines through the etching of the interlayer insulating film subsequently with the formation of the bit lines with only the hard mask nitride film without the formation of sidewall spacers, and then of the grooves. After forming nitride film spacers on both side walls, a conductive film is embedded in the groove to form a line type storage node contact.

However, the hole type storage node contact forming process is difficult to apply to the development of a device having a line width of 0.14 μm or less due to lack of mask alignment margin as described above. Although this has been proposed, such a line type storage node contact forming process has a problem in that a self-aligned contact defect occurs between the storage node and the bit line due to a lack of process margin.

In detail, the line-type storage node contact forming process needs to form a thick nitride spacer to protect the bit line after the formation of the groove, so that the opening defect of the nitride spacer is likely to appear due to the gap between the very narrow bit lines, and also the contact bottom. As the area is small, the resistance problem becomes serious, and as the gap between the bit lines is narrow, difficulty in filling a gap during deposition of a subsequent insulating film is caused.

Therefore, the process of forming the line pattern storage node contact may reduce the reliability of the device as well as the reliability of the device because the process margin is insufficient, and may also cause a decrease in manufacturing yield.

Accordingly, an object of the present invention is to provide a method for forming a storage node contact of a semiconductor device capable of preventing defects caused by lack of process margins.

Another object of the present invention is to provide a method of forming a storage node contact of a semiconductor device capable of simplifying a process while securing a self-aligned contact margin.

1A through 1E are cross-sectional views illustrating processes for forming a hole type storage node contact method according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 First interlayer insulation film

3: titanium nitride film 4: tungsten film

5: nitride film for hard mask 6: bit line

7 second interlayer insulating film 8 antireflection film

9: photosensitive film pattern 10: contact hole

11 nitride film spacer 12 storage node contact

In order to achieve the above object, the present invention comprises the steps of providing a semiconductor substrate having a first interlayer insulating film having a poly plug; Sequentially depositing a conductive film and a hard mask nitride film on the first interlayer insulating film; Patterning the hard mask nitride layer and the conductive layer to form bit lines; Sequentially depositing a second interlayer insulating film and an antireflection film on the first interlayer insulating film so as to cover the bit lines; Forming a photoresist pattern on the antireflection film to expose portions of the antireflection film between bit lines; Etching the exposed anti-reflection film portions and the second interlayer insulating film portions below to form a contact hole exposing the poly plug; Removing the remaining photoresist pattern and the anti-reflection film; Forming sidewall spacers on sidewalls of the contact holes; Depositing a polysilicon film to completely fill the contact hole on the substrate resultant; And a step of etching back the polysilicon layer.

Here, the hard mask nitride film is deposited to a thickness of 1000 to 1600 kPa, and the first interlayer insulating film is deposited to a thickness of 1500 to 2000 kPa on the bit line.

The anti-reflection film is etched using CF4, CH2F2, O2 and Ar gases, and the top power in the etching equipment is higher than the bottom power, and preferably the bottom power in the etching equipment is less than 1/3 of the top power. Do it.

In addition, the etching of the anti-reflection film is performed with an etching target such that the surface of the second interlayer insulating film is etched together after being completely removed.

Etching of the second interlayer dielectric layer is performed using C5F8, O2 and Ar gas at a low pressure of 15-20 mTorr, and at an electrode temperature higher than room temperature in order to secure the contact hole bottom CD.

In addition, the etching of the second interlayer dielectric layer may be performed under conditions in which the flow rate of Ar gas is minimized so that the top attack by Ar sputtering is minimized while flowing more C5F8 gas than O2 so that the hard mask nitride layer is etched with a gentle slope. do.

The method for forming a storage node contact of the present invention includes performing a wet cleaning to increase the bottom CD of the contact hole after forming the contact hole and before removing the remaining photoresist pattern and the anti-reflection film. It includes more.

According to the present invention, since the storage node contact is formed in a hole type, it is possible to prevent a self-aligned contact failure between the storage node and the bit line due to lack of process margin, and to secure the contact hole bottom CD (Critical Dimension). This allows for reliable formation of hole-type storage node contacts despite the lack of mask alignment margin.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating processes for forming a hole type storage node contact method according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a predetermined lower structure including a transistor is formed, and a first interlayer insulating film 2 is formed to cover the same, and a known LPC (Landing Plug Contact) is formed in place of the first interlayer insulating film 2. According to the process, the semiconductor substrate 1 in which the poly plug (not shown) was formed is provided.

Then, to form a tungsten bit line on the first interlayer insulating film 2 including the poly plug, a TiN film 3 as a barrier film, a tungsten film 4 as a bit line material and a nitride film 5 for a hard mask are formed. Are deposited in sequence, and then patterned to form several bit lines 6. At this time, the deposition thickness of the hard mask nitride film 5 is about 1800 to 2000 GPa.

Next, the second interlayer insulating film 7 is deposited on the first interlayer insulating film 2 including the bit line 6 to a thickness such that the deposition thickness on the bit line 6 is about 1500 to 2000 GPa. Then, after the antireflection film 8 is deposited on the second interlayer insulating film 5 to a thickness of 500 to 600 Å, a photoresist pattern 79 is formed on the antireflection film 8. At this time, the photoresist pattern (9) is formed to expose only the local area between the bit lines (6) to form a hole type storage node contact.

Referring to FIG. 1B, the antireflection film 6 is etched using the photoresist pattern 9. At this time, the anti-reflection film 6 is etched using CF4, O2 and Ar gas, but CH2F2 gas is additionally used to prevent attack of the tower portion due to insufficient thickness of the photoresist pattern 9. Do it. In addition, when the anti-reflection film 8 is etched, the surface of the second interlayer insulating film 7 may be etched about 1000 to 1300 후 after the etching target itself is completely removed.

Here, in addition to the addition of CH2F2 gas, the attack of the top portion due to the lack of the thickness of the photoresist layer pattern 9 makes the top power in the etching equipment higher than the bottom power, so that the polymer during etching ) Can also be prevented, in which case the bottom power is maintained at 1/3 or less of the top power to reduce ion straightness.

Referring to FIG. 1C, the main etching is performed on the second interlayer insulating film 8 using the remaining photoresist film pattern 9, thereby exposing a lower pattern, that is, a poly plug, between the bit lines 35. Contact holes 10 are formed.

In this case, the main etching is performed using C5F8, O2 and Ar gas, and at a low pressure of 15 to 20 mTorr to implement a high etching rate. In addition, since the contact hole 10 is formed between the bit lines 6 in the main etching, even when misalignment occurs between the photoresist pattern 9 and the bit line 6, the bottom CD of the contact hole 10 is formed. In order to ensure that the electrode temperature in the etching equipment is higher than room temperature so that the nitride film for the hard mask is etched with a gentle slope, and the oxide etchant C5F8 gas flows more than O2. On the other hand, when the main etching, the flow rate of the Ar gas is added to improve the uniformity to minimize the top attack by the Ar sputtering.

Subsequently, after the main etching, wet cleaning of the substrate resultant is performed to remove the second interlayer insulating layer, that is, the oxide layer remaining on the sidewall of the bit line, thereby making the bottom CD of the contact hole 10 as large as possible. give.

Referring to FIG. 1D, after the remaining photoresist pattern and the anti-reflection film are removed, a nitride nitride film for a spacer is deposited on the substrate resultant, and then blanket-etched to form sidewalls of the contact holes 10, more precisely, bit lines ( A nitride film spacer 11 is formed on the sidewall of 6) for electrical isolation from the storage node contacts to be subsequently formed. In this case, the nitride film spacer 11 is preferably formed to expose the poly plug.

Here, since the nitride film spacer 11 is formed after the formation of the contact hole 10 rather than forming the contact hole 10 through the self-aligned contact etching after the formation, the nitride film thickness is thinner than the conventional one. The bottom CD of the contact hole 10 can be secured, and in particular, there is no damage due to self-aligned contact etching, so that the storage node contact to be formed later, more precisely, complete electrical isolation from the storage node. Can be.

Referring to FIG. 1E, a conductive film, preferably a polysilicon film, is deposited to completely fill the contact hole 10 on the substrate resultant. Then, the polysilicon film is etched back to form a hole type storage node contact 12 according to the present invention.

Subsequently, although not shown, a storage node contacting the storage node contact 12 is formed on the second interlayer insulating layer 8 including the hole type storage node contact 12, and then a series of subsequent processes are performed. Complete the semiconductor device.

According to the method of the present invention as described above, since the storage node contacts are formed in a hole type instead of a line type, the thickness of the hard mask nitride layer can be lowered as compared with the case of forming the storage node contacts in the line type. For example, if the thickness of the hard mask nitride film in the line type storage node contact process is 3000 kPa or more, the thickness of the hard mask nitride film in the hole type storage node contact process may be approximately 2000 kPa or less, as in the present invention. This is because the damage of the hard mask nitride film at the time of forming the contact hole is not larger than in the case of forming the groove.

Accordingly, the method of the present invention can improve the profile of the bit line during the self-aligned contact etching process for forming the contact hole, thereby sufficiently securing the bottom CD of the contact hole, and furthermore, forming the nitride film spacer after forming the contact hole. By forming, the reliability of electrical isolation between the storage node and the bit line can be ensured.

Therefore, the method of the present invention can improve the contact hole bottom CD securing problem, that is, the resistance problem due to the lack of mask alignment margin, which is a conventional problem while applying the hole type storage node contact, and also, the line type. By replacing the process with the hole type process, the self-aligned contact failure between the storage node and the bit line can be solved.

As described above, in the present invention, since the storage node contacts are formed in a hole type rather than a line type, the thickness of the hard mask nitride layer can be reduced, thereby improving the etching profile of the bit line, and thus, the bottom CD of the contact hole. As a result, the problem of insufficient mask alignment margin can be improved, and the problem of self-aligned contact failure between the storage node and the bit line can be improved.

In addition, the present invention can omit CMP (Chemical Mechanical Polishing) for the polysilicon film in the line type process and can additionally obtain the effect of the process simplification.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (12)

Providing a semiconductor substrate having a first interlayer insulating film having a poly plug; Sequentially depositing a conductive film and a hard mask nitride film on the first interlayer insulating film; Patterning the hard mask nitride layer and the conductive layer to form bit lines; Sequentially depositing a second interlayer insulating film and an antireflection film on the first interlayer insulating film so as to cover the bit lines; Forming a photoresist pattern on the antireflection film to expose portions of the antireflection film between bit lines; Etching the exposed anti-reflection film portions and the second interlayer insulating film portions below to form a contact hole exposing the poly plug; Removing the remaining photoresist pattern and the anti-reflection film; Forming sidewall spacers on sidewalls of the contact holes; Depositing a polysilicon film to completely fill the contact hole on the substrate resultant; And And etching back the polysilicon layer. The method of claim 1, wherein the hard mask nitride layer is deposited to a thickness of 1800 to 2000 GPa. The method of claim 1, wherein the first interlayer dielectric layer is deposited to a thickness such that the deposition thickness on the bit line is 1500 to 2000 microseconds. The method of claim 1, wherein etching of the anti-reflection film is performed using CF 4, CH 2 F 2, O 2, and Ar gas. The method of claim 1, wherein the etching of the anti-reflection film is performed by making the top power in the etching equipment higher than the bottom power. The method of claim 5, wherein the etching of the anti-reflection film is performed by maintaining the bottom power in the etching equipment to 1/3 or less of the top power. 2. The storage node contact as claimed in claim 1, wherein the anti-reflection film is etched using an etch target that allows the thickness of a portion of the surface of the second interlayer insulating film to be etched together after the anti-reflection film is completely removed. Formation method. The method of claim 7, wherein the etching of the anti-reflection film A method of forming a storage node contact in a semiconductor device, characterized in that the etching target is performed such that the surface of the second interlayer insulating film is etched with about 1000 to 1300 Å. The method of claim 1, wherein the etching of the second interlayer insulating film A method of forming a storage node contact in a semiconductor device, characterized by using C5F8, O2 and Ar gases at a low pressure of 15-20 mTorr. 10. The method of claim 1, wherein the etching of the second interlayer dielectric layer is performed by increasing the electrode temperature in the etching equipment to room temperature to secure the contact hole bottom CD. . 10. The flow rate of the Ar gas is minimized so that the etching of the second interlayer insulating layer is performed by flowing more C5F8 gas than O2 so that the hard mask nitride layer is etched with a gentle slope. The storage node contact forming method of a semiconductor device, characterized in that performed under the condition of. The method of claim 1, after the forming of the contact hole and before removing the remaining photoresist pattern and the anti-reflection film, And performing a wet cleaning to enlarge the bottom CD of the contact hole.