KR20020072402A - Method for forming plug in semiconductor device - Google Patents
Method for forming plug in semiconductor device Download PDFInfo
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- KR20020072402A KR20020072402A KR1020010012300A KR20010012300A KR20020072402A KR 20020072402 A KR20020072402 A KR 20020072402A KR 1020010012300 A KR1020010012300 A KR 1020010012300A KR 20010012300 A KR20010012300 A KR 20010012300A KR 20020072402 A KR20020072402 A KR 20020072402A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 24
- 239000007789 gas Substances 0.000 claims description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 239000011261 inert gas Substances 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 125000006850 spacer group Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택플러그 형성방법에 관한 것으로서, 보다 구체적으로는 폴리실리콘막과 산화막간의 식각선택비를 조절하여 콘택플러그를 돌출형태로 형성하여 줌으로써 소자의 불량을 방지할 수 있는 반도체 소자의 콘택플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device, and more particularly, to a semiconductor device capable of preventing defects of a device by controlling an etching selectivity between a polysilicon film and an oxide film to form a contact plug in a protrusion shape. It relates to a method for forming a contact plug.
반도체소자중 DRAM 이나 플래쉬 메모리소자 등에서는 DC(direct contact) 또는 BC(buried contact) 공정을 진행하여 콘택을 형성한 후 폴리실리콘막을 사용하여 콘택내에 플러그를 형성하였다.Among semiconductor devices, a DRAM, a flash memory device, and the like are formed by performing a direct contact (DC) or buried contact (BC) process to form a contact, and then using a polysilicon film to form a plug in the contact.
폴리플러그를 형성하는 일반적인 방법은 콘택홀을 포함한 기판상에 폴리실리콘막을 증착한 후 드라이에칭공정을 진행하여 하부층의 DC 또는 BC 의 개구부에 도달할 때까지 에치백하여 콘택 플러그를 형성하였다.In the general method of forming a polyplug, a polysilicon film is deposited on a substrate including a contact hole, followed by a dry etching process to etch back until reaching an opening of a DC or BC of a lower layer to form a contact plug.
도 1a 내지 도 1c는 종래의 반도체 소자의 콘택 플러그를 형성하는 방법을 설명하기 위한 공정도를 도시한 것이다.1A to 1C show a process diagram for explaining a method of forming a contact plug of a conventional semiconductor device.
도 1a를 참조하면, 반도체 기판(10)상에 절연막으로서 산화막(11)을 형성하고, 상기 기판의 소정부분이 노출되도록 상기 산화막(11)을 식각하여 콘택(12), 예를 들면 DC 콘택(12)을 형성한다. 이어서, 상기 콘택(12)을 포함한 산화막(11)상에 폴리실리콘막(13)을 증착한다.Referring to FIG. 1A, an oxide film 11 is formed as an insulating film on a semiconductor substrate 10, and the oxide film 11 is etched to expose a predetermined portion of the substrate, thereby forming a contact 12, for example, a DC contact ( 12) form. Subsequently, a polysilicon film 13 is deposited on the oxide film 11 including the contact 12.
도 1b를 참조하면, 건식식각공정을 진행하여 상기 산화막(11)이 노출될 때까지 상기 폴리실리콘막(13)을 에치백한다. 이로써, 상기 콘택(12)내에 폴리 플러그(14)를 형성한다. 이때, 상기 콘택(12)내에 형성된 플러그(14)는 증착시의 폴리실리콘막(13)의 리세스가 DC 콘택(12)내에 그대로 전사되므로, 그의 표면이 리세스된 구조를 얻는다.Referring to FIG. 1B, the polysilicon layer 13 is etched back through a dry etching process until the oxide layer 11 is exposed. Thus, the poly plug 14 is formed in the contact 12. At this time, the plug 14 formed in the contact 12 transfers the recess of the polysilicon film 13 at the time of deposition into the DC contact 12 as it is, thereby obtaining a structure in which the surface thereof is recessed.
도 1c를 참조하면, 폴리 플러그(14) 형성후 표면 균일도(uniformity) 등의 차이로 인한 폴리 잔유물을 제거하기 위하여 오버에칭공정을 진행하면 콘택(12)내의 폴리 플러그(14a)의 리세스는 더욱 더 증가하게 된다.Referring to FIG. 1C, if the over-etching process is performed to remove poly residues due to differences in surface uniformity and the like after the formation of the poly plug 14, the recess of the poly plug 14a in the contact 12 may be further increased. Will increase further.
상기 콘택 플러그를 형성할 때 폴리실리콘막과 산화막의 식각선택비의 콘트롤이 매우 중요한 데, 종래의 콘택 플러그 형성방법은 감광막을 이용한 사진식각공정에 의해 콘택플러그를 형성하는 것이 아니라 개스 케미스트리(gas chemistry)를 이용하여 형성하였다.When forming the contact plug, it is very important to control the etching selectivity of the polysilicon film and the oxide film. In the conventional method of forming a contact plug, a gas chemistry is not formed by forming a contact plug by a photolithography process using a photosensitive film. It was formed using).
따라서, 개스 케미스트리에 의한 콘택 플러그 형성시 막질간의 식각선택비 확보에 지배적인 역할을 하는 카본 소오스를 콘트롤할 수 있는 요소가 없기 때문에 폴리실리콘막과 산화막간의 식각선택비를 확보하기 어려운 문제점이 있었다.Therefore, there is a problem in that it is difficult to secure the etching selectivity between the polysilicon film and the oxide film because there is no element that can control the carbon source that plays a dominant role in securing the etching selectivity between the films when forming the contact plug by the gas chemistry.
또한, 콘택홀이 노출될 때까지 즉, 산화막이 노출될 때까지 폴리실리콘막을 에치백한 다음 폴리잔유물을 제거하기 위하여 오버에칭공정을 수행하면 폴리 플러그의 리세스가 더욱 더 심해지는 문제점이 있었다.Further, when the polysilicon film is etched back until the contact hole is exposed, that is, the oxide film is exposed, and the overetching process is performed to remove the poly residue, the recess of the poly plug becomes more severe.
종래의 방법으로 폴리플러그가 형성된 반도체 소자는 후속공정을 진행할 때 폴리플러그의 리세스에 의해 불량이 발생되는 문제점이 있는데 이를 도 2a 내지 도2c를 참조하여 설명하면 다음과 같다.A semiconductor device in which a polyplug is formed by a conventional method has a problem in that a defect occurs due to a recess of a polyplug when a subsequent process is performed, which will be described below with reference to FIGS. 2A to 2C.
도 2a 내지 도 2c는 종래의 콘택 플러그 형성방법을 이용한 반도체 소자의 제조공정도를 도시한 것이다.2A to 2C illustrate a manufacturing process diagram of a semiconductor device using a conventional method for forming a contact plug.
도 2a를 참조하면, 반도체 기판(20)상에 절연막(21)으로서 산화막을 형성한 다음, 상기 기판(20)의 일부분이 노출되도록 콘택(22)을 형성한다. 이어서 도 1a 내지 도 1c 에 도시된 방법으로 콘택(22)내에 폴리 플러그(23)를 형성한다.Referring to FIG. 2A, an oxide film is formed as an insulating film 21 on a semiconductor substrate 20, and then a contact 22 is formed to expose a portion of the substrate 20. A poly plug 23 is then formed in the contact 22 in the manner shown in FIGS. 1A-1C.
이어서, 에치스톱퍼용 절연막(24)으로 SiN 막 또는 SiON 막을 증착하고, 그위에 층간 절연막(25)으로서 산화막을 형성한다. 이어서, 상기 층간 절연막인 산화막(25)상에 감광막(26)을 형성한다.Subsequently, a SiN film or a SiON film is deposited with the etch stopper insulating film 24, and an oxide film is formed as the interlayer insulating film 25 thereon. Subsequently, a photosensitive film 26 is formed on the oxide film 25 as the interlayer insulating film.
도 2b를 참조하면, 상기 감광막(26)을 마스크로 하여 상기 산화막(25) 및 질화막(24)을 식각하여 비어홀(27)을 형성한다. 이로써, 콘택(22)내의 폴리플러그(23)가 노출되어진다.Referring to FIG. 2B, the via layer 27 is formed by etching the oxide layer 25 and the nitride layer 24 using the photosensitive layer 26 as a mask. As a result, the poly plug 23 in the contact 22 is exposed.
도 2c를 참조하면, 상기 비어홀(27)을 통해 상기 콘택플러그(23)와 콘택되는 전도층, 예를 들어 비트라인(28)을 형성한다.Referring to FIG. 2C, a conductive layer, for example, a bit line 28, is formed in contact with the contact plug 23 through the via hole 27.
상기한 바와같은 반도체 소자의 제조방법은 콘택(22)내의 폴리 플러그(23)의 리세스가 심하기 때문에, 비트라인(28)과 상기 콘택플러그(23)를 콘택시키기 위한 비어홀(27)형성공정시 도 2b에서와 같이 에치스톱퍼로 사용된 SiN 막 또는 SiON막의 잔유물(24a)이 콘택(22)내에 스페이서 형태로 존재하게 된다.In the method of manufacturing the semiconductor device as described above, since the recesses of the poly plug 23 in the contact 22 are severe, the process of forming the via hole 27 for contacting the bit line 28 and the contact plug 23 is performed. As shown in FIG. 2B, the residue 24a of the SiN film or the SiON film used as the etch stopper is present in the contact 22 in the form of a spacer.
따라서, 상기 비어홀(27)내에 잔유물(24a)이 존재하는 상태에서 도 2c와 같이 비트라인(28)을 형성하게 되면, 폴리플러그(23)와 비트라인(28)간의 접촉불량을초래하고, 이에 따라 콘택저항이 증가하여 소자가 페일되는 문제점이 있었다. 도 3에는 페일 프로파일이 도시되어 있다.Therefore, when the bit line 28 is formed as shown in FIG. 2C in the state where the residue 24a exists in the via hole 27, a poor contact between the polyplug 23 and the bit line 28 may occur. Accordingly, there is a problem in that the device fails due to an increase in contact resistance. 3 shows a fail profile.
또한, 상기 비어홀(27)내의 잔유물(24a)이 존재하는 것을 방지하기 위해서는 충분한 식각량으로 상기 비어홀내의 층간 절연막과 에치스톱퍼를 식각하여야 한다. 그러나, 이러한 오버에칭에 의해 폴리플러그의 리세스는 더욱 더 증가하게 되고, 또한 절연막으로 사용되는 산화막의 소모가 증가되어 절연막으로서의 역할을 제대로 수행할 수 없어 소자의 불량을 초래하는 문제점이 있었다.In addition, in order to prevent the residue 24a in the via hole 27 from being present, the interlayer insulating layer and the etch stopper in the via hole must be etched with a sufficient etching amount. However, such over-etching increases the recesses of the poly plugs more and more, and the consumption of the oxide film used as the insulating film is increased, so that the role of the insulating film cannot be properly performed, resulting in a defect of the device.
본 발명은 상기한 바와같은 종래 기술의 문제점을 해결하기 위한 것으로서, 폴리실리콘막과 산화막의 식각선택비를 조절하여 폴리플러그를 돌출형태로 형성하여 소자의 불량을 방지할 수 있는 반도체소자의 콘택플러그 형성방법을 제공하는 데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, by adjusting the etch selectivity of the polysilicon film and the oxide film to form a poly plug protruding to prevent the defect of the device contact plug of the semiconductor device The purpose is to provide a formation method.
도 1a 내지 도 1c는 종래의 반도체 소자의 콘택플러그 형성방법을 설명하기 위한 공정단면도,1A to 1C are cross-sectional views illustrating a method of forming a contact plug of a conventional semiconductor device;
도 2a 내지 도 2c는 종래의 콘택플러그 형성방법을 이용한 반도체 소자의 제조방법을 설명하기 위한 공정단면도,2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device using a conventional method for forming a contact plug;
도 3은 종래의 방법에 의해 형성된 리세스된 콘택플러그를 보여주는 사진,3 is a photograph showing a recessed contact plug formed by a conventional method;
도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체소자의 콘택플러그를 형성하는 방법을 설명하기 위한 공정단면도,4A through 4D are cross-sectional views illustrating a method of forming a contact plug of a semiconductor device according to an embodiment of the present invention;
도 5a 내지 도 5c는 본 발명의 콘택 플러그 형성방법을 이용한 반도체 소자의 제조방법을 설명하기 위한 공정단면도,5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device using the contact plug forming method of the present invention;
도 6은 본 발명의 방법에 의해 형성된 돌출된 콘택플러그를 보여주는 사진,Figure 6 is a photograph showing a protruding contact plug formed by the method of the present invention,
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
30, 40 : 반도체 기판 31, 31a, 41 : 산화막30, 40: semiconductor substrate 31, 31a, 41: oxide film
32, 42 : 콘택 33 : 폴리실리콘막32, 42: contact 33: polysilicon film
34, 34a, 43 : 플러그 44 : 질화막34, 34a, 43: plug 44: nitride film
45 : 층간 절연막(산화막) 46 : 감광막45: interlayer insulation film (oxide film) 46: photosensitive film
47 : 비어홀 48 : 비트라인47: beer hole 48: bit line
이와 같은 목적을 달성하기 위한 본 발명은 반도체 기판상에 콘택홀을 구비한 층간 절연막을 형성하는 단계와; 상기 콘택홀을 포함한 층간 절연막상에 플러그용 도전막을 형성하는 단계와; 상기 도전막을 에치백하여 상기 콘택홀에 플러그를 형성하는 단계와; 상기 플러그가 돌출되도록 상기 층간 절연막을 식각하는 단계를 포함하는 반도체 소자의 콘택플러그 형성방법을 제공하는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming an interlayer insulating film having a contact hole on the semiconductor substrate; Forming a plug conductive film on the interlayer insulating film including the contact hole; Etching back the conductive layer to form a plug in the contact hole; It provides a method for forming a contact plug of a semiconductor device comprising the step of etching the interlayer insulating film so that the plug protrudes.
상기 층간 절연막은 폴리실리콘막에 대한 산화막의 식각선택비가 1이상인 조건에서 식각하고, 이를 위해 CxHyFz 가스에 O2가스 또는 비활성가스를 첨가하여 탄소의 양을 조절하는 것을 특징으로 한다.The interlayer insulating film is etched under the condition that the etching selectivity of the oxide film relative to the polysilicon film is 1 or more, and for this purpose, the amount of carbon is controlled by adding O 2 gas or an inert gas to the CxHyFz gas.
또한, 본 발명은 반도체 기판상에 콘택홀을 구비한 산화막을 형성하는 단계와; 상기 콘택홀을 포함한 산화막상에 폴리실리콘막을 형성하는 단계와; 산화막에 대한 폴리실리콘막의 식각선택비가 1이상인 조건에서 상기 폴리실리콘막을 에치백하여 콘택플러그를 형성하는 단계와; 산화막에 대한 폴리실리콘막의 식각선택비가 1이하인 조건에서 상기 산화막을 식각하여 돌출된 형태의 콘택플러그를 형성하는 단계를 포함하며, 상기 콘택플러그를 형성하는 단계와 산화막을 식각하는 단계는 동일 챔버내에서 수행되는 반도체 소자의 콘택플러그 형성방법을 제공하는 것을 특징으로 한다.In addition, the present invention comprises the steps of forming an oxide film having a contact hole on the semiconductor substrate; Forming a polysilicon film on the oxide film including the contact hole; Forming a contact plug by etching back the polysilicon film under the condition that the etching selectivity ratio of the polysilicon film to the oxide film is 1 or more; Etching the oxide film to form a protruding contact plug under the condition that the etching selectivity ratio of the polysilicon film to the oxide film is less than or equal to 1, wherein forming the contact plug and etching the oxide film are performed in the same chamber. It is characterized by providing a method for forming a contact plug of a semiconductor device to be performed.
또한, 본 발명은 반도체 기판상에 콘택홀을 구비한 층간 절연막으로 산화막을 형성하는 단계와; 상기 콘택홀을 포함한 층간 절연막상에 플러그용 폴리실리콘막을 형성하는 단계와; 상기 폴리실리콘막을 에치백하여 상기 콘택홀에 플러그를 형성하는 단계와; 상기 플러그가 돌출되도록 상기 층간 절연막을 습식식각하는 단계를 포함하며, 상기 습식식각단계에서 폴리실리콘막에 대한 산화막의 선택비가 양호한 HF 와 같은 에천트를 사용하여 습식식각하는 반도체 소자의 콘택플러그 형성방법을 제공하는 것을 특징으로 한다.In addition, the present invention comprises the steps of forming an oxide film with an interlayer insulating film having a contact hole on the semiconductor substrate; Forming a polysilicon film for a plug on the interlayer insulating film including the contact hole; Etching back the polysilicon layer to form a plug in the contact hole; And wet etching the interlayer insulating layer to protrude the plug, and in the wet etching step, a method of forming a contact plug of a semiconductor device wet etching using an etchant such as HF having a good selection ratio of an oxide film to a polysilicon film. It characterized in that to provide.
이하, 본 발명을 보다 구체적으로 설명하기 위하여 본 발명에 따른 일 실시예를 첨부 도면을 참조하면서 보다 상세하게 설명하고자 한다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.
도 4a 내지 도 4c는 본 발명의 일 실시예에 따른 반도체 소자의 콘택플러그를 형성하기 위한 공정도를 도시한 것이다.4A to 4C illustrate a process diagram for forming a contact plug of a semiconductor device according to an embodiment of the present invention.
본 발명의 일 실시예에 따른 반도체 소자의 콘택 플러그 형성방법은 개스 케미스트리를 조절하여 식각개스중 카본량을 조절하여 폴리실리콘막과 산화막에 대한 식각선택비를 콘트롤하여 콘택 플러그를 돌출된 형태로 형성한다.In the method of forming a contact plug of a semiconductor device according to an embodiment of the present invention, a contact plug is formed in a protruding form by controlling an amount of carbon in an etching gas by controlling a gas chemistry to control an etching selectivity of a polysilicon film and an oxide film. do.
도 4a를 참조하면, 반도체 기판(30)상에 절연막(31)으로서 산화막을 형성한 다음, 기판의 소정부분이 노출되도록 상기 산화막(31)을 식각하여 콘택(32)을 형성한다.Referring to FIG. 4A, an oxide layer is formed as an insulating layer 31 on a semiconductor substrate 30, and then the oxide layer 31 is etched to expose a portion of the substrate to form a contact 32.
도 4b와 같이 상기 콘택(32)을 포함한 산화막(31)상에 폴리실리콘막(33)을 증착하고, 도 4c와 같이 상기 산화막(31)이 노출될 때까지 상기 폴리실리콘막(33)을 식각하면 콘택(32)내에 폴리 플러그(34)가 형성된다. 이때, 폴리실리콘막(33)은 상기 산화막(31)에 대한 폴리실리콘막의 식각선택비가 1이상인 조건, 다시 말하면 산화막에 대한 폴리실리콘막의 식각선택비가 1이하인 조건에서 에치백된다.A polysilicon film 33 is deposited on the oxide film 31 including the contact 32 as shown in FIG. 4B, and the polysilicon film 33 is etched until the oxide film 31 is exposed as shown in FIG. 4C. A poly plug 34 is formed in the lower surface of the contact 32. In this case, the polysilicon film 33 is etched back under the condition that the etching selectivity of the polysilicon film with respect to the oxide film 31 is one or more, that is, the etching selectivity of the polysilicon film with respect to the oxide film is one or less.
이때, 폴리실리콘막(33)은 건식식각공정, 즉 저압상태에서 이방성에칭(anisotropic etching)인 RIE(reactive ion etching) 공정을 통해 상기 산화막(31)이 노출될 때까지 전면 에칭한다.At this time, the polysilicon layer 33 is etched entirely until the oxide layer 31 is exposed through a dry etching process, that is, an active ion etching (RIE) process, which is anisotropic etching in a low pressure state.
도 4d와 같이, 폴리 잔유물을 제거하기 위한 식각공정을 진행한다. 종래에는 폴리 잔유물을 제거하기 위하여 폴리실리콘막을 오버에칭하였으나, 본 발명의 실시예에서는 폴리실리콘막에 대한 산화막의 식각선택비가 1이상인 조건에서 폴리잔유물을 제거하기 위한 식각공정을 진행하면, 폴리실리콘막보다 산화막이 상대적으로빠르게 식각되어진다.As shown in Figure 4d, the etching process for removing the poly residue. Conventionally, the polysilicon film is overetched to remove the poly residue, but in the embodiment of the present invention, when the etching process for removing the poly residue is performed under the condition that the etching selectivity ratio of the oxide film to the polysilicon film is greater than or equal to the polysilicon film, The oxide film is etched relatively quickly.
따라서, 폴리 플러그 형성공정후 남아있는 폴리 잔유물을 제거할 수 있을 뿐만 아니라 폴리 플러그보다 산화막이 빠르게 식각되므로, 폴리플러그(34a)는 산화막(31a)보다 돌출된 형태가 된다. 그러므로, 폴리플러그(34a)의 리세스는 더 이상 증가하지 않게 된다.Therefore, not only the poly residues remaining after the poly plug forming process can be removed but also the oxide film is etched faster than the poly plug, so that the poly plug 34a is more protruding than the oxide film 31a. Therefore, the recess of the polyplug 34a no longer increases.
즉, 본 발명의 일 실시예에서는, 폴리플러그를 형성하기 위한 폴리실리콘막을 2차례의 건식식각공정을 통해 식각한다. 1차 건식식각 공정에서는 산화막(31)에 대한 폴리실리콘막(33)의 식각선택비가 1이상인 조건에서 폴리실리콘막(33)을 식각하여 폴리 플러그(34)를 콘택(32)내에 형성한다. 2차 건식식각 공정에서는 산화막(31)에 대한 폴리실리콘막(33)의 식각선택비가 1이하인 조건에서 진행하는데, 이 경우에는 폴리플러그(34)보다 산화막(31)이 빠르게 식각되므로, 최종적으로, 콘택(32)내에 돌출된 형태의 폴리 플러그(34a)가 형성된다.That is, in one embodiment of the present invention, the polysilicon film for forming the polyplug is etched through two dry etching processes. In the first dry etching process, the polysilicon film 33 is etched under the condition that the etching selectivity of the polysilicon film 33 to the oxide film 31 is 1 or more to form the poly plug 34 in the contact 32. In the second dry etching process, the etching selectivity of the polysilicon film 33 to the oxide film 31 is less than or equal to 1, and in this case, since the oxide film 31 is etched faster than the polyplug 34, finally, A protruding poly plug 34a is formed in the contact 32.
이때, 폴리플러그를 형성하기 위한 2단계 건식식각 공정은 동일한 RIE 챔버내에서 인시튜방식으로 진행된다.At this time, the two-step dry etching process for forming the polyplug is in-situ in the same RIE chamber.
이를 위하여 본 발명의 일 실시예에 따르면 2차 식각공정에서는 1차 식각공정과는 다른 개스 케미스트리를 이용하는데, 산화막에 대한 폴리실리콘막의 식각선택비가 1이하가 되도록 CxHyFz 가스에 O2가스를 첨가하여 탄소의 함유량을 조정하였다. 2차 식각공정에서는 C/F(carbon/Fluorine)의 비율중 카본(C)의 양을 일정비율로 콘트롤하는 것이 필수적인데, 본 발명에서는 이를 위하여 CxHyFz의 식각가스에 O2를 첨가하여 C의 비율을 조정하였다.To this end, according to an embodiment of the present invention, the second etching process uses a gas chemistry different from the primary etching process, by adding O 2 gas to the CxHyFz gas so that the etching selectivity of the polysilicon film with respect to the oxide film is 1 or less. The content of carbon was adjusted. In the second etching process, it is essential to control the amount of carbon (C) in the ratio of C / F (carbon / Fluorine) to a certain ratio. In the present invention, for this purpose, by adding O 2 to the etching gas of CxHyFz, the ratio of C Was adjusted.
이때, 총 식각개스의 양(sccm)중 산소(O2)의 함유량(O2/CxHyFz+O2)이 50% 이상의 범위에서는 카본(C)의 함유량이 감소함과 동시에 상대적으로 플로린(F)의 함유량이 증가하게 되는데, 이는 폴리실리콘막보다는 산화막과의 반응이 활발하게 일어남으로써 폴리실리콘막에 대한 산화막의 식각선택비를 증가시키게 되는 것이다.At this time, when the content (O 2 / CxHyFz + O 2 ) of oxygen (O 2 ) in the amount (sccm) of the total etching gas is 50% or more, the content of carbon (C) decreases and relatively the florin (F) The content of is increased, which increases the etching selectivity of the oxide film relative to the polysilicon film by actively reacting with the oxide film rather than the polysilicon film.
한편, 본 발명의 일 실시예에 따른 콘택플러그 형성방법에서는 2차 식각공정시 산화막에 대한 폴리실리콘막의 식각선택비를 콘트롤하기 위한 또 다른 방법으로 일정량의 Ar, N2등과 같은 비활성가스를 추가로 첨가하는 방법이 있다.Meanwhile, in the method for forming a contact plug according to an embodiment of the present invention, another method for controlling the etching selectivity ratio of the polysilicon film to the oxide film during the secondary etching process may further include an inert gas such as Ar and N 2 . There is a method of adding.
비활성가스를 첨가하는 경우에는 총 식각가스의 양(sccm)중 비활성가스의 양(Ar/CxHyFz+O2+Ar)을 40% 이하로 조정하는데, 비활성가스가 40%이하의 레인지에서는 스퍼터링 효과에 의해 폴리실리콘막에 대한 산화막의 선택비를 더 증가시킬 수 있다.When inert gas is added, adjust the amount of inert gas (Ar / CxHyFz + O 2 + Ar) to 40% or less of the total amount of etching gas (sccm). This can further increase the selectivity of the oxide film to the polysilicon film.
본 발명의 돌출형태의 콘택플러그를 형성하면 후속공정시 콘택플러그의 리세스에 의한 소자의 불량이 방지되는데, 이를 도 5a 내지 도 5c를 참조하여 설명하면 다음과 같다.Formation of the protruding contact plug of the present invention prevents a defect of the device due to the recess of the contact plug in a subsequent process, which will be described below with reference to FIGS. 5A to 5C.
도 5a 내지 도 5c는 본 발명의 콘택 플러그 형성방법을 이용한 반도체 소자의 제조공정도를 도시한 것이다.5A to 5C illustrate a manufacturing process diagram of a semiconductor device using the contact plug forming method of the present invention.
도 5a를 참조하면, 반도체 기판(40)상에 절연막(41)으로서 산화막을 형성한 다음, 상기 기판(40)의 일부분이 노출되도록 콘택(42)을 형성하고, 상기한 본 발명의 방법을 이용하여 콘택(42)내에 돌출된 형태의 폴리 플러그(43)를 형성한다.Referring to FIG. 5A, an oxide film is formed as an insulating film 41 on a semiconductor substrate 40, and then a contact 42 is formed to expose a portion of the substrate 40, using the method of the present invention described above. As a result, a poly plug 43 having a protruding shape is formed in the contact 42.
이어서, SiN 막 또는 SiON 막과 같은 에치스톱퍼용 절연막(44)과 산화막으로된 층간 절연막(45)을 순차 형성한 다음 산화막(45)상에 비어홀을 형성하기 위한 감광막(46)을 형성한다.Subsequently, an etch stopper insulating film 44 such as a SiN film or a SiON film and an interlayer insulating film 45 made of an oxide film are sequentially formed, and then a photosensitive film 46 for forming via holes is formed on the oxide film 45.
도 5b를 참조하면, 상기 감광막(46)을 마스크로 하여 상기 산화막(45) 및 질화막(44)을 식각하여 비어홀(47)을 형성한다. 이로써, 콘택(42)내의 폴리플러그(43)가 노출되어진다.Referring to FIG. 5B, the via layer 47 is formed by etching the oxide layer 45 and the nitride layer 44 using the photosensitive layer 46 as a mask. As a result, the polyplug 43 in the contact 42 is exposed.
도 5c를 참조하면, 상기 비어홀(47)을 통해 상기 콘택플러그(43)와 콘택되는 전도층, 예를 들어 비트라인(48)을 형성한다.Referring to FIG. 5C, a conductive layer, for example, a bit line 48, is formed to contact the contact plug 43 through the via hole 47.
상기한 바와같은 반도체 소자의 제조방법은 콘택(42)내의 폴리 플러그(43)가 돌출된 형태로 형성되기 때문에, 비어홀 형성시 콘택(42)내에 에치스톱퍼용 절연막(44)이 잔존하는 문제점을 해결할 수 있다.In the method of manufacturing the semiconductor device as described above, since the poly plug 43 in the contact 42 is formed to protrude, the problem that the insulating film 44 for the etch stopper remains in the contact 42 when the via hole is formed is solved. Can be.
이에 따라 잔존물을 제거하기 위한 오버에칭공정이 배제되어 리세스없는 폴리플러그의 양호한 프로파일을 확보할 수 있다. 또한, 비트라인(48)과 콘택플러그(43)간의 접촉을 향상시킬 수 있을 뿐만 아니라 접촉저항을 감소시킬 수 있게 된다.This eliminates the over-etching process to remove the residue, thereby ensuring a good profile of the recessed polyplug. In addition, the contact between the bit line 48 and the contact plug 43 can be improved as well as the contact resistance can be reduced.
본 발명의 일 실시예에서는 개스 케미스트리를 변화시킨 건식식각공정에 의해 폴리 플러그를 형성하는 방법을 제시하였으나, 폴리실리콘막에 대한 산화막의 선택비가 높은 산화막 에천트를 이용하여 콘트롤하면 습식식각을 통해서도 원하는 프로파일을 구현할 수 있다.In one embodiment of the present invention, a method of forming a poly plug by a dry etching process in which a gas chemistry is changed is proposed. You can implement a profile.
본 발명의 다른 실시예로서 도 4c와 같이 폴리실리콘막을 1차로 건식식각한 다음, 도 4d와 같이 산화막을 식각하기 위한 2차식각공정에서는 습식식각공정을 통해 식각하여 독출된 형태의 콘택플러그를 형성하는 것이다.As another embodiment of the present invention, as shown in FIG. 4C, the polysilicon film is primarily dry-etched, and then, in the secondary etching process for etching the oxide film as shown in FIG. 4D, a contact plug having a read shape is formed by etching through a wet etching process. It is.
즉, 콘택(32)을 포함한 산화막(31)상에 폴리실리콘막(33)을 증착한 다음 상기 산화막(33)이 노출될 때까지 건식식각공정으로 식각하고, 이어서 2차 식각공정에서는 폴리실리콘막에 대한 산화막의 식각선택비가 우수한 습식 케미칼, 즉 HF와 같은 산화막 에천트를 이용하여 산화막만을 선택적으로 식각하여 주면, 돌출된 형태의 폴리 플러그를 형성하는 것이 가능하다.That is, the polysilicon film 33 is deposited on the oxide film 31 including the contact 32 and then etched by a dry etching process until the oxide film 33 is exposed, followed by the polysilicon film in the secondary etching process. If only the oxide film is selectively etched using a wet chemical having excellent etching selectivity to the oxide, that is, an oxide etchant such as HF, it is possible to form a protruding poly plug.
따라서, 상기한 바와같은 본 발명의 콘택플러그 형성방법에 따르면, 1차로 산화막에 대한 폴리실리콘막의 식각선택비가 1이상인 조건에서 폴리실리콘막을 식각하여 폴리 플러그를 형성한 다음 2차로 산화막에 대한 폴리실리콘막의 식각선택비가 1이하인 조건에서 산화막을 식각하여 폴리 플러그를 돌출한 형태로 형성하여 줌으로써, 폴리플러그의 리세스에 의한 소자불량을 방지할 수 있는 이점이 있다.Therefore, according to the contact plug forming method of the present invention as described above, the polysilicon film is first etched under the condition that the etching selectivity ratio of the polysilicon film to the oxide film is 1 or more, and then the poly plug is formed to form the polysilicon film for the second oxide film. By etching the oxide film under the condition that the etching selectivity is 1 or less, the poly plug is formed to protrude, thereby preventing device defects due to the recess of the poly plug.
상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.
Claims (15)
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| KR1020010012300A KR20020072402A (en) | 2001-03-09 | 2001-03-09 | Method for forming plug in semiconductor device |
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| KR1020010012300A KR20020072402A (en) | 2001-03-09 | 2001-03-09 | Method for forming plug in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7745338B2 (en) | 2006-07-11 | 2010-06-29 | Samsung Electronics Co., Ltd. | Method of forming fine pitch hardmask patterns and method of forming fine patterns of semiconductor device using the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7745338B2 (en) | 2006-07-11 | 2010-06-29 | Samsung Electronics Co., Ltd. | Method of forming fine pitch hardmask patterns and method of forming fine patterns of semiconductor device using the same |
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