KR20040088842A - Apparatus and method for compensating synchronizing signal - Google Patents

Abstract

PURPOSE: A device of compensating for a synchronous signal and a method thereof are provided to generate a synchronous signal having a certain section length based on an information detection signal produced at a normal time, if extracted features are abnormal. CONSTITUTION: An information recording section detector(11) detects an information recording section of a signal, and generates an information detection signal having a high information recording section. A synchronous signal compensator/generator(12) extracts features of the high section of the information detection signal, generates a window signal based on the information detection signal produced when the extracted features are normal, and generates a synchronous signal based on the information detection signal produced at a normal time when a phase difference between the information detection signal and the window signal is within an error range and the extracted features are normal. If the phase difference is within the error range and the extracted features are abnormal, the compensator/generator(12) generates a synchronous signal having a certain high section length.

Description

Apparatus and method for compensating synchronizing signal

The present invention relates to an apparatus and method for compensating for a distorted sync signal.

In a disk medium such as an optical disk, spiral grooves are formed for tracking. In addition, in order to record the address information, the wobbling is wobbling at regular intervals in correspondence with the address information. At this time, the recording of the address information is implemented by modulating a carrier wave with a minimum shift keying (MSK) corresponding to the address information. In order to be able to demodulate at the same timing as the modulation timing of the modulating side at the demodulating side, an MSK synchronization signal having the same period as the period in which the address information is recorded is used. However, conventionally, since the MSK signal is generated based on the MSK signal input to the demodulating side, when the MSK signal is distorted due to various non-ideal factors such as surrounding radio wave interference, the MSK sync signal is also distorted, thereby providing reliable MSK. There was a problem that it could not be demodulated.

The technical problem to be achieved by the present invention is that even when a modulated signal is distorted due to various non-ideal factors such as surrounding radio wave interference, the synchronous signal of the modulated signal is constantly output without distortion, thereby enabling reliable demodulation. An apparatus and method are provided, and in particular, an apparatus and method for enabling reliable demodulation of an MSK signal.

1 is a block diagram of a synchronization signal compensation apparatus according to an embodiment of the present invention.

2 is a block diagram of an MSK synchronization signal compensation apparatus according to an embodiment of the present invention.

3 is a waveform diagram of various signals used in the process of generating the MSK detection signal of the present invention.

4A and 4B are waveform diagrams of various signals used in the process of generating the MSK synchronization signal of the present invention.

5 is a flowchart illustrating a synchronization signal compensation method according to an embodiment of the present invention.

6A and 6B are diagrams illustrating a MSK synchronization signal compensation method according to an embodiment of the present invention.

In accordance with another aspect of the present invention, an apparatus for compensating for synchronizing signals includes: an information recording section detecting unit configured to detect an information recording section with respect to a predetermined signal and to generate an information detection signal having the detected information recording section as a high section; And extracting a characteristic of a high section of the information detection signal, generating a window signal based on the information detection signal at a time when the extracted characteristic is normal, and a phase difference between the information detection signal and the window signal is within an error range. When the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal timing, and when the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is abnormal, And a synchronization signal compensation / generation unit configured to generate a synchronization signal having a constant high length based on the information detection signal at a normal time just before the abnormal time.

According to another aspect of the present invention, there is provided an MSK synchronization signal compensation apparatus, comprising: an MSK detection unit for detecting an information recording section with respect to an MSK signal, and generating an MSK detection signal having the detected information recording section as a high section; And extracting a length of the high section of the MSK detection signal, generating an MSK window signal based on the MSK detection signal at a point in time at which the extracted length is normal, and the high section of the MSK detection signal is a high section of the MSK window signal. When the extracted length is normal and the extracted length is normal, the MSK synchronization signal is generated based on the MSK detection signal at the normal time, and the high interval of the MSK detection signal is within the high interval of the MSK window signal and the extracted characteristics. The abnormal time point includes an MSK sync signal compensation / generation unit for generating an MSK sync signal having a constant high length based on the MSK detection signal at the normal time point just before the abnormal time point.

According to another aspect of the present invention, there is provided a synchronization signal compensation method according to the present invention. (A) Detecting an information recording section with respect to a predetermined signal, and generating an information detection signal having the detected information recording section as a high section. step; And (b) extracting a characteristic of a high section of the information detection signal, generating a window signal based on the information detection signal at the time when the extracted characteristic is normal, and a phase difference between the information detection signal and the window signal is different. When the extracted characteristic is within the error range and the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal timing, and the phase difference between the information detection signal and the window signal is within the error range and the extracted characteristic At an abnormal time point, generating a synchronization signal having a constant length of a high section based on the information detection signal at a normal time point immediately before the abnormal time point.

(A) detecting an information recording section with respect to the MSK signal and generating an MSK detection signal having the detected information recording section as a high section according to the present invention for solving the another technical problem; And (b) extracting a length of the high section of the MSK detection signal, generating an MSK window signal based on the MSK detection signal at the time when the extracted length is normal, and the high section of the MSK detection signal is the MSK window. When the extracted length is within the normal period and the extracted length is normal, the MSK synchronization signal is generated based on the MSK detection signal at the normal time point, and the high period of the MSK detection signal is within the high period of the MSK window signal and the When the extracted characteristic is abnormal, the method may include generating an MSK synchronization signal having a constant high section length based on the MSK detection signal at the normal time immediately before the abnormal time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a synchronization signal compensation apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the synchronization signal compensating device includes an information recording section detector 11 and a synchronization signal compensation / generation unit 12.

The information recording section detection unit 11 detects the information recording section with respect to the input predetermined signal, and generates an information detection signal in which the detected information recording section is set as the high section. When information is recorded in a signal, the section in which the information is recorded is modulated in amplitude or phase so as to be distinguished from the section in which no information is recorded. AM (Amplitude Modulation) is when the phase is fixed and only amplitude is modulated, Frequency (Frequency Modulation) is when the amplitude is fixed and only phase is modulated, and BPSK (Binary Phase Shift Keying) modulates both amplitude and phase It is the case. The information recording section detection section 11 detects a section in which the amplitude or phase is modulated in this manner, and generates an information detection signal in which the detected section is set to a high section and the remaining section is set to a low section. In general, the high interval refers to a section in which the signal value is "1" in the digital signal, and the low section refers to a section in which the signal value is "0" in the digital signal.

Referring to FIG. 1, the information recording section detector 11 is composed of an analog-digital converter 111, a phase locked loop circuit 112, and an information detection signal generator 113.

The analog to digital converter 111 converts an analog signal into a digital signal. Since only the section in which the information is recorded needs to be detected, the analog signal is converted into a digital signal by setting only a specific value or more high. At this time, an analog signal is converted into a digital signal using a limiter or the like. In particular, in the case of digital modulation, since the digital signal is converted into an analog signal, the demodulation step converts the analog signal into a digital signal.

The phase locked loop circuit 112 generates a phase locked clock signal having a frequency equal to the fundamental frequency of the digital signal. The phase locked loop circuit (PLL) circuit 112 includes a voltage controlled oscillator (VCO), a feedback circuit, a comparator, and the like, in which a frequency of an output signal is determined by an input voltage. By feeding back the frequency of the signal output from the VCO, the comparator compares the fixed low frequency, generates a voltage corresponding to the difference between the two frequencies, and inputs the generated voltage back to the VCO, thereby providing a phase locked loop circuit 112. Always outputs a constant frequency. That is, the phase locked loop circuit 112 outputs a signal having a fixed frequency. In other words, a signal whose phase is fixed is output. Because phase is an integral frequency, the concept of fixing frequency and the concept of fixing phase mean the same thing. The phase locked loop 112 of the present invention generates a phase locked clock signal having a frequency equal to a fundamental frequency of the digital signal converted by the analog-digital converter 111, that is, a frequency of an unmodulated section.

The information detection signal generator 113 compares the phase of the digital signal with the phase of the phase locked clock signal, detects an information recording section with respect to the digital signal, and generates an information detection signal having the detected information recording section as a high section. do. Since the phase-locked clock signal is a phase-locked signal, comparing the phase-locked digital signal with a phase-modulated digital signal for only a section in which information is recorded, it is possible to know which part of the digital signal has been modulated. . At this time, a phase-modulated section, that is, an information recording section, is detected, and during this section, an information detection signal is generated in which the signal becomes "1" and the signal becomes "0" during the remaining sections.

The synchronization signal compensation / generation unit 12 extracts a characteristic of the high section of the information detection signal, generates a window signal based on the information detection signal at the time when the extracted characteristic is normal, and phases of the information detection signal and the window signal. When the difference is within the error range and the extracted feature is normal, the synchronization signal is generated based on the information detection signal at the normal time point. When the phase difference between the information detection signal and the window signal is within the error range and the extracted feature is abnormal A synchronization signal having a constant high length is generated based on the information detection signal at a normal time just before the abnormal time. Here, the synchronization signal refers to a signal transmitted to synchronize the demodulation period with the modulator. Therefore, the synchronization signal should always be output constantly.

Referring to FIG. 1, the sync signal compensator / generator 12 includes an information detection signal characteristic extractor 121, a sync clock signal generator 122, a window signal generator 123, and a sync signal generator 124. , A basic synchronous clock signal generator 125, and a signal reliability value counter 126.

The information detection signal characteristic extraction unit 121 extracts the characteristics of the high section of the information detection signal. Here, the characteristics of the high section may include the length of the high section, the position of the high section, and the like.

The synchronous clock signal generator 122 generates a synchronous clock signal based on the information detection signal when the extracted characteristic is normal. The fact that the characteristic of the high section of the information detection signal is normal means that the length, position, etc. of the high section is normal, and that there is no obstacle in generating a synchronization signal based on the information detection signal. This sync signal informs another device of a certain period of time during which information can be read.

The window signal generator 123 generates a window signal covering an error range of the information detection signal based on the synchronous clock signal. SUMMARY OF THE INVENTION An object of the present invention is to correct a case where an information detection signal is distorted due to various reasons, that is, even when the position of the high section of the information detection signal is shaken or the length of the high section of the information detection signal is changed, thereby maintaining a constant synchronization signal. To generate. Therefore, a window signal covering the error range of such information detection signal is needed. Since the window signal should be normally output even when the characteristic of the information detection signal is abnormal, the window signal is generated based on the synchronous clock signal which is constantly output based on the information detection signal of the normal time.

When the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is normal, the synchronization signal generator 124 generates a synchronization signal based on the information detection signal at the normal time, and the information detection signal and the window. When the phase difference of the signal is within the error range and the extracted characteristic is abnormal, the synchronization signal is generated based on the synchronization clock signal. Here, the error range refers to a range in which the input signal may be distorted due to the influence of the surroundings. If the input signal exceeds an error range over a predetermined interval, the signal is no longer input or a heterogeneous signal is newly input. Must see Since the phase difference between the information detection signal and the window signal is within the error range and the normal information detection signal is output when the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal. When the phase difference between the information detection signal and the window signal is within the error range and the extracted characteristic is abnormal, the abnormal information detection signal is output. Therefore, the synchronization signal is generated based on the synchronization clock signal generated based on the conventional information detection signal. Create

The basic synchronous clock signal generator 125 generates a basic synchronous clock signal having a constant frequency at all times by using a crystal oscillator or the like.

The signal reliability value counter 126 counts the signal reliability value every time a phase difference between the information detection signal and the window signal is not within the error range. Here, the signal reliability value is a value for an interval in which a signal that cannot be seen as the original signal is continuously input. When the signal reliability value is exceeded, the signal is no longer inputted or heterogeneous. It should be regarded as a case where the signal of is newly input.

The sync signal generator 124 generates a sync signal based on the sync clock signal when the count of the signal reliability value counter is not finished, and generates a basic sync clock signal when the count of the signal reliability value counter ends. A sync signal is generated as a reference. At the time when the count of the signal reliability value counter is not finished, the signal is no longer input or a heterogeneous signal is newly input. Therefore, the synchronization clock signal generated based on the previous information detection signal is used. Generate a sync signal. When the count at the signal reliability value counter ends, the signal is no longer input or a heterogeneous signal is newly input. The synchronization signal is generated based on the basic synchronization clock signal having a constant frequency at all times. Thereafter, when the information detection signal for the heterogeneous signal is generated, a synchronization signal of a new frequency is generated based on this.

2 is a block diagram of an MSK synchronization signal compensation apparatus according to an embodiment of the present invention.

3 is a waveform diagram of various signals used in the process of generating the MSK detection signal of the present invention.

4A and 4B are waveform diagrams of various signals used in the process of generating the MSK synchronization signal of the present invention.

Referring to FIG. 2, the MSK synchronization signal compensation device includes an MSK detection unit 21 and an MSK synchronization signal compensation / generation unit 22.

The MSK detection unit 21 detects an information recording section with respect to the MSK signal, and generates an MSK detection signal in which the detected information recording section is set as a high section. Here, the MSK (Minimum Shift Keying) signal is a kind of Continuous Phase Frequency Shift Keying (CPFSK) signal, so that the phase after one symbol time with respect to the phase at the present time becomes a leading or delay of ± 90 °. If two carriers f1 and f0 are selected, both codes become orthogonal and ideally demodulate, and the minimum frequency difference at which this orthogonality is established, that is, 2 (f1-f0) T = 1 (T: signal time) The signal which selected the carrier so that this may be established. Referring to FIG. 3, the analog MSK signal is represented by a waveform of cos {2πx ({f} _ {wob}) xt} in a section where no information is recorded, but cos {2πx (1.5 x {in a section where information is recorded. f} _ {wob}) xt},-cos {2πx ({f} _ {wob}) xt}, cos {2πx (1.5 x {f} _ {wob}) xt}. That is, in the case of the analog MSK signal, the frequency is 1.5 times at the start and end of the section in which the information is recorded.

Referring to FIG. 2, the MSK detector includes an analog-digital converter 211, a phase locked loop circuit 212, a phase locked clock delay unit 213, and an MSK detection signal generator 214.

The analog to digital converter 211 converts an analog MSK signal into a digital MSK signal. In the case of digital modulation such as MSK, since the digital signal is converted into an analog signal, the demodulation step must convert the analog signal into a digital signal. As shown in Fig. 2, the analog MSK signal is converted to a digital signal by setting only a specific value or more high. At this time, an analog signal is converted into a digital signal using a limiter or the like.

Phase locked loop circuit 212 generates a phase locked clock signal having a frequency equal to the fundamental frequency of the digital MSK signal. Referring to FIG. 3, the fundamental frequency of the digital MSK signal is 2πx ({f} _ {wob}) according to cos {2πx ({f} _ {wob}) xt}, and is a phase locked clock having the same frequency as this. Generate a signal.

The phase locked clock delay unit 213 delays the phase locked clock signal by a predetermined time. Referring to FIG. 3, since the digital MSK signal and the phase locked clock signal have almost the same time point on the rising edge and the falling edge, it is inconvenient to compare both signals. To eliminate this inconvenience, the phase locked clock delay section 213 delays the phase locked clock signal by a predetermined time as shown in FIG.

The MSK detection signal generator 214 rises when the phase locked clock signal delayed in the high period of the digital MSK signal rises, and the signal of the phase locked clock delayed in the low period after the high period of the digital MSK signal rises. At that point, the falling MSK detection signal is generated. As a result of delaying the phase locked clock, as shown in Fig. 3, the rising edge of the delayed phase locked clock signal occurs in the low period of the digital MSK signal at the time when information is not recorded, i.e., unmodulated. Therefore, if the rising edge of the delayed phase locked clock signal occurs in the high section of the digital MSK signal, it can be seen that the point in time is the section in which the information is recorded. Thereafter, if the rising edge of the delayed phase locked clock signal occurs again in the low section of the digital MSK signal, it can be seen that the section in which the information is recorded is finished. Referring to FIG. 3, the MSK detection signal corresponds to a one-to-one correspondence with the information recording section. The MSK detection signal is a low section after the high section of the digital MSK signal from the time when the delayed phase locked clock signal rises in the high section of the digital MSK signal. One high period is made until the signal of the delayed phase locked clock rises within the circuit. In the absence of external interference, as shown in FIG. 3, the length of the high section of the MSK detection signal is 2T. Here, T refers to one period of the unmodulated MSK signal, that is, one period of the phase locked clock signal.

The MSK synchronization signal compensation / generating unit 22 extracts the length of the high section of the MSK detection signal, generates the MSK window signal based on the MSK detection signal at the extracted time point, and the high section of the MSK detection signal. When the extracted length is within the high period of the MSK window signal and the extracted length is normal, the MSK synchronization signal is generated based on the MSK detection signal at the normal time point, and the high period of the MSK detection signal is within the high period of the MSK window signal. When the extracted characteristic is abnormal, the MSK synchronization signal having a constant high length is generated based on the MSK detection signal at the normal time immediately before the abnormal time. In a disk medium such as an optical disk, spiral grooves are formed for tracking. In addition, in order to record the address information, the wobbling is wobbling at regular intervals in correspondence with the address information. At this time, the recording of the address information is implemented by MSK modulating a carrier wave corresponding to the address information. Here, the synchronization signal is a signal having the same period as the period in which the address information is recorded, and is a signal for improving the reliability of the MSK demodulation by enabling demodulation at the same timing as the modulation timing of the modulating side. Therefore, the synchronization signal should be output stably even if there is external interference.

The MSK sync signal compensator / generator 22 includes an MSK length extractor 221, an MSK sync clock signal generator 222, a SK window signal generator 223, an MSK sync signal generator 224, and a basic MSK sync. And a clock generator 225 and an MSK reliability value counter 226.

The MSK length extractor 221 extracts the length of the high section of the MSK detection signal. 4A and 4B, the length of the high section of the MSK detection signal may be 1T, 2T, 3T, or the like.

The MSK synchronous clock signal generator 222 generates an MSK synchronous clock signal rising after the falling edge of the high period of the MSK detection signal at the extracted length. In the case of Fig. 4A, the normal MSK signal is continuously input, where the length of the high section of the MSK detection signal is 2T. The MSK synchronous clock signal is generated based on the MSK detection signal at this point. That is, the MSK synchronous clock signal rises at a certain point (the time of the next rising edge of the MSK detection signal) after the falling edge of the high section of the MSK detection signal, and falls after a certain time. The MSK synchronous clock signal generator 222 may be implemented as a counter that is reset whenever an MSK detection signal having a high interval of 2T is generated.

The MSK window signal generation unit 223 rises after the falling edge of the high section of the MSK synchronization clock signal and generates an MSK window signal having a high section having a length longer than the extracted length. Since the MSK window signal is a reference signal for determining whether the MSK detection signal is valid, the MSK window signal is generated based on the MSK synchronization clock signal generated based on a normal MSK detection time signal. That is, the MSK window signal rises after the falling edge of the high section of the MSK sync clock signal and falls after the high section of the length longer than the extracted length. Since the MSK window signal should be determined to be valid both when the length of the high section of the MSK detection signal is 1T and 3T or when the relative position of the MSK detection signal is shaken, as shown in FIGS. 4A and 4B, the high section The length of Rx becomes a multiple of the length of the high section of the MSK detection signal, and the time of occurrence of the high section rises before the rising edge of the MSK detection signal and falls after the falling edge of the MSK detection signal.

The MSK synchronization signal generation unit 224 has an MSK synchronization that rises after the falling edge of the high period of the MSK detection signal at the normal time when the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted length is normal. Generates a signal, and generates an MSK synchronization signal rising after the falling edge of the high period of the MSK synchronization clock signal at an abnormal time when the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted length is abnormal. . The fact that the high section of the MSK detection signal is within the high section of the MSK window signal means that the MSK signal is continuously input. However, when the MSK signal is distorted due to various non-ideal factors, the lengths of the high intervals of the MSK detection signal are 1T and 3T. However, when the length of the high section of the MSK detection signal is 4T or more, it is determined that a heterogeneous signal is input, and the high section of the MSK detection signal is outside the high section of the MSK window signal. In the case of FIG. 4A, when a normal MSK signal is continuously input, the length of the high section of the MSK detection signal is 2T, and as shown in FIG. 4A, the MSK synchronization signal is the high section of the MSK detection signal. Raise after the falling edge. In the case of FIG. 4B, a normal MSK signal is input and an abnormal MSK signal is input. At this time, the length of the high section of the MSK detection signal is 2T. As shown in FIG. 4A, the MSK synchronization signal is the MSK synchronization clock. Rising after the falling edge of the high section of the signal. Since the MSK synchronization clock signal is the same signal as the MSK detection signal when a normal MSK signal is input, the synchronization signal is constantly output regardless of whether or not the MSK signal is distorted.

The basic MSK synchronous clock generator 225 generates a basic MSK synchronous clock having a constant frequency by using a crystal oscillator or the like.

The MSK reliability value counter 226 counts the MSK reliability values at certain points in time when the high section of the MSK detection signal is not within the high section of the MSK window signal. Here, the MSK reliability value is a value for an interval in which a signal that cannot be seen as an MSK signal is continuously input. When the MSK reliability value is exceeded, the MSK signal is no longer inputted or heterogeneous. It should be regarded as a case where the signal of is newly input.

The MSK sync signal generator 224 generates an MSK sync signal rising after the falling edge of the high section of the MSK sync clock signal when the count of the MSK reliability value counter is not finished, and the count in the MSK reliability value counter is increased. At the end, the MSK sync signal is generated rising after the rising edge of the high period of the basic MSK sync clock. Since the MSK signal is still accepted at the time when the count of the MSK reliability value counter is not finished, the MSK sync signal is generated rising after the falling edge of the high period of the MSK sync clock signal. As the MSK signal is no longer input or a heterogeneous signal is newly input at the end of the count at the MSK reliability value counter, it always rises after the rising edge of the high section of the basic MSK synchronization clock with a constant frequency. Generates an MSK synchronization signal. Thereafter, when the information detection signal for the heterogeneous signal is generated, a synchronization signal of a new frequency is generated based on this.

5 is a flowchart illustrating a synchronization signal compensation method according to an embodiment of the present invention.

Referring to FIG. 5, the synchronization signal compensation method includes the following steps.

First, an information recording section is detected for a predetermined signal, and an information detection signal is generated in which the detected information recording section is a high section. In detail, first, an analog signal is converted into a digital signal (51). Next, a phase locked clock signal having a frequency equal to the fundamental frequency of the digital signal is generated (52). Next, the phase of the digital signal is compared with the phase of the phase locked clock signal to detect the information recording section with respect to the digital signal, and generate an information detection signal having the detected information recording section as the high section (53).

Then, the characteristic of the high section of the information detection signal is extracted, and the extracted characteristic generates a window signal based on the information detection signal at a normal time point, and the phase difference between the information detection signal and the window signal is within an error range and extracted When the characteristic is normal, the synchronization signal is generated based on the information detection signal at the normal time, and when the phase difference between the information detection signal and the window signal is within the error range and the extracted characteristic is abnormal, the synchronization signal is generated at the normal time immediately before the abnormal time. A synchronization signal having a constant high length is generated based on the information detection signal. In detail, first, characteristics of the high section of the information detection signal are extracted (54). Next, a synchronous clock signal is generated based on the information detection signal at the time when the extracted characteristic is normal (55). Subsequently, a window signal covering the error range of the information detection signal is generated 56 based on the synchronous clock signal. Subsequently, a basic synchronous clock signal having a constant frequency is generated (57). Subsequently, the phase difference between the information detection signal and the window signal is within an error range (58), at the time when the extracted characteristic is normal (581), and generates a synchronization signal based on the information detection signal at the normal time (5811), When the phase difference between the information detection signal and the window signal is within an error range (58), and when the extracted characteristic is abnormal (581), a synchronization signal is generated (5812) based on the synchronization clock signal.

Further, the signal reliability value is counted 558 at a certain point in time (582) where the phase difference between the information detection signal and the window signal is not within the error range. Next, when the count is not completed (583), a synchronous signal is generated based on the synchronous clock signal (5831), and when the count is finished (583), a synchronous signal is generated based on the basic synchronous clock signal. (5832).

6A and 6B are diagrams illustrating a MSK synchronization signal compensation method according to an embodiment of the present invention.

6A and 6B, the MSK synchronization signal compensation method includes the following steps.

First, an information recording section is detected for the MSK signal, and an MSK detection signal is generated in which the detected information recording section is set to a high section. In detail, the analog MSK signal is first converted into a digital MSK signal (61). Next, a phase locked clock signal having a frequency equal to the fundamental frequency of the digital MSK signal is generated (62). Next, the phase locked clock signal is delayed by a predetermined time (63). Then, the MSK detection rises when the delayed phase locked clock signal rises in the high period of the digital MSK signal, and falls when the delayed phase locked clock signal rises in the low period after the high period of the digital MSK signal. Generate a signal (64).

Subsequently, the length of the high section of the MSK detection signal is extracted, and the MSK window signal is generated based on the MSK detection signal at the extracted length, and the high section of the MSK detection signal is within the high section of the MSK window signal. When the extracted length is normal, the MSK synchronization signal is generated based on the MSK detection signal at the normal time, and when the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted characteristic is abnormal, The MSK synchronization signal having a constant high length is generated based on the MSK detection signal at a normal time point. In detail, first, the length of the high section of the MSK detection signal is extracted (65). Next, the extracted length generates an MSK sync clock signal rising after the falling edge of the high section of the MSK detection signal at the normal time (66). Next, it rises after the falling edge of the high section of the MSK sync clock signal and generates an MSK window signal having a high section of length longer than the extracted length (67). Next, generate a basic MSK sync clock with a constant frequency (68). Subsequently, the high period of the MSK detection signal is within the high period of the MSK window signal (69), and when the extracted length is normal (691), the MSK rising after the falling edge of the high period of the MSK detection signal at the normal time. A synchronization signal is generated, and the high section of the MSK detection signal is within the high section of the MSK window signal (69), and when the extracted length is abnormal (691), it rises after the falling edge of the high section of the MSK sync clock signal. An MSK synchronization signal is generated (6912).

Further, at a predetermined time point when the high section of the MSK detection signal is not within the high section of the MSK window signal (69), the MSK reliability value is counted (692). Next, when the count is not finished (693), an MSK synchronization signal rising after the falling edge of the high section of the MSK synchronization clock signal is generated (6931), and when the count ends (693), the basic MSK synchronization is performed. An MSK sync signal that rises after the rising edge of the high period of the clock is generated (6932).

Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed in a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium.

The computer-readable recording medium may include a magnetic storage medium (eg, ROM, floppy disk, hard disk, etc.), an optical reading medium (eg, CD-ROM, DVD, etc.) and a carrier wave (eg, the Internet). Storage medium).

So far, the present invention has been described with reference to preferred embodiments. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

According to the present invention, even when a certain modulated signal is distorted due to various non-ideal factors such as surrounding radio wave interference, the synchronous signal of the modulated signal is constantly output without distortion, so that it is possible to reliably demodulate. In particular, by correcting not only when the relative position of the MSK signal is shaken, but also when the length of the MSK signal is out of the normal length, it is possible to increase the reliability of the demodulated data when demodulating the MSK signal on an optical disc. .

Claims (21)

An information recording section detection section for detecting an information recording section with respect to a predetermined signal and generating an information detection signal having the detected information recording section as a high section; And Extracts a characteristic of a high section of the information detection signal, generates a window signal based on the information detection signal at a normal time point, and the phase difference between the information detection signal and the window signal is within an error range When the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal timing, and when the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is abnormal, And a synchronization signal compensation / generation unit configured to generate a synchronization signal having a constant high length based on the information detection signal at a normal time point immediately before the abnormal time point. The method of claim 1, wherein the information recording section detection unit An analog to digital converter for converting an analog signal into a digital signal; A phase locked loop circuit for generating a phase locked clock signal having a frequency equal to a fundamental frequency of the digital signal; And Generating an information detection signal by comparing the phase of the digital signal with the phase of the phase locked clock signal, detecting an information recording section with respect to the digital signal, and generating an information detection signal having the detected information recording section as a high section; Synchronization signal compensation device comprising a. The method of claim 1, wherein the sync signal compensation / generating unit An information detection signal characteristic extraction unit for extracting a characteristic of a high section of the information detection signal; A synchronous clock signal generator configured to generate a synchronous clock signal based on the information detection signal when the extracted characteristic is normal; A window signal generation unit generating a window signal covering an error range of the information detection signal based on the synchronous clock signal; And When the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal time point, and the synchronization of the information detection signal and the window signal is performed. And a synchronization signal generator for generating a synchronization signal based on the synchronization clock signal when a phase difference is within an error range and the extracted characteristic is abnormal. The method of claim 3, wherein the synchronization signal compensation / generation unit A basic synchronous clock signal generator for generating a basic synchronous clock signal having a constant frequency; And And a signal reliability value counter for counting a signal reliability value at a predetermined time point at which a phase difference between the information detection signal and the window signal is not within an error range. The synchronization signal generator of claim 4, wherein the synchronization signal generator generates a synchronization signal based on the synchronization clock signal when the count of the signal reliability value counter is not finished. And generating a synchronization signal based on the basic synchronization clock signal. An MSK detection unit for detecting an information recording section with respect to the MSK signal and generating an MSK detection signal having the detected information recording section as a high section; And Extracting the length of the high section of the MSK detection signal, generating the MSK window signal based on the MSK detection signal at the time when the extracted length is normal, the high section of the MSK detection signal is a high section of the MSK window signal The MSK synchronization signal is generated based on the MSK detection signal at the normal time when the extracted length is normal, and the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted characteristic is And an MSK synchronization signal compensation / generation unit for generating an MSK synchronization signal having a constant high section length based on the MSK detection signal at the normal time immediately before the abnormal time. The method of claim 6, wherein the MSK detection unit An analog to digital converter for converting an analog MSK signal into a digital MSK signal; A phase locked loop circuit for generating a phase locked clock signal having a frequency equal to a fundamental frequency of the digital MSK signal; A phase locked clock delay unit configured to delay the phase locked clock signal by a predetermined time; And It rises when the delayed phase locked clock signal rises in the high period of the digital MSK signal and falls when the signal of the delayed phase locked clock rises in the low period after the high period of the digital MSK signal. MSK detection signal generating unit for generating an MSK detection signal, characterized in that the MSK synchronization signal compensation device. The method of claim 6, wherein the MSK synchronization signal compensation / generation unit An MSK length extractor for extracting a length of a high section of the MSK detection signal; An MSK synchronous clock signal generator configured to generate an MSK synchronous clock signal rising after the falling edge of the high section of the MSK detection signal at the extracted length; An MSK window signal generator that rises after the falling edge of the high period of the MSK synchronization clock signal and generates an MSK window signal having a high period longer than the extracted length; And When the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted length is normal, generates an MSK synchronization signal rising after the falling edge of the high period of the MSK detection signal at the normal time point. Generating a MSK synchronization signal rising after the falling edge of the high period of the MSK synchronization clock signal at the abnormal time when the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted length is abnormal; MSK synchronization signal compensation device comprising a MSK synchronization signal generator. The method of claim 8, wherein the MSK sync signal compensation / generation unit A basic MSK synchronous clock generator for generating a basic MSK synchronous clock having a constant frequency; And And a MSK reliability value counter for counting MSK reliability values at certain points in time when a high section of the MSK detection signal is not within a high section of the MSK window signal. 10. The MSK synchronization signal generator of claim 9, wherein the MSK synchronization signal generation unit generates an MSK synchronization signal rising after a falling edge of a high period of the MSK synchronization clock signal when the count of the MSK reliability value counter is not completed. And an MSK synchronization signal rising after the rising edge of the high period of the basic MSK synchronization clock when the count at the value counter ends. (a) detecting an information recording section with respect to a predetermined signal and generating an information detection signal having the detected information recording section as a high section; And (b) extracting a characteristic of a high section of the information detection signal, generating a window signal based on the information detection signal at a time when the extracted characteristic is normal, and a phase difference between the information detection signal and the window signal is an error; When the extracted characteristic is within the range and the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal timing, and the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is abnormal. And generating a synchronization signal having a constant length of a high section based on the information detection signal at the normal viewpoint immediately before the abnormal viewpoint. The method of claim 11, wherein step (a) (a1) converting an analog signal into a digital signal; (a2) generating a phase locked clock signal having a frequency equal to the fundamental frequency of the digital signal; And (a3) comparing the phase of the digital signal with the phase of the phase locked clock signal to detect an information recording section with respect to the digital signal, and generating an information detection signal having the detected information recording section as a high section; Synchronization signal compensation method comprising a. The method of claim 11, wherein step (b) extracting a characteristic of a high section of the information detection signal; (b2) generating a synchronous clock signal based on the information detection signal at the time when the extracted characteristic is normal; (b3) generating a window signal covering an error range of the information detection signal based on the synchronous clock signal; And (b4) when the phase difference between the information detection signal and the window signal is within an error range and the extracted characteristic is normal, a synchronization signal is generated based on the information detection signal at the normal time, and the information detection signal and the And generating a synchronization signal based on the synchronization clock signal when the phase difference of the window signal is within an error range and the extracted characteristic is abnormal. The method of claim 13, wherein step (b) (b5) generating a basic synchronous clock signal having a constant frequency; And and (b6) counting a signal reliability value at a predetermined time point at which a phase difference between the information detection signal and the window signal is not within an error range. 15. The method of claim 14, wherein step (b4) generates a synchronization signal based on the synchronization clock signal when the count in step (b6) is not finished, and the count in step (b6) is completed. And a synchronization signal is generated based on the basic synchronization clock signal. (a) detecting an information recording section with respect to the MSK signal, and generating an MSK detection signal having the detected information recording section as a high section; And (b) extracting the length of the high section of the MSK detection signal, generating an MSK window signal based on the MSK detection signal at the time when the extracted length is normal, and the high section of the MSK detection signal is the MSK window signal. When the extracted length is normal and the extracted length is normal, the MSK synchronization signal is generated based on the MSK detection signal at the normal time, and the high period of the MSK detection signal is within the high period of the MSK window signal and the extraction is performed. And generating an MSK synchronization signal having a constant high length based on the MSK detection signal at the normal time immediately before the abnormal time. The method of claim 16, wherein step (a) (a1) converting an analog MSK signal into a digital MSK signal; (a2) generating a phase locked clock signal having a frequency equal to the fundamental frequency of the digital MSK signal; (a3) delaying the phase locked clock signal by a predetermined time; And (a4) When the delayed phase locked clock signal rises in the high period of the digital MSK signal, and rises, and when the delayed phase locked clock signal rises in the low period after the high period of the digital MSK signal. And generating a falling MSK detection signal at. The method of claim 16, wherein step (b) (b1) extracting a length of a high section of the MSK detection signal; (b2) generating an MSK synchronous clock signal rising after the falling edge of the high period of the MSK detection signal at the extracted length; (b3) generating an MSK window signal that rises after the falling edge of the high period of the MSK sync clock signal and has a high period longer than the extracted length; And (b4) When the high section of the MSK detection signal is within the high section of the MSK window signal and the extracted length is normal, the MSK synchronization signal rising after the falling edge of the high section of the MSK detection signal at the normal point in time is detected. Generating the MSK synchronization signal rising after the falling edge of the high period of the MSK synchronization clock signal when the high period of the MSK detection signal is within the high period of the MSK window signal and the extracted length is abnormal; MSK synchronization signal compensation method comprising a. 19. The method of claim 18, wherein step (b) (b5) generating a basic MSK sync clock having a constant frequency; And and (b6) counting the MSK reliability value at a predetermined time point when the high section of the MSK detection signal is not within the high section of the MSK window signal. 20. The MSK synchronization signal of claim 19, wherein the step (b4) generates an MSK synchronization signal rising after the falling edge of the high period of the MSK synchronization clock signal when the count in the step (b6) is not finished. and generating a MSK synchronization signal that rises after the rising edge of the high period of the basic MSK synchronization clock at the end of the count in step b6). A computer-readable recording medium having recorded thereon a program for executing the method of any one of claims 11 to 20 on a computer.