JP2003045028A - Synchronizing clock extracting method and data storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for producing a synchronizing clock synchronized with the rotation of a disk by accurately compensating the phase deviation due to the crosstalk from a wobble signal of an adjacent recording track. SOLUTION: A data storage device is provided with: a wobble signal extracting circuit 41 for reproducing the wobble component of a data recording track; a wobble clock extracting circuit 42 for extracting a wobble clock which is phase-locked with a wobble signal obtained with the wobble signal extracting circuit and has small jitters; a prepit detector 5 for extracting the timing of the prepit recorded on a recording disk; and a phase difference detecting circuit for outputting a phase correction signal by comparing the phase difference between the wobble clock and a prepit detecting signal obtained by the prepit detector. The method for producing the synchronizing clock to obtain a clock synchronized with the rotation of the recording disk is provided by correcting the phase of the wobble clock on the basis of the aforementioned correction signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock extraction method for extracting a clock synchronized with a fluctuation in the rotation of a disc in a data recording apparatus for recording data on a recordable disc using a recording clock.

[0002]

2. Description of the Related Art As an example of a recordable optical disc, a DV
D-R (Digital Versatile Disc-Recordable) and DV
D-RW (Digital Versatile Disc-Rewritable) is known. On these recording disks, recording tracks are engraved with a slight wobble at a predetermined frequency (140 kHz).

Although the rotational speed of the recording disk is controlled so that the linear velocity is substantially constant, when the disk center and the rotation axis of the spindle motor do not coincide, the linear velocity of the disk at the head position fluctuates. Resulting in.

Therefore, when recording is continued at a constant data recording speed, a recording mark will be formed at a position deviated from a desired position on the disk due to a change in linear velocity.

At the time of data recording, the wobble phase of the recording track is detected and a clock synchronized with this is generated to control the data recording speed.

As a result, the expected recording mark can be formed at a predetermined position on the disk even when the rotational speed of the disk fluctuates.

The conventional synchronous clock extraction method and the function of each block in the data recording device will be described below with reference to the block diagram of the data recording device shown in FIG.

The wobble signal from the recording track is focused by the head 2 onto the recording track of the recording disk 1 and irradiated with the light beam, and the reflected light is received by a photodetector (not shown) which is divided into two parallel to the recording track. It is obtained by taking the difference of the current output obtained from each detector in the regenerative amplifier 3.

However, the signal output from the regenerative amplifier is, in addition to a sine-wave signal having a wobble frequency component,
The composite signal includes frequency components other than the wobble frequency due to the influence of recording marks and prepits formed on the recording disk.

Components other than the wobble frequency act as disturbance for the wobble phase extraction of the recording track. The wobble signal extractor removes the influence of the recording marks formed on the recording disk and the fluctuation of the low frequency component from the composite signal Sr output by the reproduction amplifier, and extracts the wobble signal component at a predetermined wobble frequency. Is passed through a band pass filter (not shown) having a pass band and binarized by a comparator (not shown) having an intermediate value of the amplitude of the wobble signal component at a slice level, and a signal Sw mainly having a wobble frequency component is output.

In the wobble clock extraction circuit 42, the PL
A wobble clock with less jitter is extracted from the wobble signal by using a circuit such as an L (Phase Locked Loop) synchronization circuit that can obtain a clock with high frequency stability by absorbing a phase variation due to noise.

Even when the signal passes through the bandpass filter, the wobble signal has a pulse waveform due to prepits and a residual high frequency component due to a recording mark.

By using the PLL, it is possible to obtain the wobble clock Sc that minimizes the jitter of the clock used for data recording and that follows the fluctuation of the linear velocity of the disk.

The recording clock is obtained by multiplying the wobble clock by the multiplication circuit 7 to the recording channel bit rate.

Due to the prepits formed on the recording disk, a pulse-shaped prepit waveform is superimposed on the composite signal output from the reproducing amplifier 3.

The pre-pit detector 5 detects the period in which pre-pits exist by using a comparator (not shown) whose slice level is a predetermined reference value larger than the amplitude of a sinusoidal wobble signal included in the composite signal, and detects the pulse-like state. The pre-pit detection signal Sp is output.

The prepit decoder 6 outputs address data indicating the position of the light beam focused on the recording track by the head 2 by decoding the prepit signal. The recording data fetched from the host system (not shown) by the interface circuit 8 is temporarily stored in the recording data control circuit 9.

When the recording data control circuit detects that the recording start position has been reached by the address data obtained by the pre-pit decoder, it sends the accumulated recording data to the recording circuit 10. In the recording circuit, data is taken from the recording data control circuit according to the recording clock, the amount of light emitted from the head is modulated, and marks are formed on the recording disk 1.

FIG. 6 shows waveforms at various portions of the circuit having the configuration of FIG.

In the wobble signal Sr extracted from the composite signal Sr by binarization, the vicinity of the rising or falling of the wobble signal Sr is likely to be uncertain due to the influence of the pre-pit waveform or the recording mark superimposed on the composite signal.

The wobble clock extraction circuit can extract the phase-synchronized wobble clock Sc from such a signal by using a PLL in which the compression rate of the phase error is set sufficiently high.

In the DVD-R and DVD-RW, a part of the focused beam applied to the recording track impinges on the adjacent recording track, which causes crosstalk due to the wobble signal of the adjacent track.

Amplitude fluctuations and phase fluctuations occur in the wobble signal due to crosstalk, but the effect of the phase fluctuations particularly affects the generation of the recording clock.

The crosstalk from the wobble signal of the adjacent track cannot be removed by the bandpass filter because the frequency is almost the same as that of the wobble signal of the track to be recorded.

Further, in the wobble clock extraction circuit, if the frequency tracking performance capable of absorbing the linear velocity fluctuation due to the eccentricity of the recording disk is secured, the wobble phase fluctuation due to the crosstalk will also be tracked.

Therefore, when the recording clock is extracted by using the wobble signal affected by the crosstalk, it is impossible to form the recording mark accurately synchronized with the rotation of the disc.

As means for solving this, Japanese Patent Laid-Open No. 10-
In 293926, the phase of the recording clock is adjusted based on the phase adjustment signal obtained by comparing the phase of the wobble signal detected by the wobble signal extractor and the prepit detection signal output by the prepit detector. An example is shown.

The configuration and operation will be described below with reference to FIG.

The reproduction amplifier 3 outputs a composite signal Sr in which pulsed pre-pit waveforms and recorded data are superimposed, as in the example of FIG.

The same applies to the wobble signal extraction circuit which binarizes the composite signal and outputs the wobble signal Sw.

In the phase difference detection circuit 43, the wobble signal S
The phase of w is compared with the phase of the pre-pit detection signal Sp to detect the phase shift amount of the wobble signal and output it as a phase adjustment signal.

The phase circuit 44 corrects the phase of the wobble clock output from the wobble clock extraction circuit 42 according to the phase adjustment signal, and then outputs it.

By this phase correction, even when the phase fluctuation of the wobble frequency component is caused by the crosstalk from the wobble signal of the adjacent track, the phase of the wobble clock is corrected based on the timing of the prepit detection signal, and the phase is corrected. It eliminates the effects of fluctuations.

[0034]

In the wobble signal Sw, rising and falling timings are uncertain due to the influence of prepits and recording marks formed on the disc, and jitter and whisker-like pulses exist. ing.

When it is attempted to detect the phase difference by using the wobble signal containing a lot of jitter and the pre-pit detection signal as in the conventional example shown in FIG. 7, it is possible to obtain an accurate result due to the influence of the jitter contained in the wobble signal. It is difficult to know the reference phase, and an error due to jitter is also superimposed on the obtained phase adjustment signal.

Since the error superimposed on the phase adjustment signal is used for the phase amount control by the phase circuit 44, the influence of the variation remains on the phase of the correction clock Ss output from the phase circuit.

As a result, there is a problem in that the crosstalk due to the wobble signal of the adjacent track cannot be accurately canceled.

Further, if the phase of the correction clock varies, the variation of the recording clock obtained by multiplying the phase also remains, and it is difficult to secure sufficient recording performance.

An object of the present invention is to provide a method for accurately compensating for a phase shift due to crosstalk from a wobble signal of an adjacent recording track and generating a synchronous clock synchronized with the rotation of a disk.

[0040]

According to a first aspect of the present invention, there is a data recording track wobbled with a wobble signal having a predetermined frequency component, and has a predetermined phase relationship with the wobble signal. A wobble signal extracting step of reproducing a wobble component of the data recording track in a data storage device for recording data on a recording disk having prepits formed thereon based on a recording clock phase-synchronized with the wobble signal; PL from the wobble signal obtained by the extraction step
Based on a wobble clock extraction step for extracting a wobble clock phase-locked by L, a phase shift step for adjusting and outputting the phase of the wobble clock, and a phase-adjusted correction clock output from the phase shift step. The step of generating a recording clock synchronized with the correction clock, the pre-pit detecting step of extracting the timing of the pre-pit, and the phase difference between the wobble clock and the pre-pit detecting signal obtained by the pre-pit detecting step are compared to determine the phase. A phase difference detection step of outputting a correction signal; a step of controlling the phase amount of the phase shift step by the phase correction signal obtained in the phase difference detection step; and a wobble synchronized with the rotation of the recording disk by the step. To get the clock, Synchronous clock extraction method characterized by obtaining is provided.

According to a second aspect of the present invention, recording having a data recording track wobbled with a wobble signal having a predetermined frequency component, and pre-pits having a predetermined phase relationship with the wobble signal are formed. In a data storage device for recording data on a disc for recording based on a recording clock phase-synchronized with the wobble signal, a wobble signal extracting step for reproducing a wobble component of the data recording track and a wobble signal extracting step are obtained. A delay step of delaying and outputting a wobble signal, a wobble clock extraction step of extracting a wobble clock phase-locked by a PLL from the output signal of the delay step, and a recording clock synchronized with the wobble clock based on the wobble clock. To generate The pre-pit detection step of extracting the timing of the pre-pit, the phase difference detection step of comparing the phase difference between the wobble clock and the pre-pit detection signal obtained by the pre-pit detection step, and outputting a phase correction signal, and the delay step. By the step of correcting the delay amount of the phase correction signal obtained by the phase difference detecting step, and the step,
And a step of obtaining a wobble clock that is synchronized with the rotation of the recording disk, the synchronization clock extracting method being provided.

According to a third aspect of the present invention, recording having a data recording track wobbled with a wobble signal having a predetermined frequency component, and pre-pits having a predetermined phase relationship with the wobble signal are formed. In a data storage device for recording data on a disc for recording based on a recording clock phase-synchronized with the wobble signal, a wobble signal extracting step for reproducing a wobble component of the data recording track and a wobble signal extracting step are obtained. A wobble clock extraction step of extracting a wobble clock from a wobble signal by a PLL, a step of generating a recording clock synchronized with the wobble clock based on the wobble clock, and a phase shift for adjusting and outputting the phase of the wobble clock. Steps and the pre-pit A prepit detection step of extracting timing, a phase difference detection step of comparing the phase difference between the wobble clock and the prepit detection signal obtained by the prepit detection step, and outputting a phase correction signal, and a phase of the phase shift step. In the step of correcting the amount by the phase correction signal obtained in the phase difference detecting step and the step of extracting the wobble clock, the PLL operation is performed so that the phases of the wobble signal and the output signal of the phase shift step match. There is provided a method for extracting a synchronous clock, comprising: a step and a step of obtaining a wobble clock synchronized with the rotation of the recording disk by the step.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION To clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows the configuration of a data recording apparatus using the synchronous clock extraction method according to the first embodiment of the present invention.

In the head 2, similarly to the example shown in the prior art, the reflected light by the focused beam applied to the recording disk 1 is received by a photodetector (not shown).

The reproduction amplifier 3 outputs a composite signal in which, in addition to the wobble frequency component, a pulse-shaped signal due to prepits and a high-frequency component due to the recorded data are superposed by the output current obtained from the photodetector.

The wobble signal extraction circuit 41 outputs a binary wobble signal mainly having a wobble frequency component based on the composite signal obtained by the regenerative amplifier 3.

Further, in the wobble clock extraction circuit 42, the PLL circuit extracts and outputs the wobble clock with less jitter.

Since the linear velocity fluctuation due to the eccentricity of the recording disk is followed, the response characteristic of the wobble clock extraction circuit is
The wobble clock is set to follow the frequency fluctuation corresponding to the rotation speed of the recording disk.

On the other hand, the pre-pit detection circuit also detects the period in which pre-pits exist and outputs a pulse-like pre-pit detection signal as in the case of the prior art.

The phase difference detection circuit 43 compares the phase of the wobble clock extracted by the PLL with the timing of the pre-pit detection signal and outputs a phase correction signal.

The phase circuit 44 corrects the phase of the wobble clock based on the phase correction signal and outputs it. As a result, a stable synchronization clock synchronized with the prepit detection timing can be obtained.

The recording clock is obtained by multiplying the synchronous clock output from the phase circuit.

The data fetched from the host system (not shown) by the interface circuit 8 is written as a recording mark on the recording disk in synchronization with the recording clock via the recording data control circuit 9, the recording circuit 10 and the head 2. .

Next, the operation will be described with reference to FIG. 2 based on the output waveform of each part of the circuit. In the composite signal Sr output from the reproduction amplifier, a prepit waveform or the like is superimposed on a sinusoidal signal having a wobble frequency component as in the conventional circuit configuration.

In the wobble signal extraction circuit, the composite signal is passed through a bandpass filter to extract components other than the wobble frequency, and then binarized to generate the wobble signal Sw.
Is output. By narrowing the pass band of the band pass filter provided in the wobble signal extraction circuit, unnecessary frequency components superimposed on the composite signal due to the influence of recording marks etc. can be removed. The bad effect that it becomes difficult to follow occurs.

Therefore, it is desirable that the pass band of the band pass filter be wide.

The binarized wobble signal contains jitter and whisker-like pulses near the rising and falling edges due to the influence of unnecessary frequency components that cannot be completely removed by the bandpass filter. In the wobble clock extraction circuit, P
The LL circuit removes the jitter remaining near the rising and falling edges of the wobble signal and extracts and outputs the wobble clock that is phase-synchronized with the wobble signal.

A phase comparator (not shown) provided in the wobble clock extraction circuit compares the phases of the input wobble signal and the wobble clock, has a wobble frequency component included in the wobble signal, and averages the wobble signal. The wobble clock Sc having the same phase is output.

In the phase difference comparison circuit 43, not the wobble signal Sw including jitter but the wobble clock Sc that does not include jitter and is synchronized in phase by the wobble clock extraction circuit is compared with the phase shift between the pre-pit detector Sp. work.

The phase difference comparison circuit 43 detects how much the phase of the wobble clock deviates from the reference phase (for example, 90 degrees) with respect to the timing when the prepit is detected, and outputs a phase correction signal.

The phase correction signal is output by, for example, a counter using a fixed clock having a channel clock frequency.
It can be obtained by detecting how many counts the phase of the wobble clock deviates from the reference phase generated based on the pre-pit detection signal.

Further, in order to eliminate the influence of the timing variation included in the pre-pit detection signal, the phase difference detection circuit averages a plurality of pre-pit detection timings and then outputs the phase correction signal to obtain a higher accuracy. A high phase correction signal can be obtained.

The wobble clock that follows the frequency fluctuation corresponding to the number of revolutions of the recording disk also follows the phase fluctuation due to the crosstalk from the wobble signal of the adjacent track.

On the other hand, by adopting the synchronous clock extraction method of the configuration shown in FIG. 1 in which the phase correction is performed based on the prepit position obtained by the prepit detection signal, the phase fluctuation due to the crosstalk is canceled, A recording mark can be accurately formed at a desired position on the disc.
The configuration of a data recording device using a synchronous clock extraction method according to another embodiment of the present invention is shown in FIG.

The wobble signal extracted by the wobble signal extraction circuit 41 is input to the wobble clock extraction circuit 42 after being delayed by the delay circuit 45 for a designated time.

The phase difference detection circuit 43 detects the phase difference between the pre-pit detection signal and the wobble clock, and outputs the phase correction signal so as to increase or decrease the delay amount by the delay circuit 45 for the time corresponding to the detected phase difference. Output. This makes it possible to obtain the same phase correction effect as the method according to the first embodiment.

When the configuration of FIG. 2 is adopted, the phase difference detection circuit 43 constitutes a feedback loop together with the delay circuit 45 and the wobble clock 42, so that the output phase of the wobble clock extraction circuit can be controlled more accurately. There is. FIG. 4 shows the configuration of a data recording device using the synchronous clock extraction method according to the third embodiment of the present invention.

The embodiment of FIG. 3 is an example in which the phase correction step of the synchronous clock by the phase circuit 45 is provided on the feedback loop of the PLL constituting the wobble clock extraction circuit 42.

The wobble signal obtained by the wobble signal extraction circuit 41 is supplied to the phase comparator 421 and LPF (Low-pas).
s Filter) 422, VCO (Voltage Controlled Osci)
wobble clock extraction circuit 42 that constitutes a PLL by the frequency divider 424, the frequency divider 424, and the phase circuit 45.
The wobble clock is extracted and output by.

The phase comparator compares the output signal phases of the wobble signal extraction circuit and the phase circuit and outputs the phase error to the LPF. The LPF outputs by limiting the band of the input signal so that it can follow the linear velocity fluctuation of the recording disk.

The VCO changes the oscillation frequency based on the input voltage and outputs it. In this embodiment, an example in which the oscillation frequency of the VCO matches the frequency of the recording channel has been shown.

The wobble clock is obtained by dividing the VCO output by the frequency dividing circuit 424. In this case, since the clock output from the VCO can be directly used as the recording clock, the wobble clock extraction circuit 4
There is no need to provide a frequency multiplier circuit outside the second unit.

The phase detection circuit 43 detects the phase difference between the wobble clock obtained as the output of the frequency dividing circuit and the output of the pre-pit detector, and outputs it as a phase correction signal.

The phase circuit delays the phase of the wobble clock based on the phase correction signal and supplies it to the phase comparator 421.

Since the wobble clock extraction circuit works to synchronize the wobble clock delayed by the phase circuit and the wobble signal given from the wobble signal extraction circuit, the phase shift of the wobble signal due to crosstalk is absorbed by the phase circuit. , It is possible to obtain a recording clock synchronized with the number of revolutions of the disc.

[0077]

The first effect of the present invention is to detect the phase difference from the pre-pit detection timing even if there is crosstalk from the wobble signal of the adjacent recording track,
By correcting the phase of the wobble clock, it is possible to accurately extract the synchronous clock synchronized with the rotation speed of the disk.

The second effect of the present invention is to compare the wobble clock extracted by the PLL synchronizing circuit with the prepit detection timing as compared with the case where the wobble signal and the prepit detection timing are used for detecting the phase difference. As a result, the influence of residual jitter superimposed on the wobble signal is reduced, and high phase difference detection accuracy can be realized.

The third effect of the present invention is that the phase amount of the wobble clock becomes stable, so that the jitter of the recording clock obtained by multiplying the wobble clock can be reduced and high recording performance can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data recording device using a clock extraction method according to a first embodiment of the present invention.

FIG. 2 is an operation diagram illustrating an operation of the clock extraction method according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a data recording device using a clock extraction method according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a data recording device using a clock extraction method according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a data recording device using a conventional clock extraction method.

FIG. 6 is an operation diagram illustrating an operation of a conventional clock extraction method.

FIG. 7 is a configuration diagram of a data recording device using a second conventional clock extraction method.

[Explanation of symbols]

1 ... Recording disc 2 ... Head 3 ... Regenerative amplifier 5 ... Pre-pit detector 6 ... Pre-pit decoder 7 ... Multiplier circuit 8 ... Interface circuit 9 ... Recording data control circuit 10 ... Recording circuit 41 ... Wobble signal extraction circuit 42 ... Wobble clock extraction circuit 43 ... Phase difference detection circuit 44 ... Phase circuit 45 ... Delay circuit 421 ... Phase comparator 422 ... LPF 423 ... VCO 424 ... Divider circuit

Claims (6)

[Claims] 1. A wobble signal on a recording disk having a data recording track wobbled with a wobble signal having a predetermined frequency component and having prepits having a predetermined phase relationship with the wobble signal, In a data storage device for recording data based on a synchronized recording clock, a wobble signal extracting step for reproducing a wobble component of the data recording track, and a wobble phase-locked by a PLL from a wobble signal obtained by the wobble signal extracting step. A wobble clock extraction step for extracting a clock, a phase shift step for adjusting and outputting the phase of the wobble clock, and a phase-adjusted correction clock output from the phase shift step for synchronizing with the correction clock The step of generating the recording clock. A prepit detection step of extracting the timing of the prepit, a phase difference detection step of outputting a phase correction signal by comparing the phase difference between the wobble clock and the prepit detection signal obtained by the prepit detection step, Controlling the phase amount of the phase shift step by the phase correction signal obtained in the phase difference detecting step; and obtaining a wobble clock synchronized with the rotation of the recording disk by the step. Synchronous clock extraction method. 2. A wobble signal having a data recording track wobbled with a wobble signal having a predetermined frequency component, and a phase of the wobble signal on a recording disk having prepits having a predetermined phase relationship with the wobble signal. In a data storage device for recording data based on a synchronized recording clock, a wobble signal extraction step for reproducing a wobble component of the data recording track, and a delay for delaying and outputting the wobble signal obtained by the wobble signal extraction step. A wobble clock extraction step of extracting a wobble clock phase-locked by a PLL from the output signal of the delay step; a step of generating a recording clock synchronized with the wobble clock based on the wobble clock; Thymin A pre-pit detection step for extracting the phase difference between the wobble clock and the pre-pit detection signal obtained by the pre-pit detection step, and a phase difference detection step for outputting a phase correction signal; and a delay amount for the delay step. A synchronous clock extraction method comprising: a step of correcting with a phase correction signal obtained in the phase difference detecting step; and a step of obtaining a wobble clock synchronized with the rotation of a recording disk by the step. 3. A wobble signal having a wobbling signal having a predetermined frequency component is provided on a recording disk having a data recording track wobbled with a prepit having a predetermined phase relationship with the wobble signal. In a data storage device for recording data based on a synchronized recording clock, a wobble signal extraction step for reproducing a wobble component of the data recording track, and a wobble clock extracted by a PLL from the wobble signal obtained by the wobble signal extraction step. A wobble clock extraction step, a step of generating a recording clock synchronized with the wobble clock based on the wobble clock, a phase shift step of adjusting and outputting the phase of the wobble clock, and a timing of the pre-pit extraction Sup A pit detection step, a phase difference detection step of comparing the phase difference between the wobble clock and the pre-pit detection signal obtained by the pre-pit detection step, and outputting a phase correction signal, and a phase amount of the phase shift step A step of correcting with the phase correction signal obtained in the phase difference detecting step; a step of causing a PLL operation in the wobble clock extraction step so that the wobble signal and the output signal of the phase shift step are in phase with each other; A step of obtaining a wobble clock synchronized with the rotation of the recording disk by the step; 4. A phase of the wobble signal on a recording disk having a data recording track wobbled with a wobble signal having a predetermined frequency component, and having a prepit having a predetermined phase relationship with the wobble signal. In a data storage device for recording data based on a synchronized recording clock, a wobble signal extracting means for reproducing a wobble component of the data recording track, and a wobble phase-locked by a PLL from a wobble signal obtained by the wobble signal extracting means. Wobble clock extraction means for extracting a clock, phase shift means for adjusting and outputting the phase of the wobble clock, and phase-adjusted correction clock output from the phase shift means for synchronization with the correction clock Means for generating a recording clock, and the pre-pit A pre-pit detection means for extracting a timing, by comparing the phase difference between the pre-pit detection signal obtained by the wobble clock and the pre-pit detection means,
Phase difference detection means for outputting a phase correction signal, means for controlling the phase amount of the phase shift means by the phase correction signal obtained by the phase difference detection means, and means for synchronizing the rotation of the recording disk A data storage device comprising: means for obtaining a wobble clock; and a synchronous clock extraction method characterized by: 5. The phase of the wobble signal on a recording disk having a data recording track wobbled with a wobble signal having a predetermined frequency component, and having a prepit having a predetermined phase relationship with the wobble signal. In a data storage device for recording data based on a synchronized recording clock, a wobble signal extracting means for reproducing a wobble component of the data recording track, and a delay for delaying and outputting the wobble signal obtained by the wobble signal extracting means. Means, wobble clock extraction means for extracting a wobble clock phase-locked by a PLL from the output signal of the delay means, means for generating a recording clock synchronized with the wobble clock based on the wobble clock, Pre-pit inspection to extract timing Means compares the phase difference between the pre-pit detection signal obtained by the wobble clock and the pre-pit detection means,
A phase difference detecting means for outputting a phase correction signal; a means for correcting the delay amount of the delay means by the phase correction signal obtained by the phase difference detecting means; and a wobble clock synchronized with the rotation of the recording disk by the means. And a synchronization clock extracting method characterized by: 6. A wobble signal having a predetermined frequency component, a data recording track wobbled by a wobble signal, and a wobble signal, the wobble signal of which has a predetermined phase relationship with the wobble signal. In a data storage device that records data based on a synchronized recording clock, a wobble signal extracting unit that reproduces a wobble component of the data recording track, and a wobble clock is extracted by a PLL from the wobble signal obtained by the wobble signal extracting unit. Wobble clock extracting means, means for generating a recording clock synchronized with the wobble clock based on the wobble clock, phase shifting means for adjusting and outputting the phase of the wobble clock, and extracting the timing of the pre-pit Pre-pit detection means for Comparing the phase difference between the wobble clock and the pre-pit detection signal obtained by the pre-pit detection means,
Phase difference detection means for outputting a phase correction signal; means for correcting the phase amount of the phase shift means by the phase correction signal obtained by the phase difference detection means; and the wobble clock extraction means for the wobble signal and the wobble signal A synchronous clock extraction method, characterized in that: means for performing a PLL operation so as to match the phase with the output signal of the phase shift means; means for obtaining a wobble clock synchronized with the rotation of the recording disk by the means; Data storage device.