KR20040085529A - Lower Electrode Structure of Capacitor Having Diffusion Barrier for ULSI Memory and Method for Forming Lower Electrode Structure of Capacitor and Capacitor - Google Patents

Abstract

PURPOSE: A structure of a bottom electrode of a capacitor for ULSI memory device having a diffusion barrier, a method for forming a bottom electrode of a capacitor, and a method for forming a capacitor are provided to prevent diffusion of oxygen and chrome by using the first and the second diffusion barriers. CONSTITUTION: A structure of a bottom electrode of a capacitor includes the first diffusion barrier. The first diffusion barrier is formed with a CrxTi1-xN layer(24) and TiN layer in order to prevent diffusion of oxygen and chrome to a polycrystalline silicon contact plug for connecting a pass transistor to a capacitor. The structure of the bottom electrode of the capacitor further includes the second diffusion barrier for preventing the diffusion of chrome from the CrxTi1-xN layer to a dielectric(26) through a Pt bottom electrode(25).

Description

Lower Electrode Structure of Capacitor Having Diffusion Barrier for ULSI Memory and Method for Forming Lower Electrode Structure of Capacitor and Capacitor}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a lower electrode structure of a capacitor for an ultra high density memory device having a diffusion barrier and a method of forming a lower electrode of a capacitor. In particular, a pass transistor and a capacitor are electrically connected in an ultra high density memory device using ferroelectric or high dielectric materials. In the case where the CrTiN thin film is provided as a diffusion barrier on the lower electrode connected to the lower electrode, the lower electrode structure of the ultra-high-density memory capacitor that the ferroelectric thin film, the lower electrode, and the silicon plug can have excellent physical and electrical properties even after a high temperature oxidation heat treatment process and the same It relates to a method of forming a lower electrode and a method of forming a capacitor.

The semiconductor memory device is classified into a volatile memory device which simultaneously loses information stored in the semiconductor memory device when the power supply is cut off and a nonvolatile memory device in which the information remains even when the power supply is cut off. With the interest of new high dielectric materials due to the increase in capacity of storage media, and the development of memory devices using them, the semiconductors with large dielectric constants or ferroelectric materials having large dielectric constants are applicable to volatile and nonvolatile memory devices. It is applied to memory devices.

Such high dielectric materials include titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and BST ((Ba _x , Sr) to replace low-k materials used in conventional volatile DRAM (DRAM). PZT (Pb (Zr _x , Ti _1-x ) O ₃ ) and SBT (SrBi ₂ Ta ₂ O) with high dielectric material of _1-x ) TiO ₃ ) and large dielectric constants used in nonvolatile memory devices as ferroelectrics ₉ ) and the like.

In general, Perovskite-type ferroelectric materials, including PZT (PbZr _x Ti _1-x O ₃ ), have been used in various devices because of their excellent piezoelectricity, superelectricity, and ferroelectricity.

Among these memory devices, non-volatile memory devices are indispensable to portable electronic devices. Especially, Ferroelectric Random Access Memory (FRAM), which stores information by using polarization characteristics of ferroelectrics, has a single power supply voltage than that of conventional flash memory devices. It has been developed as a next-generation high-capacity high-density nonvolatile memory device because it has advantages such as fast read / write speed, operation, and frequency.

The high dielectric memory device is similar to the conventional DRAM manufacturing process, and has a structure of 2T-2C (two capacitors in two transistors) or 1T-1C (one capacitor in one transistor) for high integration. In addition, there is an advantage that the density can be greatly improved by applying a Capacitor Over Bit-line (Capacitor On Bit-line) structure in the process design.

In this case, the capacitor should have a lower electrode connected to the source / drain of a pass transistor. In order to make such an electrical connection, a polycrystalline silicon (Poly-Si) or tungsten (W) contact is generally used. A plug is used, and a lower electrode is formed thereon, and a ferroelectric thin film and an upper electrode are formed thereon to manufacture a capacitor.

Hereinafter, with reference to FIG. 1, the ultra-high density memory device of the conventional COB structure will be described in detail.

Referring to FIG. 1, in the ultra-high density storage device, the COB structure is formed by the drain 4 of the pass transistor T after the well-known transistor forming process of forming the pass transistor T of the MOS structure on the silicon substrate 1. A polycrystalline silicon contact plug 5 connecting the capacitor C is formed. Then, in order to reduce contact resistance with the polycrystalline silicon contact plug 5, titanium silicide (TiSi _x ) (6) formed by rapid heat treatment of a nitrogen atmosphere, an anti-determination film (7), a lower electrode (8) of the capacitor, and a dielectric layer (9) ), The capacitor C is formed in the order of the upper electrode 10, and finally, the interlayer insulating layer 11 is formed.

In the pass transistor T disposed under the substrate 1, the gate 2 and the source region 4b are connected to the word line and the bit line 3, and the drain region 4a is connected to the capacitor C. It serves to control the operation of the capacitor (C).

In particular, in the case of the dielectric layer 9 formed on the lower electrode 8 of the capacitor C, in the case of the high dielectric or ferroelectric thin film layer, the thin film deposited in the high temperature oxidation atmosphere after the deposition process or the deposition process in order to obtain better thin film characteristics. Heat treatment process to crystallize should be carried out.

However, when the high temperature oxidation process is performed, the contact resistance is increased between the polycrystalline silicon contact plug 5 and the Pt lower electrode 8 for the connection with the transistor T due to the interfacial reaction product, or the temperature is increased. The formation of an undesired non-conducting oxide film between the lower electrode 8 and the polycrystalline silicon contact plug 5 due to the diffusion of oxygen or silicon or the like causes the ultimate high dielectric properties not to be obtained. Therefore, in order to suppress such a phenomenon, it is required to form a diffusion barrier between the contact plug 5 and the lower electrode 8 to prevent the deterioration of the contact plug 5 and the deterioration of the characteristics of the lower electrode 8.

As the conventional diffusion barrier 7, a conductive oxide film and a nitride barrier are used. The conductive oxide film includes an iridium oxide film (IrO ₂ ), a ruthenium oxide film (RuO ₂ ), a rhodium oxide film (RhO _x ), etc., while having the advantage of simultaneously serving as a lower electrode of the capacitor and a diffusion barrier, As the temperature increases, the surface roughness increases considerably, and in the case of the iridium oxide film, there is a problem that etching is difficult.

In addition, as the nitride preventing film, a titanium nitride film (TiN), a tantalum nitride film (TaN), a titanium aluminum nitride film (TiAlN; see US Patent No. 5,856,704), a titanium chromium nitride film (TiCrN; see Korean Patent Publication No. 2000-15240) Is being used.

Titanium nitride film (TiN) having good conductivity is used as the most common diffusion barrier film, but at a high temperature heat treatment of 600 ° C. or more, titanium nitride film (TiN) forms an oxide of titanium (Ti) and loses conductivity, and titanium aluminum nitride film (TiAlN) is used. Or titanium chromium nitride film (TiCrN) shows improved stability at high temperature compared with titanium nitride film (TiN), but is unsuitable as a diffusion barrier due to a reaction problem with silicon (Si) and is a substantial semiconductor device integration process. There is a problem that the application is impossible in the heat treatment process for a long time at a high temperature applied to the phase.

Therefore, a diffusion barrier film 12 (structure shown on the right side of FIG. 1) having a composite structure of CrTiN / TiN utilizing only their advantages as a solution for solving these problems is proposed by the present inventors (Patent application 10 -2001-0058860).

As described above, various anti-conductive films have been proposed, but the conventional diffusion barrier films have a high electric resistance due to oxidation of the anti-oxidation film itself by oxygen diffusion and subsequent oxidation of polycrystalline silicon in a long-term high temperature heat treatment process of 600 ° C. or higher. The problem of loss of conductivity has made it difficult to apply to substantial high integration.

In addition, in the structure of Pt / CrTiN / TiN / Poly-Si in which the double structure diffusion barrier film 12 of CrTiN / TiN is inserted to solve the oxidation problem at a high temperature as in Patent Application 10-2001-0058860, the lower electrode ( Although diffusion of Cr into Pt (13) was not a problem, when the ferroelectric was deposited as the dielectric layer 14 on the lower electrode 13 and subjected to high-temperature oxygen heat treatment, Cr was formed as shown in FIGS. 2 and 3. It can be seen that it diffuses into the ferroelectric layer 14 such as PZT and SBT, deteriorates the properties of the ferroelectric and greatly deteriorates the leakage current characteristics.

As a result, as shown in the ferroelectric polarization characteristic graph of FIG. 4, the ferroelectric capacitor almost loses the ferroelectric characteristics after the high temperature heat treatment, and thus the ferroelectric capacitor cell is impossible to operate.

As described above, the development of various technologies for the anti-oxidation film is focused only on the development of technology for preventing the deterioration of characteristics by oxidation of the lower electrode system such as the silicon plug and the anti-oxidation film, and the prevention of the deterioration of the characteristics of the ferroelectric thin film is insufficient.

Accordingly, the present invention has been made in view of the problems of the prior art, and its purpose is to provide a CrTiN / TiN as a diffusion barrier under a lower electrode electrically connecting a pass transistor and a capacitor in an ultra-high density memory device using a ferroelectric or a high dielectric material. In the case of the thin film, the lower electrode structure of the ultra-high density storage capacitor and the lower electrode formation method of the capacitor having a diffusion barrier in which the ferroelectric thin film, the lower electrode, and the silicon plug have excellent physical properties and electrical properties even after the high temperature oxidation heat treatment process To provide.

Another object of the present invention is to prevent the diffusion of Cr into the dielectric during high temperature oxidation treatment by the addition of a simple pre-annealing process when the CrTiN / TiN thin film is provided as a diffusion barrier under the lower electrode of the capacitor. The present invention provides a lower electrode structure of an ultra high density memory capacitor having a diffusion barrier, and a method of forming a lower electrode of the capacitor using the same.

It is still another object of the present invention to provide a diffusion barrier between the lower electrode and the diffusion barrier in the case where the CrTiN / TiN thin film is provided as a diffusion barrier below the lower electrode of the capacitor. It is to provide a lower electrode structure of the ultra-high-density memory capacitor for preventing the damage, and a method of forming the lower electrode of the capacitor using the same.

1 is a cross-sectional view of a semiconductor memory device having a general COB structure;

FIG. 2 is a graph illustrating a change in concentration of an element after high temperature heat treatment of a dielectric material with a CrTiN / TiN diffusion barrier in FIG. 1 using an Auger spectrometer. FIG.

3 is a cross-sectional view of the structure of the ferroelectric capacitor after the high-temperature heat treatment when the diffusion barrier of CrTiN / TiN in Figure 1,

FIG. 4 is a graph showing polarization values according to electric fields of ferroelectric capacitors after high temperature heat treatment when CrTiN / TiN diffusion barriers are provided in FIG. 1;

5A to 5C are cross-sectional views of a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a first embodiment of the present invention;

6A through 6C are cross-sectional views illustrating a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a second embodiment of the present invention;

7A to 7C are cross-sectional views of a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a third embodiment of the present invention;

8A to 8C are cross-sectional views of a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a fourth embodiment of the present invention;

9 is a cross-sectional photograph of the structure of the capacitor after the heat treatment of the capacitor of Figure 8c,

10 is a cross-sectional view of a capacitor for an ultra-high density memory device having a diffusion barrier according to a preferred embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

21; Contact plug 22; Titanium Silicide Film

23; Titanium nitride film 24; Chromium Titanium Nitride

25,25a; Lower electrode 26; dielectric

27; Upper electrodes 28,29; Interlayer insulation layer

30,30a, 31; Chromium diffusion barrier films 30b and 30c; CrO ₂

C; Capacitor T; Pass transistor

In order to achieve the above object, according to the first aspect of the present invention, the present invention relates to oxygen and a polycrystalline silicon contact plug for electrically connecting a pass transistor and a capacitor using a ferroelectric or a high dielectric material in an ultra-high density memory device having a COB structure. In a lower electrode structure of a capacitor having a first diffusion barrier layer consisting of a chromium titanium nitride layer (Cr _x Ti _1-x N) / titanium nitride layer (TiN) to prevent diffusion of chromium, the first diffusion barrier layer is pre- The second diffusion barrier layer is formed between the chromium titanium nitride layer and the Pt lower electrode by annealing to prevent the diffusion of chromium from the chromium titanium nitride layer into the dielectric through the Pt lower electrode during the high temperature heat treatment of the ferroelectric or high dielectric. It provides a lower electrode structure of the capacitor, characterized in that provided.

According to a second aspect of the present invention, there is provided a lower electrode structure of a capacitor for electrically connecting a pass transistor and a capacitor located at an upper portion of the transistor by using a polycrystalline silicon contact plug, the contact of which is on top of the polycrystalline silicon contact plug. A titanium silicide film (TiSix) formed to reduce resistance and a chromium titanium nitride film (TiSix) formed on the titanium silicide film to prevent oxygen and chromium from diffusing into the polycrystalline silicon contact plug during high temperature heat treatment of the dielectric of the capacitor. A first diffusion barrier layer consisting of Cr _x Ti _1-x N) / titanium nitride layer (TiN) and a Pt lower electrode of the chromium titanium nitride layer and the capacitor are formed to lower the Pt portion from the chromium titanium nitride layer during the high temperature heat treatment of the dielectric. Chromium diffuses into the dielectric through the electrode It provides a lower electrode structure of the capacitor, characterized in that it is provided with a second diffusion prevention film for preventing.

In addition, the lower electrode structure of the capacitor may further include a third diffusion barrier layer formed on the second diffusion barrier layer to prevent chromium from being diffused from the chromium titanium nitride layer into the dielectric during the high temperature heat treatment of the dielectric. .

According to a third aspect of the invention, in the lower electrode structure of a capacitor for electrically connecting a pass transistor and a capacitor located above the transistor using a polycrystalline silicon contact plug, the capacitor is formed on the polycrystalline silicon contact plug. To prevent oxygen and chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor; and a first diffusion barrier layer made of chromium titanium nitride film (Cr _x Ti _1-x N) / titanium nitride film (TiN); And a Pt thin film layer formed on the chromium titanium nitride film of the first diffusion barrier layer and acting as a catalyst to form chromium in the heat treatment during the heat treatment, and a Pt thin film layer formed on the upper and lower surfaces of the Pt thin film layer by heat treatment of the Pt thin film layer. P from the chromium titanium nitride film during high temperature heat treatment of the dielectric It provides a lower electrode structure of the capacitor, characterized in that it comprises a second diffusion barrier for preventing the diffusion of chromium into the dielectric through the lower electrode.

The second diffusion barrier layer is formed of a CrO ₂ film, which is an oxide of chromium diffused from the chromium titanium nitride layer by pre-annealing the first diffusion barrier layer.

According to a fourth aspect of the present invention, there is provided a low electrode structure of a capacitor for electrically connecting a pass transistor and a capacitor located above the transistor using a polycrystalline silicon contact plug, wherein the high temperature heat treatment of the dielectric of the capacitor is performed. A first diffusion barrier film composed of a chromium titanium nitride film (Cr _x Ti _1-x N) / titanium nitride film (TiN) and a chromium of the first diffusion barrier to prevent oxygen and chromium from diffusing into the polycrystalline silicon contact plug in A second diffusion barrier layer formed on the titanium nitride layer to prevent chromium from diffusing from the chromium titanium nitride layer into the dielectric during the high temperature heat treatment of the dielectric; Between the second diffusion barrier layer and the Pt lower electrode of the capacitor It provides a lower electrode structure of the capacitor being configured to generate CrO ₂ film is.

The second diffusion barrier layer is made of any one of iridium (Ir), ruthenium (Ru), iridium oxide (IrO ₂ ), and ruthenium oxide (RuO ₂ ).

According to a fifth aspect of the present invention, the present invention provides a method for forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, wherein the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug is performed. A titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug, and a chromium titanium nitride film (Cr _x Ti _1-x N) for preventing oxygen from diffusing into the polycrystalline silicon contact plug on the titanium nitride film. ) And the CrO ₂ on the surface of the chromium titanium nitride film by pre-annealing to prevent chromium from being diffused from the chromium titanium nitride film to the dielectric material through the Pt lower electrode during the high temperature heat treatment of the dielectric. a method of forming a film, the Pt film ₂ CrO bottom before the top To provide a method of forming the capacitor lower electrode, characterized in that consisting of forming.

According to a sixth aspect of the present invention, the present invention provides a method for forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, wherein the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug is performed. A titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug, and a chromium titanium nitride film (Cr _x Ti _1-x N) for preventing oxygen from diffusing into the polycrystalline silicon contact plug on the titanium nitride film. ) And sequentially forming a Pt layer of a thin film formed on the chromium titanium nitride layer and acting as a catalyst to form chromium conductive oxide during pre-annealing, and pre-annealing the Pt layer. During the high temperature heat treatment of the dielectric on the upper and lower surfaces of the Pt thin film layer Forming a CrO ₂ film for preventing the diffusion of chromium from the chromium titanium nitride film into the dielectric through the Pt lower electrode, and forming a Pt lower electrode on the CrO ₂ film. Provided is an electrode forming method.

According to a seventh aspect of the present invention, there is provided a method of forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, wherein the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug is performed. A titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug, and a chromium titanium nitride film (Cr _x Ti _1-x N) for preventing oxygen from diffusing into the polycrystalline silicon contact plug on the titanium nitride film. ) To sequentially form, to form a Pt lower electrode on the chromium titanium nitride film, and to prevent the diffusion of chromium from the chromium titanium nitride film through the Pt lower electrode to the dielectric during the high temperature heat treatment of the dielectric. Pt lower electrode by pre-annealing the Pt lower electrode Provides a CrO ₂ forming the lower electrode of the capacitor, characterized in that consisting of a film forming method in the unit.

According to an eighth aspect of the present invention, there is provided a method for forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, wherein the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug is performed. A titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug, and a chromium titanium nitride film (Cr _x Ti _1-x N) for preventing oxygen from diffusing into the polycrystalline silicon contact plug on the titanium nitride film. ) And sequentially forming a Cr diffusion barrier layer on the chromium titanium nitride layer to prevent the diffusion of Cr from the chromium titanium nitride layer into the dielectric layer at a high temperature heat treatment of the dielectric layer. Forming a Pt lower electrode thereon; Provided is a method for forming a lower electrode of a capacitor, wherein a CrO ₂ film is formed under the Cr diffusion barrier layer by Cr diffused from the chromium titanium nitride layer during high temperature heat treatment of the dielectric.

And preferably the CrO ₂ film is formed to a 5 ~ 20nm thick, the dielectric material is _{TiO 2, Ta 2 O 5,} PZT (Pb, (Zr x, Ti 1-x) O 3), SBT (Sr x Bi y Ta ₂ O ₉ ), BST ((Ba _x , Sr _1-x ) TiO ₃ ), PLZT (Pb _1-y , La _y (Zr _x , Ti _1-x ) O ₃ ), BT (Bi ₄ Ti ₃ O ₁₂ ) And ST (SrTiO ₃ ).

As described above, in the present invention, a first diffusion barrier layer made of a CrTiN / TiN thin film to prevent oxygen diffusion to a polycrystalline silicon contact plug electrically connecting a pass transistor and a capacitor in an ultra-high density memory device using a ferroelectric or a high dielectric material. By providing a second diffusion prevention film that can prevent the diffusion of Cr from CrTiN to the dielectric, the ferroelectric thin film, the lower electrode, and the silicon plug can have excellent physical and electrical properties even after the high temperature oxidation heat treatment process.

(Example)

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

5A to 5C are cross-sectional views illustrating a bottom electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a first embodiment of the present invention.

The lower electrode structure of the capacitor according to the present invention first proceeds with the process of forming a metal oxide semiconductor (MOS) transistor serving as a pass transistor to form an ultra-high density memory device, and then to form a COB structure, which will be described later with reference to FIG. 10. As described above, the contact plug 21 is formed on the interlayer insulating layer 29 using polycrystalline silicon.

After the deposition of titanium to reduce the contact resistance of the polycrystalline silicon with the contact plug 21, and then rapidly heat treatment at 700 ℃ in a vacuum nitrogen atmosphere to form the titanium silicide 22 to 30 ~ 50nm thickness.

Subsequently, the titanium nitride film 23 and the chromium titanium nitride film 24 are respectively formed to have a thickness of 10 to 50 nm in double by reactive sputtering to form a double diffusion prevention film (FIG. 5A).

The double diffusion barrier formed of the titanium nitride layer 23 and the chromium titanium nitride layer 24 solves the problem of oxidation between the contact plug 21 of the polycrystalline silicon and the lower electrode as a barrier layer having excellent oxidation resistance even at a high temperature heat treatment process of 600 ° C. or higher. do.

Subsequently, a pre-annealing process is performed to form a diffusion barrier for preventing the diffusion of Cr from the chromium titanium nitride layer 24 among the double diffusion barrier layers as a capacitor, as shown in FIG. 5B. The Cr diffusion barrier layer 30 is formed on the surface thereof in a thickness of 5 to 20 nm, preferably about 10 nm.

In this case, the temperature of the heat treatment of the pre-annealing is carried out in the range of 300 ℃-800 ℃, the atmosphere during the heat treatment is carried out in a variety of atmospheres such as oxidizing atmosphere, reduced pressure atmosphere, atmospheric pressure, and nitrogen atmosphere and reducing atmosphere. Can be. The heat treatment equipment can be performed in general tubular furnace and Rapid Thermal Annealer (RTA). In the case of tubular furnace, heat treatment is performed for 5 minutes to 2 hours, and for rapid heat treatment, 10 seconds to 5 minutes. Heat treatment in between can be performed.

As described above, the pre-annealing condition of the present invention does not require strict conditions, and can be performed by any kind of well-known methods, and various conditions are determined because the temperature is determined by the combination of two variables of temperature and time. It is possible.

The pre-condition of the preferred annealing is, for example, rapid thermal annealing (RTA) method with 700 ℃, O ₂ in the atmosphere for about 2 minutes, or carried, temperature 550 ℃ ~850 in O ₂ or N ₂ atmosphere in a tubular (Furnace) It may be carried out between 30 minutes and 60 minutes in between the ℃ or 15 minutes to 60 minutes in the atmosphere (atmosphere).

After forming the Cr diffusion barrier layer 30 by the pre-annealing, the capacitor is formed by sequentially forming the lower electrode 25 of Pt, the dielectric 26 such as PZT, and the upper electrode 27 of Pt as shown in FIG. 5C. You are done.

After that, when the PZT thin film is deposited or subjected to a heat treatment process of crystallizing the thin film deposited in a high temperature oxidizing atmosphere, the Cr diffusion barrier layer 30 previously formed by pre-annealing is a ferroelectric material of Cr as a conductive oxide. Since it serves to prevent diffusion into the thin film in advance, it can have excellent ferroelectric properties.

6A to 6C are cross-sectional views illustrating a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a second embodiment of the present invention.

First, as in the first embodiment, a MOS transistor serving as a pass transistor is formed, and then a contact plug 21 and a titanium silicide 22 are formed to form a COB structure, and then the titanium nitride film 23 ) And a chromium titanium nitride film 24 is formed.

Then, in order to form a diffusion barrier for preventing the diffusion of Cr from the chromium titanium nitride film 24 to the capacitor in the second embodiment, a thin Pt of 10 nm or less, for example, on the top of the chromium titanium nitride film 24 as shown in FIG. The lower electrode 25a is deposited in advance. In this case, the thin Pt lower electrode 25a serves as a catalyst for inducing CrO ₂ , which is a conductive oxide, instead of Cr ₂ O ₃ , which is an insulator, during oxidation of Cr diffused from the chromium titanium nitride layer 24 during heat treatment. .

Then, if the heat treatment similar to the pre-annealing proceeds, as shown in Fig. 6b, by causing the diffusion of Cr through the interface of the Pt lower electrode 25a of the thin film in advance, the Cr diffusion prevention film having a thickness of 5 ~ 20nm through heat treatment 30a is formed on the surfaces of the chromium titanium nitride film 24 and the lower electrode 25a, respectively.

Subsequently, depositing a lower electrode Pt that is more stable in Cr diffusion to a thickness of 100 to 2000 yields a lower electrode structure of an ultra-high density storage capacitor having a diffusion barrier as shown in FIG. 6C.

Therefore, since the preformed Cr diffusion barrier layer 30a serves to prevent diffusion of Cr into the ferroelectric thin film as a conductive oxide, the ferroelectric is not affected by the heat treatment process of the high temperature oxidation atmosphere in a subsequent process.

7A to 7C are cross-sectional views illustrating a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a third embodiment of the present invention.

The third embodiment, similarly to the first and second embodiments, first forms a MOS transistor serving as a pass transistor, and then a contact plug 21 and titanium silicide 22 to form a COB structure. After the formation, a double diffusion barrier film consisting of the titanium nitride film 23 and the chromium titanium nitride film 24 is formed (FIG. 7A).

Then, in order to prevent the diffusion of Cr from the chromium titanium nitride film 24 to the capacitor in the third embodiment, for example, a Pt lower electrode 25b is deposited on the upper portion of the chromium titanium nitride film 24 to a thickness of 100 to 2000. After the heat treatment of the oxidizing atmosphere in advance, as shown in FIG. 7B, Cr enters the Pt lower electrode 25b by diffusion into the Pt lower electrode 25b to form CrO ₂ (30b).

As a result, Cr, which can reach the dielectric material 26 by diffusion from the chromium titanium nitride film 24 at the time of heat treatment, is formed in the pretreatment even when a dielectric material 26 such as PZT is subsequently formed and the heat treatment process is performed at a high temperature oxidation atmosphere. Oxidized, so the dielectric is not affected.

8A to 8C are cross-sectional views illustrating a process of forming a lower electrode structure of a capacitor for an ultra-high density storage device having a diffusion barrier according to a fourth embodiment of the present invention.

As described above, the fourth embodiment also first forms a MOS transistor serving as a pass transistor, and then forms a contact plug 21 and a titanium silicide 22 to form a COB structure, followed by a titanium nitride film 23. ) And a double diffusion barrier film formed of a chromium titanium nitride film 24 (FIG. 8A).

Then, in order to prevent the diffusion of Cr from the chromium titanium nitride film 24 to the capacitor in the fourth embodiment, for example, iridium (Ir), ruthenium (Ru) and iridium oxide thereof as oxides are formed on top of the chromium titanium nitride film 24. A Cr diffusion barrier 31 made of any one of (IrO ₂ ) and ruthenium oxide (RuO ₂ ) is formed to a thickness of 1 nm to 100 nm.

Subsequently, when the lower electrode 25 of the Pt and the dielectric 26 are formed and subjected to high temperature oxidation treatment for crystallization, Cr diffused from the chromium titanium nitride film 24 to the capacitor is blocked by the Cr diffusion barrier 31. As a result of the oxidation, a CrO ₂ film 30c is formed between the chromium titanium nitride film 24 and the Cr diffusion barrier film 31, and the dielectric material 26 is not affected by this.

9 is a cross-sectional photograph of the structure of the capacitor after the heat treatment of the capacitor of the fourth embodiment obtained in accordance with FIGS. 8A to 8C, in which Cr is blocked by the Cr diffusion barrier layer 31 and does not affect the dielectric material 26. It can be seen that a CrO ₂ film 30c is formed between the chromium titanium nitride film 24 and the Cr diffusion barrier film 31.

As described above, the lower electrode structure of the capacitor for the ultra-high density memory device having the diffusion barrier according to the first to fourth embodiments of the present invention prevents conductivity preservation and diffusion of Cr in a high temperature oxidation atmosphere, thereby ensuring stability of the high dielectric material. It is to provide a highly integrated semiconductor memory device realization technology having a.

10 is a cross-sectional view of a capacitor for an ultra-high density memory device having a diffusion barrier according to a preferred embodiment of the present invention.

The capacitor shown in FIG. 10 is a structure implemented by integrating the diffusion barrier technologies of the first to fourth embodiments.

The capacitor according to the present invention first forms a contact plug 21 made of polycrystalline silicon on the interlayer insulating layer 29 to form a COB structure after the MOS transistor forming process.

After the deposition of titanium to reduce the contact resistance of the polycrystalline silicon with the contact plug 21, rapid heat treatment in a vacuum nitrogen atmosphere to form the titanium silicide 22 to 30 ~ 50nm thickness.

Subsequently, the titanium nitride film 23 and the chromium titanium nitride film 24 are formed to have a thickness of 10 to 50 nm, respectively, by reactive sputtering to form a double diffusion prevention film.

Subsequently, in order to form a diffusion barrier for preventing diffusion of Cr from the chromium titanium nitride layer 24 among the double diffusion barrier layers, the chromium titanium nitride layer is subjected to the pre-annealing process as in the first embodiment. (24) A Cr diffusion prevention film 30 is formed on the surface with a thickness of about 5 to 20 nm, preferably about 10 nm.

Thereafter, a thin Pt lower electrode 25a of 10 nm or less is deposited as a stopper on the Cr diffusion barrier layer 30 as a stopper, and then the second heat treatment is performed on the lower electrode 25a. A diffusion barrier film 30a is formed.

Subsequently, as in the fourth embodiment, a Cr diffusion barrier layer 31 including a iridium oxide layer IrO ₂ or a ruthenium oxide layer RuO ₂ , which is a conductive oxide, is formed on the Cr diffusion barrier 30a and then subjected to a high temperature heat treatment process. It is formed to help the formation of CrO ₂ and to prevent the diffusion of Cr.

Thereafter, the lower electrode 25 is deposited using Pt, and a dielectric constant of high dielectric constant is deposited. The dielectric constant 26 of high dielectric constant is TiO ₂ , Ta ₂ O ₅ , PZT (Pb, (Zr _x , Ti _1-x ) O ₃ ), SBT (Sr _x Bi _y Ta ₂ O ₉ ), BST ((Ba _x , Sr _1-x ) TiO ₃ ), PLZT (Pb _1-y , La _y (Zr _x , Ti _1-x ) O ₃ ), BT (Bi ₄ Ti ₃ O ₁₂ ), ST (SrTiO ₃ ) You can use one.

After that, a high temperature (550 to 850 ° C.) heat treatment is performed in an oxygen atmosphere to obtain the characteristics of the high dielectric material.

After the Pt is deposited on the upper electrode 17 to complete the capacitor, the interlayer insulating layer 28 is filled.

In the capacitor structure of the present invention configured as described above, the composition of the chromium titanium nitride layer in the double diffusion barrier layer had Cr _x Ti _1-x N (0.7 <x <0.9) when the RBS (Rutherford Backscattering Spectrometry) analysis was performed. .

As described above, the connection structure between the capacitor and the pass transistor of the present invention has excellent conductivity when the polycrystalline silicon is used as the contact plug 21, and a titanium nitride film 23 which blocks the diffusion of chromium and a strong titanium oxide at high temperature. The adoption of the chromium nitride film 24 forms an excellent mechanism as a composite diffusion barrier for polycrystalline silicon.

That is, when Pt is used as the lower electrode 25 of the capacitor C, oxygen is chromium titanium when oxygen (O ₂ ) diffuses into the lower diffusion prevention layer in the high temperature oxidation atmosphere through the high grain permeability of oxygen. Spontaneous formation of an ultrathin film that directly prevents oxidation by chromium (Cr) showing rapid diffusion in the nitride film 24, and diffusion of chromium into polycrystalline silicon, which is a problem of the chromium titanium nitride film 24 itself, It is blocked by the titanium nitride film 23.

Further, the diffusion of chromium into the dielectric 26 of the capacitor C according to the formation of the titanium chromium nitride film (CrTiN) 24 / the titanium nitride film (TiN) 23 may be caused by any of the first to fourth embodiments described above. The diffusion of chromium is blocked by the chromium diffusion barrier layer structure composed of one or a combination thereof.

In other words, CrO ₂ , which is a conductive oxide, is formed in advance by a pre-annealing process as in the first embodiment to prevent diffusion of Cr into the high dielectric material, or after the thin lower electrode Pt is deposited in advance as in the second embodiment. After the heat treatment causes the diffusion of Cr through the interface of the Pt lower electrode layer in advance to form a CrO ₂ thin film produced during the heat treatment, and then deposit a lower electrode (Pt) more stable to the diffusion of Cr, or the third embodiment After the formation of the double barrier layer as described above, the lower electrode (Pt) layer is deposited to heat-treat the oxidation atmosphere in advance to prevent diffusion of Cr into the high-k dielectric (PZT) or iridium (Ir), as in the fourth embodiment. ruthenium (Ru) and formed in its oxide electrodes, iridium oxide (IrO _2), ruthenium oxide (RuO ₂₎ a lower electrode when the high-temperature oxygen annealing in a way that prevents the diffusion of Cr through the inserted between the diffusion preventing film CrTiN thin film By pre Sikkim forming a conductive oxide (CrO ₂₎ it is to prevent the diffusion of Cr into the high-dielectric (PZT).

As a result, it is possible to form a capacitor using a high-k dielectric material by adding the diffusion barrier of the present invention, compared to the conventional diffusion barrier, which is not possible to realize substantial high integration. Therefore, as a highly integrated large-capacity volatile and nonvolatile memory device, The effect that can be utilized for Ultra Large Scale Integration (ULSI) can be expected.

As described above, in the present invention, a first diffusion barrier layer made of a CrTiN / TiN thin film to prevent oxygen diffusion to a polycrystalline silicon contact plug electrically connecting a pass transistor and a capacitor in an ultra-high density memory device using a ferroelectric or a high dielectric material. And a second diffusion barrier layer capable of preventing diffusion of Cr from CrTiN into the dielectric, the ferroelectric thin film, the lower electrode, and the silicon plug can have excellent physical and electrical properties even after the high temperature oxidation heat treatment process.

In the above, the present invention has been illustrated and described with reference to specific preferred embodiments, but the present invention is not limited to the above-described embodiments and is not limited to the spirit of the present invention. Various changes and modifications can be made by those who have

Claims (17)

In order to prevent diffusion of oxygen and chromium in polycrystalline silicon contact plugs electrically connecting a pass transistor and a capacitor using ferroelectric or high dielectric in a COB structure ultra-high density memory device (Cr _x Ti _1-x N) In the lower electrode structure of the capacitor having a first diffusion barrier layer formed of a titanium nitride film (TiN), As the first diffusion barrier is pre-annealed, chromium titanium nitride film is formed between the Pt lower electrode and chromium is diffused from the chromium titanium nitride film to the dielectric through the Pt lower electrode during the high temperature heat treatment of the ferroelectric or high dielectric material. A lower electrode structure of a capacitor, comprising a second diffusion prevention film for preventing. In the lower electrode structure of the capacitor for electrically connecting the pass transistor and the capacitor located on top of the transistor using a polycrystalline silicon contact plug, A titanium silicide film (TiSix) formed on the polycrystalline silicon contact plug to reduce contact resistance; A chromium titanium nitride film (Cr _x Ti _1-x N) / titanium nitride film (TiN) is formed on the titanium silicide layer to prevent diffusion of oxygen and chromium into the polycrystalline silicon contact plug during high temperature heat treatment of the dielectric of the capacitor. A first diffusion barrier layer, And a second diffusion barrier layer formed between the chromium titanium nitride layer and the Pt lower electrode of the capacitor to prevent the diffusion of chromium from the chromium titanium nitride layer into the dielectric through the Pt lower electrode during the high temperature heat treatment of the dielectric. Lower electrode structure of the capacitor. In the lower electrode structure of the capacitor for electrically connecting the pass transistor and the capacitor located on top of the transistor using a polycrystalline silicon contact plug, A chromium titanium nitride film (Cr _x Ti _1-x N) / titanium nitride film (TiN) is formed on the polycrystalline silicon contact plug to prevent oxygen and chromium from diffusing into the polycrystalline silicon contact plug during high temperature heat treatment of the dielectric of the capacitor. A first diffusion barrier layer formed of A Pt thin film layer formed on the chromium titanium nitride film of the first diffusion barrier film and acting as a catalyst such that Cr forms a conductive oxide during heat treatment; A second diffusion barrier layer formed on the upper and lower surfaces of the Pt thin film layer according to the heat treatment of the Pt thin film layer to prevent chromium from diffusing into the dielectric from the chromium titanium nitride film through the Pt lower electrode during the high temperature heat treatment of the dielectric; The lower electrode structure of the capacitor, characterized in that provided with. In the lower electrode structure of the capacitor for electrically connecting the pass transistor and the capacitor located on top of the transistor using a polycrystalline silicon contact plug, A first diffusion barrier layer formed of a chromium titanium nitride layer (Cr _x Ti _1-x N) / titanium nitride layer (TiN) to prevent oxygen and chromium from diffusing into the polycrystalline silicon contact plug during high temperature heat treatment of the dielectric of the capacitor; , A second diffusion barrier layer formed on the chromium titanium nitride layer of the first diffusion barrier layer to prevent chromium from diffusing from the chromium titanium nitride layer into the dielectric layer during high temperature heat treatment of the dielectric layer; And a CrO ₂ film formed between the second diffusion barrier film and the Pt lower electrode of the capacitor by chromium diffused from the chromium titanium nitride film during the high temperature heat treatment of the dielectric. The lower electrode structure of claim 1, wherein the second diffusion barrier layer is an oxide of chromium diffused from the chromium titanium nitride layer by pre-annealing the first diffusion barrier layer. The lower electrode structure of claim 4, wherein the second diffusion barrier layer is made of one of iridium (Ir), ruthenium (Ru), iridium oxide (IrO ₂ ), and ruthenium oxide (RuO ₂ ). 3. The third diffusion barrier layer of claim 2, further comprising: a third diffusion barrier layer formed on the second diffusion barrier layer to prevent chromium from diffusing from the chromium titanium nitride layer into the dielectric layer at a high temperature heat treatment to the dielectric layer; And a CrO ₂ film formed below the third diffusion prevention film by chromium diffused from the chromium titanium nitride film during the high temperature heat treatment of the dielectric. A method of forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, Titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug, and oxygen diffused into the polycrystalline silicon contact plug on the titanium nitride film. Sequentially forming a chromium titanium nitride film (Cr _x Ti _1-x N) to prevent the formation thereof; Forming a CrO ₂ film on the surface of the chromium titanium nitride film by pre-annealing to prevent chromium from diffusing into the dielectric from the chromium titanium nitride film through the Pt lower electrode during the high temperature heat treatment of the dielectric; Forming a lower Pt electrode on the CrO ₂ film. A method of forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, Titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug, and oxygen diffused into the polycrystalline silicon contact plug on the titanium nitride film. Sequentially forming a chromium titanium nitride film (Cr _x Ti _1-x N) to prevent the formation thereof; Forming a Pt layer of a thin film formed on the chromium titanium nitride film and acting as a catalyst so that chromium forms a conductive oxide during pre-annealing; The Pt layer is pre-annealed to form a CrO ₂ film on the upper and lower surfaces of the Pt thin film layer to prevent chromium from diffusing into the dielectric from the chromium titanium nitride film through the Pt lower electrode during the high temperature heat treatment of the dielectric. To do that, Forming a lower Pt electrode on the CrO ₂ film. A method of forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, Titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug, and oxygen diffused into the polycrystalline silicon contact plug on the titanium nitride film. Sequentially forming a chromium titanium nitride film (Cr _x Ti _1-x N) to prevent the formation thereof; Forming a Pt lower electrode on the chromium titanium nitride layer; Forming a CrO ₂ film inside the Pt lower electrode by pre-annealing the Pt lower electrode to prevent chromium from diffusing into the dielectric through the Pt lower electrode during the high temperature heat treatment of the dielectric. Method for forming a lower electrode of the capacitor, characterized in that. A method of forming a lower electrode of a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, Titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug, and oxygen diffused into the polycrystalline silicon contact plug on the titanium nitride film. Sequentially forming a chromium titanium nitride film (Cr _x Ti _1-x N) to prevent the formation thereof; Forming a Cr diffusion barrier layer on the chromium titanium nitride layer to prevent the diffusion of Cr from the chromium titanium nitride layer into the dielectric during the high temperature heat treatment of the dielectric; Forming a Pt lower electrode on the Cr diffusion barrier; A method of forming a lower electrode of a capacitor, wherein a CrO ₂ film is formed under the Cr diffusion barrier layer by Cr diffused from the chromium titanium nitride layer during the high temperature heat treatment of the dielectric. The method according to any one of claims 8 to 10, wherein the CrO ₂ film is formed to have a thickness of 5 to 20 nm. The method according to any one of claims 8 to 10, further comprising forming a Cr diffusion barrier layer to prevent chromium from diffusing from the chromium titanium nitride film into the dielectric during the high temperature heat treatment of the dielectric before forming the Pt lower electrode. More, A method of forming a lower electrode of a capacitor, wherein a CrO ₂ film is formed under the Cr diffusion barrier due to chromium being diffused from the chromium titanium nitride film during the high temperature heat treatment of the dielectric. The dielectric material of claim 8, wherein the dielectric material is TiO ₂ , Ta ₂ O ₅ , PZT (Pb, (Zr _x , Ti _1-x ) O ₃ ), SBT (Sr _x Bi _y Ta ₂ O ₉ ), BST ((Ba _x , Sr _1-x ) TiO ₃ ), PLZT (Pb _1-y , La _y (Zr _x , Ti _1-x ) O ₃ ), BT (Bi ₄ Ti ₃ O ₁₂ ) And ST (SrTiO ₃ ). The method of claim 11, wherein the Cr diffusion barrier is formed of any one of iridium (Ir), ruthenium (Ru), iridium oxide (IrO ₂ ), and ruthenium oxide (RuO ₂ ). A method of forming a capacitor connected to a lower pass transistor through a polycrystalline silicon contact plug, Titanium nitride film (TiN) for preventing chromium from diffusing into the polycrystalline silicon contact plug during the high temperature heat treatment of the dielectric of the capacitor on the polycrystalline silicon contact plug, and oxygen diffused into the polycrystalline silicon contact plug on the titanium nitride film. Sequentially forming a chromium titanium nitride film to prevent it from being formed, Forming a first Cr diffusion barrier on the surface of the chromium titanium nitride film by pre-annealing to prevent chromium from diffusing from the chromium titanium nitride film to the dielectric through the Pt lower electrode during the high temperature heat treatment of the dielectric; Forming a Pt lower electrode on the first Cr diffusion barrier layer; Forming a dielectric on the Pt lower electrode; Heat treatment in a high temperature oxidizing atmosphere to crystallize the dielectric; And forming an upper electrode on the dielectric. 17. The capacitor of claim 16, further comprising forming a second Cr diffusion barrier layer on the top of the CrO ₂ film to prevent the diffusion of chromium from the chromium titanium nitride layer into the dielectric during the high temperature heat treatment of the dielectric. Method of formation.