KR100442709B1 - A capacitor having double protection layer of hetero-nitride and a method for forming electrodes thereof - Google Patents

Abstract

The capacitor having the double barrier film of the dissimilar nitride of the present invention comprises: a polycrystalline silicon (Poly-Si) layer 21 in contact with one terminal on a substrate; An ASi _x layer (1 <x <3) 22 on the polycrystalline silicon layer; An A _1-y Si _y N layer (0 ≦ y <1) 23 (where A is Ti, W or Ta) as a first prevention film on the ASi _x layer (1 ≦ _x ≦ 3); D _z A _1-z N layer (0 <z <1) 23 as a second protective film on the A _1-y Si _y N layer (0 ≦ y <1) layer (where A is Ti, W or Ta) , D is Cr, Re or Al); A lower electrode 25 on the D _z A _1-z N layer (0 <z <1); A dielectric layer 26 on the lower electrode; And a capacitor over bit-line (capacitor on bit-line) structure having a double diffusion barrier layer, characterized in that it comprises an upper electrode 7 on the dielectric layer. Therefore, by applying the barrier film having the structure of the above-described invention, it is possible to form a capacitor using a high-k dielectric material, and thus to be utilized in an ultra large scale integration (ULSI) as a highly integrated high-volume volatile and nonvolatile memory device. You can expect the effect.

Description

A capacitor having a double barrier of heteronitride and a method for forming an electrode thereof {A CAPACITOR HAVING DOUBLE PROTECTION LAYER OF HETERO-NITRIDE AND A METHOD FOR FORMING ELECTRODES THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device and a structure thereof, and more particularly, to a capacitor using a dielectric thin film having a high dielectric constant and a fabrication thereof.

In general, a semiconductor memory device is classified into a volatile memory device in which information stored in the semiconductor memory device disappears at the same time when the power supply is cut off, and a nonvolatile memory device in which information remains even when the power supply is cut off. While the development of memory devices using these materials has been actively progressed along with the interest of new high-k materials due to the large capacity of storage media, semiconductors in which dielectric or ferroelectric materials having large dielectric constants are practically applied to volatile and non-volatile memory devices. It is applied to memory devices. Such high dielectric materials include titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and BST ((Ba _{x '} ,) to replace the low dielectric materials used in the conventional volatile DRAM (DRAM). Sr _{1-x '} ) TiO ₃ ) PZT (Pb (Zr _x' , Ti _{1-x '} ) O ₃ ) and SBT (SrBi ₂ Ta ₂ O ₉ ) with high dielectric constant and ferroelectric There is a non-volatile memory device to which is applied. Among these memory devices, nonvolatile memory devices are indispensable to portable electronic devices. Especially, memory devices using ferroelectrics have advantages such as faster read / write speed, operation, and frequency at a single power supply voltage than conventional flash memory devices. It has been developed as a next-generation large-capacity, highly integrated nonvolatile memory device.

This high-dielectric memory device is similar to the conventional DRAM fabrication process, and has a structure of 2T-2C (two capacitors in two transistors) or 1T-1C (one capacitor in one transistor) for high integration. In addition, there is an advantage that the degree of integration can be greatly improved by applying a Capacitor Over Bit-line (Capacitor On Bit-line) structure in the circuit design. The capacitor has a structure in which a lower portion is connected to a polycrystalline silicon node connected to a source / drain of a pass transistor. After forming a high-k dielectric layer on the lower electrode of the capacitor, the high-k dielectric layer The crystallization heat treatment process of the high temperature oxidizing atmosphere to obtain the high dielectric properties of In this high temperature oxidation process, the contact resistance is increased due to the deterioration of characteristics due to the interfacial reaction product between the polycrystalline silicon and the lower electrode (formerly platinum: Pt), and also between the lower electrode and the polycrystalline silicon due to diffusion of oxygen at high temperature. The problem is that the ultimate high dielectric properties cannot be obtained due to the formation of the unwanted insulator oxide film.

This problem will be described with reference to FIG. 1, which is a conventional capacitor structure. First, after a process of forming a word line 2 and a bit line 3 on a silicon substrate 1, a pass transistor is formed. Titanium silicide (TiSi _x ) (1≤x≤3) (6) and barrier film (7) formed by rapid heat treatment of nitrogen atmosphere to reduce the contact resistance between the drain (4) and the polycrystalline silicon plug (5) connecting the capacitor. ), The lower electrode 8, the high dielectric material layer 9, the upper electrode 10, and the interlayer insulating layer 11 are formed in this order.

The prevention film 7 includes a conductive oxide film and a nitride prevention film. Among these, conductive oxides include iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), and rhodium oxide (RhO _x ), which have the advantage of being able to act as electrodes and barriers. Has a disadvantage in that the roughness becomes considerably large, and the iridium oxide film has a problem in that etching is difficult.

In addition, the nitride preventing film includes a titanium nitride film (TiN), a tantalum nitride film (TaN), a titanium aluminum nitride film (TiAlN; US Pat. No. 5,856,704), a titanium chromium nitride film (TiCrN; Korean Patent Application No. 10-1998-0035021), and the like. Titanium nitride film, which has good conductivity, is used as the most common prevention film.However, at a temperature higher than 600 ° C, the titanium nitride film forms titanium oxide and loses its conductivity.In the case of titanium aluminum nitride film or titanium chromium nitride film, high temperature is compared with titanium nitride film. Although it shows improved stability at, it is not suitable for diffusion prevention film due to the reaction problem with silicon and has a problem that it is not applicable to a long time heat treatment process at a high temperature applied in a practical semiconductor device integration process.

On the other hand, the barrier film structures 21a, 12b, 13a, and 14b of the complex structure have been proposed to take advantage of the above-mentioned problems. For example, nitride such as TiN is used as the first barrier 12a used as the double barrier in FIG. 1, and iridium (Ir) is used as the second barrier 12b. In addition, iridium oxide (IrO) was again used for the third composite layer 13b between the lower electrode 13a such as platinum and the dielectric layer.

However, although various conductive barrier films as described above have been proposed, the conventional barrier films have been exposed to electricity by the oxidation of the barrier film itself by oxygen diffusion and the oxidation of polycrystalline silicon in the long-term high temperature heat treatment process of 600 ° C. or higher. The problem of loss of conductivity has made it difficult to apply to substantial high integration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a highly integrated semiconductor memory device realization technique in which a double structured barrier film is inserted between polycrystalline silicon and a lower electrode, and has stability during high temperature oxidation heat treatment.

Further objects and effects of the present invention will become more apparent from the following detailed description of the invention described with reference to the accompanying drawings.

1 is a schematic diagram of a conventional capacitor structure.

2 is a schematic diagram of a capacitor structure according to the present invention;

3A and 3B are cross-sectional and plan views, respectively, of an actual contact structure for measuring characteristics when the double barrier film according to the present invention is substantially integrated into an element.

4A to 4C are graphs showing current values with respect to a voltage applied as a contact resistance when the number of polycrystalline silicon plugs of FIG. 3 is one. FIG. 4A is a case of a titanium nitride film, and FIG. 4B is a case of a titanium chromium nitride film. 4C is for the case of the double-layered prevention film of the present invention.

5A to 5C are graphs showing current values with respect to a voltage applied as a contact resistance when the number of polycrystalline silicon plugs of FIG. 3 is 500. FIG. 5A is a case of a titanium nitride film, and FIG. 5B is a case of a titanium chromium nitride film. 5C is for the case of the double-layered prevention film of the present invention.

FIG. 6 is a graph showing contact resistance values at an applied voltage of 3V with respect to each heat treatment temperature in the case of FIG. 3.

FIG. 7 is a graph illustrating contact resistance values when heat treatment is performed for 2 hours in an oxygen atmosphere at a temperature of 725 ° C in the case of FIG. 3.

<Description of the symbols for the main parts of the drawings>

1 substrate 2 word line

3: bit line 4: drain

5: polysilicon plug 6: titanium silicide layer

7: prevention film 8: lower electrode

9 dielectric layer 10 upper electrode

11: interlayer insulating material layer 12a-13b: conventional composite barrier film

21 polycrystalline silicon plug 22 titanium silicide layer

23: titanium nitride film 24: chromium titanium nitride film

25: lower electrode 26: dielectric layer

27: upper electrode 28: interlayer insulating material layer

31 polysilicon plug 32 substrate

33: silicon oxide layer 34: n + doped surface

35: titanium silicide layer 36: first heteronitride film

37: second heteronitride film 38: electrode

According to an aspect of the present invention, there is provided a capacitor having a double barrier layer of a dissimilar nitride, including: a polysilicon (Poly-Si) layer 21 in contact with one terminal on a substrate; An ASi _x layer (1 <x <3) 22 on the polycrystalline silicon layer; An A _1-y Si _y N layer (0 ≦ y <1) 23 (where A is Ti, W or Ta) as a first prevention film on the ASi _x layer (1 ≦ _x ≦ 3); D _z A _1-z N layer (0 <z <1) 24 as a second protective film on the A _1-y Si _y N layer (0 ≦ y <1) layer (where A is Ti, W or Ta) , D is Cr or Re); A lower electrode 25 on the D _z A _1-z N layer (0 <z <1); A dielectric layer 26 on the lower electrode; And an upper electrode 7 on the dielectric layer, and having a conductive property on the D _z A _1-z N layer (0 <z <1) 24 as the second protective layer (CrO _{z ″} (0.9 <). z "<3)) and a rhenium oxide film (ReO _z"' (0.9 <z "'<4)) are formed.

Preferably, in the D _z A _1-z N layer, z is 0.7 <z <0.9, and the upper and lower electrodes are platinum (Pt), iridium (Ir), ruthenium (Ru), rhodium (Rh), and their At least one selected from oxides of iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), rhodium oxide (Rh _x O _y ), strontium ruthenium oxide (SrRuO ₃ ), and the dielectric material of the dielectric layer is , TiO ₂ , Ta ₂ O ₅ , PZT (Pb, (Zr _{x '} , Ti _1-x' ) O ₃ ), SBT (Sr _{x '} Bi _y' Ta ₂ O ₉ ), BST ((Ba _{x '} , Sr _{1-x '} ) TiO ₃ ), PLZT (Pb _1-y' , La _{y '} (Zr _x' , Ti _{1-x '} ) O ₃ ), BT (Bi ₄ Ti ₃ O ₁₂ ), and ST (SrTiO ₃ It is characterized in that any one or more of the materials such as) is selected.

On the other hand, according to another aspect of the present invention, a method of forming an electrode of a capacitor having a double barrier film of heteronitride, after depositing titanium or tantalum in order to reduce the contact resistance of the contact plug 21 of polycrystalline silicon, the nitrogen atmosphere in a vacuum state A high temperature rapid heat treatment at to form an ASi _x layer (1 <x <3) 22 (where A is Ti, W or Ta); A _1-y Si _y N layer (0 ≦ y <1) 23 as a first protective film on the ASi _x layer (1 ≦ _x ≦ 3) by reactive sputtering (where A is Ti, W Or Ta), and a D _z A _1-z N layer (0 <z <1) 24 (where A is a second prevention film) on the A _1-y Si _y N layer (0 ≦ y <1) layer. Is Ti, W or Ta, D is Cr or Re); Depositing a lower electrode 25 on the D _z A _1-z N layer (0 <z <1) 24; After depositing the dielectric layer 26 on the lower electrode, the D _z A _1-z N layer (0 <z <1) was subjected to a high temperature (550-850 ° C.) heat treatment in an oxygen atmosphere to obtain high dielectric properties. To spontaneously form a chromium oxide film (CrO _{z "} (0.9 <z"<3)) or a rhenium oxide film (ReO _{z "'} (0.9 <z"'<4)) having conductive properties on ; And then depositing the upper electrode 27.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of a capacitor structure according to the present invention. That is, the double barrier layer of the heteronitride layer proposed in the present invention is formed through the following process steps for the contact plug-in polysilicon as shown in FIG. 2 to form a COB structure after a MOS transistor. do.

First, titanium was deposited to reduce the contact resistance of the polycrystalline silicon with the contact plug 21, and then the titanium silicide 22 was formed by rapid heat treatment at 700 ° C. in a nitrogen atmosphere in a vacuum state, and by reactive sputtering. After forming the titanium nitride film 23 and the chromium titanium nitride film 24 to form a double barrier film, platinum 25 was deposited using the lower electrode, and the dielectric material 26 was deposited in an oxygen atmosphere to obtain the characteristics of the high dielectric material. High temperature (550-850 degreeC) heat processing is performed. After that, a capacitor is formed by depositing platinum, which is the upper electrode 27, and then the capacitor is formed by filling the interlayer insulating material 28.

In such a structure, the titanium nitride film is a conductive film having excellent conductivity. As is known in the literature, the diffusion rate of chromium in silicon is considerably fast, thereby suppressing the diffusion of chromium by the titanium nitride film having excellent diffusion preventing ability, and the chromium titanium nitride film. By forming a chromium oxide film (CrO _z ) having a very thin conductivity properties during high temperature oxidation heat treatment to withstand the diffusion of oxygen and high temperature to have a complementary structure to prevent oxidation of the titanium nitride film. (The electrical properties of these chromium oxide films can be found in Modern Ceramic Engineering, 2nd Edition, David W. Richerson, pp. 206-210, 1992.)

The composition of the chromium titanium nitride layer in the double barrier layer is Cr _z Ti _1-z N (0 <z <1, preferably, 0.7 <z <0.9) as seen through RBS (Rutherford Backscattering Spectrometry) analysis. It has a composition, and basically, the above composition, which shows the best characteristics among the results of the investigation of various compositions by controlling the ratio of chromium, titanium, and nitrogen, was applied in the present patent.

The titanium silicide 22 on the polysilicon layer may be replaced with tantalum silicide or tungsten silicide, and the titanium nitride film layer as the first double barrier layer may be a tantalum nitride film (TaN), a tungsten nitride film (WN), a tantalum silicon nitride film (TaSiN), or the like. It may be replaced with a titanium silicon nitride film (TiSiN). In addition, the chromium titanium nitride film (Cr _z Ti _1-z N) of the second double barrier layer may include an aluminum titanium nitride film (Al _z Ti _1-z N (0 <z <1)) and a chromium tantalum nitride film (Cr _z Ta _{1). -z} N (0 <z <1), chromium tantalum nitride film (Al _z Ta _1-z N (0 <z <1), chromium tungsten nitride film (Cr _z W _1-z N), rhenium titanium nitride film (Re _z) Ti _1-z N), rhenium tantalum nitride film (Re _z Ta _1-z N), rhenium tungsten nitride film (Re _z W _1-z N), or the like, and the platinum (Pt) electrode applied to the capacitor structure In addition, iridium (Ir), ruthenium (Ru), rhodium (Rh) and its oxide electrodes iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), rhodium oxide (Rh _{x '} O _y' ), strontium ruthenium oxide ( SrRuO ₃ ) electrode may be replaced, and as the high dielectric material, TiO ₂ , Ta ₂ O ₅ , PZT (Pb, (Zr _{x '} , Ti _1-x' ) O ₃ ), SBT (Sr _{x '} Bi _{y '} Ta ₂ O ₉ ), BST ((Ba _x' , Sr _{1-x '} ) TiO ₃ ), PLZT (Pb _1-y' , La _{y '} (Zr _x' , Ti _{1-x '} ) O ₃ ) _{, BT (Bi 4 Ti 3 O} 12), and ST (SrTiO ₃₎ and This material can be applied.

At this time, during the electrode formation process according to the present invention, the structure of the capacitor electrode, the D _z A _1-z N layer (0 <z <1) 24 (wherein A is Ti, W or Ta, D is used to allow spontaneous formation of a thin chromium oxide film (CrO _{z "} (0.9 <z"<3)) or rhenium oxide film (ReO _{z "'} (0.9 <z"'<4)) on Cr or Re). It is preferable.

The basic principle of the present invention is that, as mentioned above, the titanium nitride film has excellent properties as a conductivity and diffusion barrier film, and the titanium chromium nitride film is well tolerated in a high temperature oxidation atmosphere. This is because the platinum electrode has high oxygen permeability and oxygen diffuses from the high temperature oxidizing atmosphere to the barrier layer through crystal grains, and it meets the chromium with rapid diffusion in the oxygen and chromium titanium nitride to prevent oxidation directly. The ultrathin film spontaneously forms. In addition, the diffusion of chromium into polycrystalline silicon, which is a problem of the chromium titanium nitride film itself, can be prevented by the titanium nitride film.

On the other hand, when the invention is substantially integrated into the device, it must have electrical conductivity with respect to the high temperature oxidation atmosphere. 3A and 3B are cross-sectional views and plan views of an actual contact structure for measuring characteristics when the double barrier film according to the present invention is substantially integrated into an element.

In the actual contact structure of FIG. 3A, the diameter of the polysilicon plug 31 is 0.25 μm to 0.35 μm, and the number of polysilicon plugs is 1 to 500. The contact pattern is formed in the silicon substrate 32. Both polycrystalline silicon formed through the silicon oxide 33, which is an insulating layer, were formed through the n + -doped surface 34, and the capacitor electrode 38 was formed on the first and second hetero nitride layers on the titanium silicide 35. The double barrier film (36, 37) and the electrode 38 were formed in the order of depositing to test the contact resistance. In the actual figure, nine polycrystalline silicon plugs are shown on the left and 63 polycrystalline silicon plugs are shown on the right.

4 and 5 are graphs showing current values with respect to voltages applied as contact resistances when the number of polycrystalline silicon is 1 and 500, respectively, and as the slope is inversely proportional to the contact resistance value, the higher the slope, the higher the electrical conductivity. will be.

4A to 4C are graphs showing a current value with respect to a voltage applied as a contact resistance when the number of polycrystalline silicon plugs of FIG. 3 is one. FIG. 4A is a case of a titanium nitride film, and FIG. 4B is a titanium chromium nitride film. 4C is for the case of the double-layered prevention film of the present invention, and FIGS. 5A to 5C show current values for voltages applied as contact resistance when the number of polysilicon plugs of FIG. 3 is 500. FIG. As a graph, FIG. 5A shows a case of a titanium nitride film, FIG. 5B shows a case of a titanium chromium nitride film, and FIG. 5C shows a case of a double structure prevention film of the present invention.

As shown in FIG. 4, in the case of a contact pattern having one polycrystalline silicon, the titanium nitride film (FIG. 4A) shows a greater resistance value than before the heat treatment even at a low temperature of 550 ° C, and the titanium chromium nitride film (FIG. 4B) is after 700 ° C. On the other hand, it can be seen that the electrical conductivity is lost, but in the case of the barrier film (FIG. 4C) having the dual structure of the present invention, the conductivity is good even at a high temperature of 800 ° C.

In addition, when 500 polycrystalline silicon is present on a practical integrated circuit, the overall contact resistance is lowered, which shows electrical conductivity up to 600 ° C in the case of a titanium nitride film (FIG. 4A), and a contact resistance to withstand the chromium titanium nitride film (FIG. 5B). Although better, it was not able to withstand high temperatures above 700 ℃, but the double structure of hetero nitride film (Fig. 5c) showed similar contact resistance even after high temperature oxidation heat treatment at 850 ℃, and as the other barrier increased as the temperature increased to high temperature. Contrary to this increasing trend, temperature-independent results are shown. These results are summarized in FIG. 6 when the contact resistance values at the applied voltage of 3V for each heat treatment temperature are summarized.

FIG. 6 is a graph showing contact resistance values at an applied voltage of 3V for each heat treatment temperature in FIG. 3, and FIG. 7 is a contact when heat treatment is performed for 2 hours under an oxygen atmosphere at a temperature of 725 ° C. in FIG. 3. It is a graph showing the resistance value.

It was a problem in the prior art using the dual structure capacitor electrode structure of dissimilar nitride film in that the protection film must maintain the electrical conductivity even in the continuous high temperature heat treatment process in the device integration process in that it is a capacitor electrode for applying the high integration of the COB structure. The contact resistance value when heat treatment of the oxygen atmosphere for 2 hours at the temperature of 725 degreeC or more is shown in FIG. In Figure 7, it is shown that the number of polycrystalline silicon 1, 50, 500 is stable even in the heat treatment that continues. Therefore, it can be seen that the double barrier film of the present invention is a suitable structure for the capacitor electrode structure of the highly integrated COB structure to which a long-term high temperature heat treatment process that cannot be solved by the conventional technology can be applied.

Although the present invention has been described above with reference to one embodiment shown in the accompanying drawings, the present invention is not limited thereto, and various modifications may be made within a range easily understood by those skilled in the art. Therefore, the limitation of the present invention should be limited only by the following claims.

As described above, the capacitor having a double barrier film of the hetero nitride according to the present invention has a high dielectric constant by applying the barrier film having the structure of the above-mentioned invention, whereas the existing barrier film has not been able to realize substantial high integration. Capacitors can be formed using materials, and thus, high-capacity volatile and non-volatile memory devices can be expected to be used in ultra large scale integration (ULSI).

Claims (6)

A polysilicon (Poly-Si) layer 21 in contact with one terminal on the substrate; An ASi _x layer (1 <x <3) 22 on the polycrystalline silicon layer; An A _1-y Si _y N layer (0 ≦ y <1) 23 (where A is Ti, W or Ta) as a first prevention film on the ASi _x layer (1 ≦ _x ≦ 3); D _z A _1-z N layer (0 <z <1) 24 as a second protective film on the A _1-y Si _y N layer (0 ≦ y <1) layer (where A is Ti, W or Ta) , D is Cr or Re); A lower electrode 25 on the D _z A _1-z N layer (0 <z <1); A dielectric layer 26 on the lower electrode; And An upper electrode 7 on the dielectric layer, The second film as a D _z A _1-z N layer (0 <z <1) ( 24) chromium oxide film _{(CrO z "(0.9 <z} "<3)) formed on or rhenium oxide (ReO _{z "'(0.9}< z "&quot;< 4) &gt;), wherein the capacitor has a double-blocking film of hetero-nitride having a double-block diffusion-proof film and a capacitor-over bit-line (Capacitor On Bit-line) structure. The method of claim 1, _{Z in} the D _z A _1-z N layer is a capacitor having a double barrier of hetero-nitride, characterized in that 0.7 <z <0.9. The method of claim 1, The upper and lower electrodes include platinum (Pt), iridium (Ir), ruthenium (Ru), rhodium (Rh), and their oxides, iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), and rhodium oxide (Rh _x O _y ), a strontium ruthenium oxide (SrRuO ₃ ) is a capacitor having a double barrier film of hetero-nitride, characterized in that at least one selected. The method of claim 1, The dielectric material of the dielectric layer is TiO ₂ , Ta ₂ O ₅ , PZT (Pb, (Zr _{x '} , Ti _1-x' ) O ₃ ), SBT (Sr _{x '} Bi _y' Ta ₂ O ₉ ), BST ( (Ba _{x '} , Sr _1-x' ) TiO ₃ ), PLZT (Pb _{1-y '} , La _y' (Zr _{x '} , Ti _1-x' ) O ₃ ), BT (Bi ₄ Ti ₃ O ₁₂ ) , And a capacitor having a double barrier layer of hetero nitride, wherein at least one of a material such as ST (SrTiO ₃ ) is selected. Titanium or tantalum is deposited to reduce contact resistance of the contact plugs 21 of the polycrystalline silicon, and then subjected to high temperature rapid heat treatment in a nitrogen atmosphere in vacuum to provide the ASi _x layer (1 <x <3) (22) (A Forming Ti, W or Ta); A _1-y Si _y N layer (0 ≦ y <1) 23 as a first protective film on the ASi _x layer (1 ≦ _x ≦ 3) by reactive sputtering (where A is Ti, W Or Ta), and a D _z A _1-z N layer (0 <z <1) 24 (where A is a second prevention film) on the A _1-y Si _y N layer (0 ≦ y <1) layer. Is Ti, W or Ta, D is Cr or Re); Depositing a lower electrode 25 on the D _z A _1-z N layer (0 <z <1) 24; After depositing the dielectric layer 26 on the lower electrode, the D _z A _1-z N layer (0 <z <1) was subjected to a high temperature (550-850 ° C.) heat treatment in an oxygen atmosphere to obtain high dielectric properties. Allowing spontaneous formation of a chromium oxide film (CrO _{z "} (0.9 <z"<3)) or a rhenium oxide film (ReO _{z "'} (0.9 <z"'<4)) on the 24; And Thereafter, the method of forming an electrode of a capacitor having a double barrier layer of hetero-nitride consisting of depositing an upper electrode (27). delete