KR20040083899A - Flip Chip Packaging Method for Enhancing the Performance of Connection - Google Patents
Flip Chip Packaging Method for Enhancing the Performance of Connection Download PDFInfo
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- KR20040083899A KR20040083899A KR1020030018593A KR20030018593A KR20040083899A KR 20040083899 A KR20040083899 A KR 20040083899A KR 1020030018593 A KR1020030018593 A KR 1020030018593A KR 20030018593 A KR20030018593 A KR 20030018593A KR 20040083899 A KR20040083899 A KR 20040083899A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
본 발명은 반도체 패키징 기술에 관한 것으로, 더욱 상세하게는 칩과 기판 양측에 범프를 형성하여 접합성능을 개선시킨 플립칩 패키징 방법에 관한 것이다.The present invention relates to a semiconductor packaging technology, and more particularly, to a flip chip packaging method in which bumps are formed on both sides of a chip and a substrate to improve bonding performance.
일반적으로, 반도체 패키지는 전기적으로 외부와 연결할 수 있는 핀과 칩(다이)을 장착시킬 수 있는 구조물인 리드 프레임, 리드 프레임과 본딩패드를 연결하는 선, 칩을 장착하는 패들, 및 봉합물질들로 이루어진다. 그리고 반도체 패키지는 사용되는 밀봉재료에 따라 수지 밀봉 패키지, TCP(Tape Carrier Package) 패키지, 글래스 밀봉 패키지, 금속 밀봉 패키지 등으로 구분되고, 실장방법에 따라 삽입형과 표면실장형(SMT: Surface Mount Technology)으로 구분된다. 삽입형 패키지로는 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로는 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array) 등이 있다.In general, a semiconductor package includes a lead frame, a structure for mounting a pin and a chip (die) to be electrically connected to the outside, a line connecting the lead frame and the bonding pad, a paddle for mounting the chip, and an encapsulant. Is done. The semiconductor package is classified into a resin sealing package, a tape carrier package (TCP), a glass sealing package, a metal sealing package, etc. according to the sealing material used, and an insert type and a surface mount type (SMT) according to the mounting method. Separated by. Insertable packages include DIP (Dual In-line Package) and PGA (Pin Grid Array), and surface mount types include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier) and CLCC (Ceramic Leaded Chip Carrier). And Ball Grid Array (BGA).
한편, 칩(Die)을 기판(Substrate)에 장착하거나 물리적인 연결방식을 본딩(bonding)이라 하는데, 본딩은 다이 본딩(Die Bonding), 와이어 본딩(Wire Bonding), TAB, 플립칩 본딩(Flip Chip Bonding) 등이 있다. 여기서, 플립칩 본딩은 칩의 접속 패드에 돌기(Dump)를 만들어 PCB 기판에 직접에 접속하는 방식으로 일명 C-4라고도 하며, 선접속 과정이 없고 가장 경박 단소할 뿐만 아니라 집적도나 성능면에서 탁월하여 극소형화되는 전자제품에 널리 각광받고 있는 기술이다.On the other hand, the chip (Die) is mounted on the substrate (Substrate) or the physical connection method is called (bonding), bonding is die bonding (Die Bonding), wire bonding (Wire Bonding), TAB, Flip Chip Bonding (Flip Chip bonding) Bonding). Here, flip chip bonding is called C-4 by making a bump on the chip's connection pad and directly connecting it to the PCB board, and there is no wire connection process, it is the lightest and simplest, and is excellent in integration and performance. It is a technology that is widely spotlighted in the miniaturized electronic products.
도 1은 일반적인 플립칩 본딩을 설명하기 위해 도시한 도면이다.1 is a diagram illustrating a general flip chip bonding.
도 1을 참조하면, 플립칩 본딩은 웨이퍼(10)로부터 절단된 칩(11)의 본딩 패드(12)에 스터드 펌프(stud bump: 13)를 형성한 후 칩(11)을 뒤집어(Flip) 기판(20)상의 리드패드(21)에 직접 접속하는 구조이다. 이때 칩(11)을 세라믹 패키지(도 2의 22)에 플립칩 본딩하는 패키지 타입 플립칩 본딩과, 메인보드(25)상에 직접 플립칩 본딩하는 온보드 타입 플립칩 본딩으로 구분된다.Referring to FIG. 1, in flip chip bonding, a stud pump 13 is formed on a bonding pad 12 of a chip 11 cut from a wafer 10, and then the chip 11 is flipped over to form a substrate. The structure directly connects to the lead pad 21 on (20). In this case, the chip 11 is divided into a package type flip chip bonding for flip chip bonding to a ceramic package (22 of FIG. 2) and an onboard type flip chip bonding for flip chip bonding directly onto the main board 25.
도 2a는 패키지 타입 플립칩 본딩의 예이고, 도 2b는 온보드 타입 플립칩 본딩의 예이다.2A is an example of package type flip chip bonding, and FIG. 2B is an example of onboard type flip chip bonding.
도 2a를 참조하면, 패키지 타입에서 칩(11)은 세라믹 패키지(22)에 플립칩 본딩되어 있고, 이 패키지가 메인보드(25)에 실장되어 있다. 세라믹 패키지(22)는 패키지 뚜껑(23)에 의해 밀봉되어 있으며, 온보드 타입은 칩(11)이 메인보드(25)상에 직접 플립칩 본딩된 후 수지(26) 등에 의해 범프(13) 연결부분이 몰딩되어 있다.Referring to FIG. 2A, in the package type, the chip 11 is flip chip bonded to the ceramic package 22, and the package is mounted on the main board 25. The ceramic package 22 is sealed by the package lid 23, and the onboard type is connected to the bump 13 by the resin 26 after the chip 11 is flip-chip bonded directly onto the main board 25. This is molded.
그런데 이와 같은 종래의 플립칩 본딩은 열압착방식을 사용하므로 공정속도가 느리고, 와이어 본딩은 소형 경박화에 한계성이 있는 문제점이 있다. 특히, 칩이 접착되는 기판이 필름 등과 같이 약하거나 패드가 약한 웨이퍼 등의 경우에는 전기적인 접합성이 저하되는 문제점이 있다.However, since the conventional flip chip bonding uses a thermocompression bonding method, the process speed is low, and wire bonding has a problem in that there is a limit in miniaturization and thinning. In particular, when the substrate to which the chip is bonded is weak such as a film or the wafer having a weak pad, there is a problem in that electrical bonding property is lowered.
본 발명은 상기와 같은 문제점을 해결하기 위하여 제안된 것으로, 공정속도가 빠르고 접합 성능이 향상된 플립칩 패키징 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems, and an object thereof is to provide a flip chip packaging method having a fast process speed and improved bonding performance.
도 1은 일반적인 플립칩 본딩을 설명하기 위해 도시한 도면,1 is a view illustrating a general flip chip bonding;
도 2a는 패키지 타입 플립칩 본딩의 예,2A is an example of a package type flip chip bonding,
도 2b는 온보드 타입 플립칩 본딩의 예,2B is an example of onboard type flip chip bonding,
도 3은 본 발명에 따라 접합성을 향상시키기 위한 플립칩 패키징 방법을 도시한 순서도,3 is a flow chart illustrating a flip chip packaging method for improving bonding in accordance with the present invention;
도 4a,b는 도 3에 도시된 스터드 범프 형성의 예,4a, b are examples of the stud bump formation shown in FIG. 3,
도 5는 도 3에 도시된 테이프 접착의 예,5 is an example of the adhesive tape shown in FIG.
도 6a,b은 도 3에 도시된 웨이퍼 절단 공정의 예,6a, b are examples of the wafer cutting process shown in FIG.
도 7은 본 발명에 따라 서브스트레이트에도 솔더 범프를 형성한 예,7 shows an example in which solder bumps are also formed in the substrate according to the present invention;
도 8a,b,c은 도 3에 도시된 플립칩 본딩 공정의 예,8a, b, and c are examples of the flip chip bonding process shown in FIG.
도 9는 도 3에 도시된 수지 충진 공정의 예.9 is an example of the resin filling process shown in FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10: 웨이퍼 11: 칩(다이)10: wafer 11: chip (die)
12: 본딩 패드 13: 스터드 범프12: Bonding Pad 13: Stud Bump
20: 기판 21,72: 리드패드20: substrate 21,72: lead pad
22: 세라믹 패키지 23: 패키지 뚜껑22: ceramic package 23: package lid
25: 메인보드 52: 접착 테이프25: motherboard 52: adhesive tape
71: 기판 73: 범프71: substrate 73: bump
상기와 같은 목적을 달성하기 위하여 본 발명의 방법은, 웨이퍼에 스터드 범프를 형성하는 범프 형성단계; 웨이퍼의 일면에 테이프를 접착하는 테이프 접착단계; 상기 테이프가 접착된 웨이퍼를 칩 단위로 절단하는 다이싱단계; 기판의 패드에 범프를 형성하는 단계; 상기 기판의 패드에 형성된 범프와 상기 칩의 패드에 형성된 스터드 범프를 열압착 및 초음파를 인가하여 직접 접착하는 플립칩 본딩 단계; 패키지 타입의 본딩일 경우에, 상기 플립칩 본딩 단계에서 칩이 본딩된 세라믹 패키지에 뚜껑을 씌우고 실링하는 단계; 및 온보드 타입의 본딩일 경우에, 상기 플립칩 본딩 단계에서 칩이 본딩된 메인보드에서 칩과 메인보드간의 연결공간을 수지로 충진하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method of the present invention, the bump forming step of forming a stud bump on the wafer; A tape adhesion step of adhering the tape to one surface of the wafer; A dicing step of cutting the tape-attached wafer into chips; Forming bumps on pads of the substrate; A flip chip bonding step of directly bonding the bumps formed on the pads of the substrate and the stud bumps formed on the pads of the chip by thermal compression and ultrasonic waves; In the case of a package type bonding, capping and sealing a ceramic package to which a chip is bonded in the flip chip bonding step; And in the case of the onboard type bonding, filling the connection space between the chip and the main board with a resin in the main board to which the chip is bonded in the flip chip bonding step.
이때, 상기 기판의 범프 사이즈와 칩의 범프 사이즈는 동일하거나 어느 한측이 더 크게 할 수 있고, 본 발명의 방법은 패드가 약한 웨이퍼에 사용되어 칩패드를 손상시키지 않고서도 플립칩 본딩을 할 수 있다.In this case, the bump size of the substrate and the bump size of the chip may be the same or larger on either side, and the method of the present invention may be used for a wafer with a weak pad, so that flip chip bonding may be performed without damaging the chip pad. .
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 자세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 플립칩 패키징 방법의 절차를 도시한 순서도이다.3 is a flowchart illustrating a procedure of a flip chip packaging method according to the present invention.
본 발명에 따른 플립칩 패키징 방법은 도 3에 도시된 바와 같이, 웨이퍼를 입력받아 골드 스터드 범프를 형성하는 단계(S1,S2), 테이프를 접착하는 단계(S3), 웨이퍼를 절단하는 단계(S4), 필름 또는 PCB를 입력받아 리드패드에 범프를 형성하는 단계(S8,S9), 범프가 형성된 필름 혹은 PCB와 스터드 범프가 형성된 플립칩을 접속하는 플립칩 접합단계(S5), 수지를 충진하는 단계(S7), 검사단계(S7)로 이루어진다.In the flip chip packaging method according to the present invention, as shown in FIG. ), The step of forming a bump on the lead pad by receiving the film or PCB (S8, S9), the flip-chip bonding step (S5) for connecting the bump formed film or PCB and the flip chip formed with the stud bump, filling the resin Step S7 and inspection step S7.
도 3을 참조하면, 스터드 범프(Stud Bump)를 형성하는 단계(S2)는 웨이퍼(10)의 알루미늄 패드(12)에 접속을 위한 골드 스터드 범프(Gold Stud Bump)를 형성하는 공정으로서, 도 4에 도시된 바와 같이 웨이퍼 상의 칩들에 구현된 알루미늄 본딩패드에 금으로 된 스터드 범프를 형성한다. 통상, 범프(Bump)의 형태는 알루미늄 패드(12) 위에 길게 돌기가 형성된 형태와 돌기가 낮은 형태가 있다. 도 4를 참조하면, 웨이퍼에는 다수의 칩들이 반도체 제조공정을 통해 제조되어 있고, 각 칩의 본딩 패드에는 스터드 범프가 형성되어 있다.Referring to FIG. 3, step S2 of forming a stud bump is a process of forming a gold stud bump for connection to the aluminum pad 12 of the wafer 10. A gold stud bump is formed on an aluminum bonding pad embodied in chips on a wafer as shown in FIG. In general, bumps have a form in which protrusions are formed on the aluminum pad 12 and low protrusions. Referring to FIG. 4, a plurality of chips are manufactured on a wafer through a semiconductor manufacturing process, and stud bumps are formed on bonding pads of the chips.
테이프를 접착하는 공정(S3)은 범프가 올려진 웨이퍼를 다이싱할 경우에 다이(칩)가 개별적으로 이탈하지 않도록 테이프로 고정해주는 공정이다. 테이프 접착시의 수직 구조는 도 5에 도시된 바와 같이, 양단에 위치한 프레임 링(54)으로테이프(52)를 지지하면서 웨이퍼(10)를 테이프 접착면에 올려 놓아 접착시킨다.The step of adhering the tape (S3) is a process of fixing the tape so that the dies (chips) do not separate individually when dicing the bumped wafer. As shown in FIG. 5, the vertical structure at the time of tape adhesion is supported by placing the wafer 10 on the tape adhesive surface while supporting the tape 52 with the frame rings 54 positioned at both ends thereof.
웨이퍼 절단 공정(S4)은 웨이퍼 상태의 칩들을 절단기(도 6의 60)에 의해 개별적으로 분리하는 공정으로서, 절단시의 측단면도는 도 6에 도시된 바와 같이 절단기(60)의 블레이드(61)가 웨이퍼(10)를 완전히 자르고 테이프(52)는 일부만 잘라 절단된 후에도 테이프(52)에 의해 칩(11)들이 개별적으로 흩어지지 않게 되어 있다. 이와 같이 절단된 상태의 웨이퍼(10)는 도 6의 (나)에 도시된 바와 같은데, 도 6에서 참조번호 63은 웨이퍼의 두께(Wafer Thickness)를 나타내고, 참조번호 64는 절단 깊이(Cut Depth)를 나타내며, 참조번호 65는 인덱스(Index), 참조번호 66은 절단 두께(Cut Width)를 나타낸다.The wafer cutting step S4 is a step of separately separating chips in a wafer state by a cutting machine (60 of FIG. 6), and a side cross-sectional view at the time of cutting is shown by a blade 61 of the cutting machine 60 as shown in FIG. 6. Even after the wafer 10 is completely cut and the tape 52 is partially cut and cut, the chips 11 are not individually scattered by the tape 52. The wafer 10 in the cut state is as shown in FIG. 6B, in which reference numeral 63 denotes a wafer thickness, and reference numeral 64 denotes a cut depth. Reference numeral 65 denotes an index and reference numeral 66 denotes a cut width.
한편, 본 발명에 따라 접합성능을 향상시키기 위해 기판(71)에도 범프(73)를 형성해야 하므로 플립칩 본딩전에 리드패드(72)에 범프(73)를 형성하는 공정을 거쳐야 한다.On the other hand, according to the present invention, the bumps 73 must be formed on the substrate 71 to improve the bonding performance. Therefore, the bumps 73 must be formed on the lead pads 72 before flip chip bonding.
도 7은 본 발명에 따라 기판과 칩에 범프가 각각 형성된 예를 도시한 도면이다.7 illustrates an example in which bumps are formed on a substrate and a chip, respectively, according to the present invention.
도 7을 참조하면, 본 발명에서는 칩(11)에 스터드 범프(13)를 형성함과 아울러 기판(71)에도 범프(73)를 형성하여 범프(13)와 범프(73)가 직접 접합되도록 함으로써 접합특성을 개선한 것이다. 즉, 칩(11)의 본딩패드(12)에 스터드 범프(13)가 형성되어 있고, 기판(71)의 리드패드(72)에도 범프(73)가 형성된 것을 알 수 있다.Referring to FIG. 7, in the present invention, the stud bump 13 is formed on the chip 11 and the bump 73 is formed on the substrate 71 so that the bump 13 and the bump 73 are directly bonded to each other. The bonding characteristics are improved. That is, it can be seen that the stud bumps 13 are formed on the bonding pads 12 of the chip 11, and the bumps 73 are also formed on the lead pads 72 of the substrate 71.
플립칩 접합공정(S5)은 골드 스터드 범프된 칩(11)을 세라믹 기판이나 PCB등에 접착하는 공정이다. 본 발명에 따른 플립칩 접착공정(S5)에서는 기판(71)에는 히팅수단을 통해 열을 가하고 칩(11)에는 툴에 의해 초음파를 인가함과 아울러 기판측으로 압력을 가해 양 범프(13,73)가 열(heat), 초음파(Ultra sonic), 및 압력(Pressure)에 의해 발생된 에너지로 접합시켜준다. 이와 같이 본 발명에서는 기존의 열압착 플립칩 공법과 달리 열압착과 동시에 초음파를 가해줌으로써 종래보다 공정시간을 단축할 수 있는 잇점이 있다.The flip chip bonding step S5 is a step of bonding the gold stud bumped chip 11 to a ceramic substrate or a PCB. In the flip chip bonding process S5 according to the present invention, heat is applied to the substrate 71 through a heating means, and ultrasonic waves are applied to the chip 11 by a tool, and pressure is applied to the substrate side so that both bumps 13 and 73 are applied. Bonding with energy generated by heat, ultra sonic, and pressure. Thus, in the present invention, unlike the conventional thermocompression flip chip method, by applying ultrasonic waves at the same time as the thermocompression method, there is an advantage that the process time can be shorter than the conventional method.
도 8은 도 3에 도시된 플립칩 본딩 공정의 예이고, 도 9는 도 3에 도시된 수지 충진(몰딩) 공정의 예이다.8 is an example of the flip chip bonding process illustrated in FIG. 3, and FIG. 9 is an example of the resin filling (molding) process illustrated in FIG. 3.
도 8을 참조하면, (가)는 칩(11)에 있는 범프(13)를 기판(71)의 범프(73)보다 크게 형성하여 접합한 경우를 도시한 것이고, (나)는 칩(11)의 범프(13)와 기판(71)의 범프(73)의 크기가 동일한 경우의 접합을 도시한 것이며, (다)는 기판의 범프(13)를 칩의 범프(73)보다 크게 형성하여 접합한 경우를 도시한 것이다.Referring to FIG. 8, (a) illustrates a case where the bump 13 of the chip 11 is formed to be larger than the bump 73 of the substrate 71 to be joined, and (b) the chip 11. Shows a case where the bump 13 of the bump 13 and the bump 73 of the substrate 71 have the same size, and (c) shows that the bump 13 of the substrate is formed to be larger than the bump 73 of the chip. The case is shown.
이와 같이 칩의 범프(13)와 기판의 범프(73)는 크기와 종류를 달리하여 접합할 수 있다.As described above, the bump 13 of the chip and the bump 73 of the substrate may be joined in different sizes and types.
이어 플립칩 본딩 공정(S5) 후에 접합공간에 수지를 충진하여 칩을 보호한다(S6). 도 9는 댐(91)을 이용함과 아울러 기판(71)과 칩(11) 양측에 범프(13,73)를 각각 형성하여 접합한 것을 몰딩(93)한 예이다.Subsequently, after the flip chip bonding process S5, a resin is filled in the bonding space to protect the chip (S6). 9 shows an example of molding 93 using a dam 91 and forming bumps 13 and 73 on both sides of the substrate 71 and the chip 11, respectively.
이상에서 설명한 바와 같이, 본 발명에 따르면 플립칩 본딩을 함에 있어서열압착에 초음파를 부가하여 공정을 신속하게 처리할 수 있고, 특히 칩측에 스터드 범프를 형성함과 아울러 기판측에도 범프를 형성하여 양 범프를 직접 접합함으로써 접합특성을 크게 향상시킬 수 있는 효과가 있다. 즉, 본 발명은 Au(Al) gold bump또는 Au stud bump와 Au stud bump를 직접 연결하여 intermetalic을 형성함으로써 전기적 신뢰성 확보가 용이하고, 이미지 센서 등 패드가 약한 웨이퍼에 사용하여 칩 패드를 손상시키지 않고 플립칩 본딩을 할 수 있다.As described above, according to the present invention, in the case of flip chip bonding, ultrasonic waves can be added to thermocompression to quickly process the process, and in particular, stud bumps are formed on the chip side and bumps are also formed on the substrate side. By directly bonding, there is an effect that can greatly improve the bonding characteristics. That is, the present invention can easily secure electrical reliability by forming an intermetalic by directly connecting Au (Al) gold bumps or Au stud bumps and Au stud bumps, without damaging the chip pads by using them on wafers with weak pads such as image sensors. Flip chip bonding is possible.
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| KR1020030018593A KR20040083899A (en) | 2003-03-25 | 2003-03-25 | Flip Chip Packaging Method for Enhancing the Performance of Connection |
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