KR20040069843A - Fabrication method of gate in semiconductor device - Google Patents
Fabrication method of gate in semiconductor device Download PDFInfo
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- KR20040069843A KR20040069843A KR1020030006396A KR20030006396A KR20040069843A KR 20040069843 A KR20040069843 A KR 20040069843A KR 1020030006396 A KR1020030006396 A KR 1020030006396A KR 20030006396 A KR20030006396 A KR 20030006396A KR 20040069843 A KR20040069843 A KR 20040069843A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Abstract
Description
본 발명은 반도체 소자에 관한 것으로, 더욱 상세하게는 게이트를 형성하는 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method of forming a gate.
일반적으로 모스 트랜지스터는 필드 효과 트랜지스터(field effect transistor, FET)의 일종으로, 반도체 기판에 형성된 소스, 드레인 영역과, 이 소스, 드레인 영역이 형성된 반도체 기판 상에 게이트 산화막과 게이트가 형성된 구조를 가진다. 이러한 모스 트랜지스터의 구조에서 전극인 소스, 드레인, 게이트 상부에는 각각 전기적 신호를 인가하기 위한 금속 배선이 연결되어 소자를 작동시킨다.In general, a MOS transistor is a type of field effect transistor (FET), and has a structure in which a gate oxide film and a gate are formed on a source and drain region formed in a semiconductor substrate, and a semiconductor substrate on which the source and drain regions are formed. In the structure of the MOS transistor, metal wires for applying an electrical signal are connected to the source, the drain, and the gate, respectively, to operate the device.
게이트를 형성하기 위해서는 도 1에 도시된 바와 같이, 반도체 기판의 구조물(1) 상에 형성된 게이트 산화막(2) 상에 다결정실리콘층을 형성한 후, 다결정실리콘층을 선택적으로 식각하여 목적하는 게이트(3)의 폭으로 남긴다.In order to form the gate, as shown in FIG. 1, after the polysilicon layer is formed on the gate oxide film 2 formed on the structure 1 of the semiconductor substrate, the polycrystalline silicon layer is selectively etched to form a desired gate ( Leave to the width of 3).
이와 같이 다결정실리콘층을 선택적으로 식각할 때에는 설계된 패턴을 가지는 마스크를 이용하여 동일층의 다결정실리콘층으로부터 이웃하는 여러 개의 게이트를 동시에 형성한다.As described above, when selectively etching the polysilicon layer, a plurality of neighboring gates are simultaneously formed from the same polysilicon layer using a mask having a designed pattern.
그런데, 패턴 밀도가 서로 다를 경우, 즉 패턴이 밀한 지역과 소한 지역 사이에서 식각속도가 서로 다른, 이른바 로딩효과(loading effect)에 의해 다결정실리콘층이 깨끗하게 식각되지 못하는 문제점이 있었다.However, when the pattern density is different, that is, the polysilicon layer may not be etched cleanly by a so-called loading effect, which has different etching speeds between the dense and small areas.
즉, 패턴이 소한 지역에서는 식각속도가 빨라서 다결정실리콘층이 모두 식각되고 그 하부의 게이트 산화막이 노출된 반면에, 패턴이 밀한 지역에서는 다결정실리콘층이 미처 다 식각되지 못하고 남아있는 상태이다.That is, in the region where the pattern is small, the etching speed is high, so that all of the polysilicon layers are etched and the gate oxide film under the exposed portion is exposed, whereas in the region where the pattern is dense, the polysilicon layer is not etched.
이 때 측벽 폴리머의 생성방법이 패턴이 소한 지역에서는 전반적으로 패시베이션(passivation)을 해주지만 패턴이 밀한 지역에서는 폴리머가 아닌 다결정실리콘층이 남아있어 이를 과식각에서 패시베이션 역할을 해주지 못해서 노치(notch)가 발생하는 문제점이 있었다.At this time, the formation method of the sidewall polymer is generally passivation in the area where the pattern is small, but the polysilicon layer, not the polymer, is left in the area where the pattern is dense, and thus the notch is not passivated. There was a problem that occurred.
또한, 폴리머 증착의 차이로 인해 결과적으로 형성된 게이트의 측벽이 수직으로 깨끗하게 형성되지 못하고 소정 부분 잔류하는 푸트(foot)를 유발하는 문제점이 있었다.In addition, due to the difference in polymer deposition, there is a problem that the resulting sidewall of the gate is not formed vertically clean and causes a foot to remain in a predetermined portion.
이와 같이 게이트의 측벽에 노치나 푸트가 발생하면 동일한 폭 치수를 가지는 게이트라 할지라도 채널의 길이가 짧아지거나 혹은 길어지게 되어, 결국 동작전압에 영향을 주게 되어 소자의 오동작을 유발하는 등 소자의 신뢰성이 저하되는 문제점이 있었다.When notches or feet occur on the sidewalls of the gate, even if the gates have the same width, the channel length becomes shorter or longer, which in turn affects the operating voltage, causing malfunction of the device. There was a problem of this deterioration.
특히 소자의 고집적화 추세에 따라 게이트의 폭이 작아짐에 따라 노치로 인해 쇼트 채널 효과를 초래하는 큰 문제점을 보이고 있다.In particular, as the gate width decreases according to the trend toward higher integration of devices, a short channel effect is caused due to notches.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 다결정실리콘층을 선택적으로 식각하여 게이트를 형성할 때 게이트의 측벽이 수직모양으로 깨끗하게 식각되고 잔류물이 남지않도록 하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to ensure that the sidewalls of the gate are etched cleanly in a vertical shape and no residue is left when the gate is formed by selectively etching the polysilicon layer.
본 발명의 또 다른 목적은 반도체 소자의 신뢰성을 향상시키는 것이다.Another object of the present invention is to improve the reliability of a semiconductor device.
도 1은 종래 반도체 소자의 게이트 형성 방법을 도시한 단면도이고,1 is a cross-sectional view showing a gate forming method of a conventional semiconductor device,
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a gate forming method of a semiconductor device according to the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 다결정 SiGe층을 식각종료층으로 사용하는 특징이 있다.In order to achieve the above object, the present invention has a feature of using a polycrystalline SiGe layer as an etching termination layer.
즉, 본 발명에 따른 반도체 소자의 게이트 형성 방법은, 반도체 기판의 구조물 상에 게이트산화막을 형성하는 단계; 게이트산화막 상에 게이트로 작용할, Si 씨드층, SiGe층 및 다결정실리콘층을 순차적으로 형성하는 단계; 다결정실리콘층 상에 감광막 패턴을 형성하는 단계; 감광막 패턴을 마스크로 하여 노출된 다결정실리콘층을 식각하되, SiGe층을 식각종료층으로 사용하여 SiGe층이 노출되면 식각을 종료하는 단계; 식각 종료 후 잔존하는 SiGe층 및 Si 씨드층을 과식각하여 제거하는 단계를 포함하여 이루어진다.That is, the method for forming a gate of a semiconductor device according to the present invention comprises the steps of: forming a gate oxide film on the structure of the semiconductor substrate; Sequentially forming a Si seed layer, a SiGe layer, and a polysilicon layer to serve as a gate on the gate oxide film; Forming a photoresist pattern on the polysilicon layer; Etching the exposed polycrystalline silicon layer using the photoresist pattern as a mask, and ending the etching when the SiGe layer is exposed using the SiGe layer as an etch stop layer; After etching is complete, including the step of over-etching and removing the remaining SiGe layer and Si seed layer.
이하, 본 발명에 따른 반도체 소자의 게이트 형성 방법을 도 2a 내지 2c를참조하여 설명한다.Hereinafter, a method of forming a gate of a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2C.
먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11) 상에 게이트 산화막(12)을 형성한 후, 게이트 산화막(13) 상에 Si 씨드층(13)을 20-50Å 정도의 두께로 형성하고, 연속적으로 Si 씨드층(13) 상에 다결정 SiGe층(14)을 50-150Å 정도의 두께로 형성한 다음, 다결정 SiGe층(14) 상에 다결정실리콘층(15)을 약 2000-3000Å 정도의 두께로 형성한다.First, as shown in FIG. 2A, after the gate oxide film 12 is formed on the silicon wafer 11, the Si seed layer 13 is formed on the gate oxide film 13 to a thickness of about 20 to 50 kPa. The polycrystalline SiGe layer 14 is continuously formed on the Si seed layer 13 to a thickness of about 50-150 GPa, and then the polycrystalline silicon layer 15 on the polycrystalline SiGe layer 14 is about 2000-3000 GPa. Form to thickness.
바람직하게는 Si 씨드층(13)을 50Å의 두께로 형성하고, 다결정 SiGe층(14)을 100Å의 두께로 형성하며, 다결정실리콘층(15)을 2500Å의 두께로 형성한다.Preferably, the Si seed layer 13 is formed to a thickness of 50 GPa, the polycrystalline SiGe layer 14 is formed to a thickness of 100 GPa, and the polycrystalline silicon layer 15 is formed to a thickness of 2500 GPa.
이어서, 다결정실리콘층(15) 상에 감광막을 도포하고 노광 및 현상하여 감광막 패턴(16)을 형성한다.Subsequently, a photosensitive film is coated on the polysilicon layer 15, exposed and developed to form a photosensitive film pattern 16.
다음, 도 2b에 도시된 바와 같이, 감광막 패턴(16)을 마스크로 하여 노출된 다결정실리콘층(15)을 식각하며, 이 때 다결정 SiGe층(14)을 식각종료층을 사용한다. 즉, Ge 파장에서 식각종료점을 검출하도록 하여 게이트산화막(12)이 노출되기 전에 식각을 종료한다.Next, as illustrated in FIG. 2B, the exposed polycrystalline silicon layer 15 is etched using the photoresist pattern 16 as a mask, and at this time, the etch finish layer is used as the polycrystalline SiGe layer 14. That is, the etching end point is detected at the Ge wavelength so that the etching is terminated before the gate oxide film 12 is exposed.
다음, 도 2c에 도시된 바와 같이, 게이트산화막(12)이 노출될 때까지 과식각을 진행하여 다결정 SiGe층(14) 및 Si 씨드층(13)을 식각한 후, 감광막 패턴(16)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2C, the polycrystalline SiGe layer 14 and the Si seed layer 13 are etched by over-etching until the gate oxide film 12 is exposed, and then the photoresist pattern 16 is removed. And cleaning process.
이와 같이, 다결정 SiGe층(14)을 식각종료층을 사용하여 식각을 종료한 후, 과식각하여 나머지 다결정 SiGe층(14) 및 Si 씨드층(13)을 제거하면, 형성되는 게이트의 측벽이 수직으로 깨끗하게 식각된다.In this manner, after the etching of the polycrystalline SiGe layer 14 is finished using the etch stop layer and overetched to remove the remaining polycrystalline SiGe layer 14 and the Si seed layer 13, the sidewalls of the gate to be formed are vertical. It is etched cleanly.
상술한 바와 같이, 본 발명에서는 다결정 SiGe층을 식각종료층으로 사용하므로, 형성되는 게이트의 측벽이 수직으로 깨끗하게 식각되고 잔류물이 남지 않는 효과가 있다.As described above, in the present invention, since the polycrystalline SiGe layer is used as the etch stop layer, the sidewalls of the gate to be formed are etched vertically and cleanly, leaving no residue.
따라서, 반도체 소자의 신뢰성을 향상시키는 효과가 있다.Therefore, there is an effect of improving the reliability of the semiconductor device.
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