KR20040066678A - A capacitor fabrication method of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to make uniform the area of a lower electrode formed in or between semiconductor substrates and maximize the area of the lower electrode by preventing a molding layer from being lost in forming the lower electrode. CONSTITUTION: A molding layer and an etch stop layer are sequentially formed on a semiconductor substrate(100). The etch stop layer and the molding layer are continuously patterned to form storage node holes(135) exposing predetermined regions of the semiconductor substrate. A lower electrode layer(140a) is conformally formed on the semiconductor substrate with the storage node holes. A sacrificial layer is formed on the lower electrode layer to fill the storage node holes. The sacrificial layer and the lower electrode layer are continuously planarized until the etch stop layer is exposed so that cylindrical storage nodes are formed in the storage node holes while sacrificial layer patterns are left in the storage nodes. At least the sacrificial layer patterns are eliminated to expose the inner walls of the storage nodes.

Description

A CAPACITOR FABRICATION METHOD OF A SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device.

Among semiconductor devices, DRAMs employ capacitors as data storage elements. That is, the unit cell of the DRAM is composed of one access transistor and one cell capacitor connected in series. The cell capacitor includes a lower electrode (storage electrode) electrically connected to a source region of the access transistor, a dielectric film stacked on the lower electrode, and an upper electrode (plate electrode) stacked on the dielectric film. Therefore, in order to implement a high performance DRAM, the capacity of the capacitor must be increased. However, as the integration degree of the DRAM increases, the area occupied by the unit cell is gradually decreasing. Accordingly, the area occupied by the unit cell is also reduced.

Recently. Techniques for increasing the surface area of the storage electrode have been widely used to increase the capacity of the cell capacitor. For example, CYL INDER-SHAPED storage electrodes are widely adopted for highly integrated DRAMs. In this case, the height of the cylindrical storage electrode is directly related to its capacity.

1A and 1B are cross-sectional views illustrating a conventional capacitor manufacturing method employing a cylindrical storage electrode.

Referring to FIG. 1A, an insulating film 15 is formed on the semiconductor substrate 10. The insulating layer 15 is patterned to form a plurality of buried contact holes 20 exposing predetermined regions of the semiconductor substrate 10. Buried contact plugs 25 may be formed to fill the buried contact holes 20. An etch stop layer 30 and a molding layer 35 are sequentially formed on the entire surface of the semiconductor substrate having the buried contact plugs 25. The molding layer 35 and the etch stop layer 30 are successively patterned to form storage node holes 40 exposing the buried contact plugs 25. A conformal lower electrode layer 45 is formed on the entire surface of the semiconductor substrate 10 having the storage node holes 40.

Referring to FIG. 1B, a sacrificial layer (not shown) filling the storage node holes 40 may be formed on an entire surface of the semiconductor substrate 10 having the lower electrode layer 45. Subsequently, the sacrificial layer and the lower electrode layer 45 are continuously etched back to form cylindrical storage nodes 45a isolated from each other in the storage node holes 40. As a result, sacrificial layer patterns 50 remain in the storage nodes 45a.

The lower electrode layer 45 and the molding layer 35 may be over-etched during the etch back process. Due to such excessive etching, a molding film 35a having a non-uniform thickness remains throughout the semiconductor substrate 10. In addition, the storage nodes 45a also have non-uniform heights throughout the semiconductor substrate 10 due to the transient etching.

As described above, according to the related art, storage nodes 45a having non-uniform heights are formed throughout the semiconductor substrate 10. As a result, it is difficult to form cell capacitors with uniform capacitance on the semiconductor substrate 10.

An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of forming storage nodes having a uniform capacitance over the entire semiconductor substrate.

1A and 1B are sectional views illustrating a conventional capacitor manufacturing method employing a cylindrical storage electrode.

FIG. 2A is a cross-sectional view of a method of manufacturing a capacitor of a semiconductor device, in which a molding film and an etch stop film are formed on a semiconductor substrate. FIG.

2B is a cross-sectional view of a method of manufacturing a capacitor of a semiconductor device, in which storage node holes (HOLEs) are formed in a semiconductor substrate.

2C is a cross-sectional view in which a lower electrode film and a sacrificial film are formed on a semiconductor substrate in the capacitor manufacturing method of the semiconductor device according to the present invention;

2D is a cross-sectional view of an etch stop layer exposed on a semiconductor substrate in the method of manufacturing a capacitor of the semiconductor device according to the present invention.

2E is a cross-sectional view in which a storage node is formed on a semiconductor substrate in the capacitor manufacturing method of the semiconductor device according to the present invention.

(Code description for main part of drawing)

100: semiconductor substrate, 105: insulating film

110: buried contact hole 115: buried contact plug

120: stuffer film 125: molding film

130: etch stop 135: storage node holes

140 and 140a: lower electrode layer 140b: storage node

145: sacrificial film 145a: sacrificial film pattern

In order to achieve the above technical problem, the present invention provides a capacitor manufacturing method of a semiconductor device.

In the method of manufacturing a capacitor of the semiconductor device, a molding layer and an etch stop layer are sequentially formed on a semiconductor substrate, and the etch stop layer and the molding layer are successively patterned to expose predetermined regions of the semiconductor substrate, and Sequentially depositing a lower electrode layer and a sacrificial layer on the etch stop layer, and continuously planarizing the sacrificial layer and the lower electrode layer until the etch stop layer is exposed to form cylindrical storage nodes in the storage node holes. At the same time, the sacrificial layer patterns are left in the storage nodes, and at least the sacrificial layer patterns are removed to expose inner walls of the storage nodes.

And etching the etch stop layer and the molding layer to expose outer walls of the storage node, wherein the stuffer layer serves as a buffer when etching the etch stop layer, the molding layer, and the sacrificial layer to form the storage nodes. Do it.

Before forming the molding layer and the etch stop layer, an insulating film is formed on the semiconductor substrate, buried contact holes penetrating the insulating film are formed, a buried contact plug is filled in the buried contact hole, and the And forming a stuffer film on the insulating film and the buried contact plug.

In addition, the stuffer layer serves as a buffer layer to block excessive etching of the insulating layer when the storage node hole is formed, and the etch stop layer serves as a buffer layer to block etching of the molding layer when the sacrificial layer pattern is formed. do. The etch stop layer is preferably deposited thicker than the stuffer layer.

The planarization of the sacrificial film and the lower electrode film is preferably performed by a chemical mechanical polishing technique. Alternatively, the planarization of the sacrificial film and the lower electrode film may be performed by an etch back technique.

The stuffer layer and the etch stop layer may be a material layer having an etching rate different from that of the molding layer. For example, the stuffer layer and the etch stop layer are silicon nitride layers. The sacrificial film is preferably a silicon oxide film.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an insulating film 105 is formed on a semiconductor substrate 100 and buried contact holes 110 penetrating the insulating film 105 are formed. The buried contact holes 110 are filled with buried contact plugs 115. Subsequently, a stuffer layer, a molding layer, and an etch stop layer 120, 125, and 130 are sequentially deposited on the insulating layer 105 and the buried contact plugs 115.

The buried contact holes 110 may be filled with the buried contact plugs 115 by forming and etching back a doped polysilicon film (not shown) on the insulating layer 105.

The molding film 125 may be formed by sequentially stacking a BPSG (BORO-PHOSPHO SILICATE GLASS) film and a TEOS (TETRA-ETHYL-ORTHO-SILICATE) film, or vice versa.

The stuffer layer 120 and the etch stop layer 130 may be formed of a material layer having an etching rate different from that of the molding layer 125. For example, the stuffer layer 120 and the etch stop layer 130 are silicon nitride layers.

Referring to FIG. 2B, the etch stop layer, the molding layer, and the stuffer layer 130, 125, and 120 of FIG. 2A are sequentially etched to form storage node holes 135 that expose the buried contact plugs 115.

The formation order of the storage node holes 135 is as follows. First, photoresist patterns (not shown) are formed on the etch stop layer 130. Subsequently, the etch stop layer 130 and the molding layer 125 are removed until the stuffer layer 120 is exposed in the photoresist pattern. In this case, the stuffer layer 120 serves as a buffer layer that prevents the insulating layer 105 from being excessively etched when the storage node hole 135 is formed. Subsequently, after removing the photoresist pattern, the stuffer layer 120 is removed until the insulating layer 105 is exposed using the etch stop layer 130 and the molding layer 125 as a mask.

The etch stop layer 130 should remain on the molding layer 125 until all of the stuffer layers 120 are etched in the storage node holes 135.

Therefore, when the etch stop layer 130 and the stuffer layer 125 are formed of the same material layer, the etch stop layer 130 is preferably thicker than the stuffer layer 125.

Referring to FIG. 2C, the lower electrode layer 140 and the sacrificial layer 145 are sequentially deposited on the entire surface of the semiconductor substrate 100 having the storage node holes 135 of FIG. 2B.

The lower electrode layer 140 is a doped polysilicon layer, and the lower electrode layer 140 is formed in the storage node holes 135 and the etch stop layer 130 of FIG. 2B. The buried contact plugs 115 are connected to each other. In addition, the sacrificial layer 145 may be formed of a silicon oxide layer.

Referring to FIG. 2D, the sacrificial layer 145 and the lower electrode layer 140 of FIG. 2C are planarized until the etch stop layer is exposed, so that the cylindrical storage nodes are separated from each other in the storage node holes 135. 140a). Accordingly, sacrificial layer patterns 145 remain in the storage nodes 140a. As a result, the etch stop layer 130 prevents the molding layer 130 from being etched during the etch back process for forming the storage nodes 140a. That is, the etch stop layer 130 serves as a buffer layer that prevents etching of the molding layer 130 when the sacrificial layer pattern 145 is formed.

Thus, the molding film 130 still has its initial thickness, and the storage nodes 140a have uniform heights throughout the semiconductor substrate. In addition, the process of planarizing the sacrificial layer 145 and the lower electrode layer 140 may be performed using an etch back technique or a chemical mechanical polishing technique.

Referring to FIG. 2E, the sacrificial layer patterns 145 of FIG. 2D are selectively removed to expose inner walls of the storage nodes 140a. Alternatively, the etching stop layer 130 is removed to expose the molding layer 125 between the storage nodes 140a and the sacrificial layer patterns 145 and the molding layer 125 are removed. Inner walls and outer walls of the storage nodes 140a may be exposed.

The sacrificial layer patterns 145a and the molding layer 125 may be removed using an oxide etching solution, and the etch stop layer 130 may be removed using a phosphoric acid solution.

As described above, the semiconductor device manufacturing method according to the present invention prevents the loss of the molding film by etching during the formation of the lower electrode to make the area of the lower electrode formed in the semiconductor substrate or between the semiconductor substrates uniform. The area of the semiconductor device can be maximized and the performance of the semiconductor device can be improved by increasing the capacitance of the capacitor in the semiconductor device.

Claims (8)

A molding film and an etch stop film are sequentially formed on the semiconductor substrate, Successively patterning the etch stop layer and the molding layer to form storage node holes exposing predetermined regions of the semiconductor substrate, Forming a conformal lower electrode film on an entire surface of the semiconductor substrate having the storage node holes, Forming a sacrificial layer filling the storage node holes on the lower electrode layer; Continuously planarize the sacrificial layer and the lower electrode layer until the etch stop layer is exposed, thereby forming cylindrical storage nodes in the storage node holes, and leaving sacrificial layer patterns in the storage nodes; Exposing at least one of the sacrificial layer patterns to expose inner walls of the storage nodes. The method of claim 1, Before forming the molding layer and the etch stop layer, An insulating film is formed on the semiconductor substrate, Forming buried contact holes penetrating the insulating film, Filling the buried contact plugs in the buried contact hole; Further comprising forming a stuffer film on the insulating film and the buried contact plug, The stuffer layer is etched while forming the storage node holes. And the storage node holes expose the buried contact plugs. The method of claim 1, At least the process of removing the sacrificial layer patterns Exposing the molding layer by removing the etch stop layer between the storage nodes, And removing the sacrificial layer pattern and the exposed molding layer to expose the outer wall together with the inner walls of the storage nodes. The method of claim 2, And the stuffer layer serves as a buffer layer to prevent excessive etching of the insulating layer when the storage node hole is formed. The method of claim 1, And the etch stop layer serves as a buffer layer to block etching of the molding layer when the storage nodes are formed. The method of claim 2, And the etch stop layer is deposited thicker than the stuffer layer. The method of claim 1, And planarization of the sacrificial layer and the lower electrode layer is performed by a chemical mechanical polishing technique. The method of claim 1, Planarization of the sacrificial layer and the lower electrode layer is performed by an etch back technique.