KR20040060545A - pad aluminum structure of semiconductor device and its processing method - Google Patents
pad aluminum structure of semiconductor device and its processing method Download PDFInfo
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- KR20040060545A KR20040060545A KR1020020087352A KR20020087352A KR20040060545A KR 20040060545 A KR20040060545 A KR 20040060545A KR 1020020087352 A KR1020020087352 A KR 1020020087352A KR 20020087352 A KR20020087352 A KR 20020087352A KR 20040060545 A KR20040060545 A KR 20040060545A
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- aluminum
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 238000003672 processing method Methods 0.000 title claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 81
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000004140 cleaning Methods 0.000 claims abstract description 17
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 14
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 229920000642 polymer Polymers 0.000 claims abstract description 11
- XYVAYAJYLWYJJN-UHFFFAOYSA-N 2-(2-propoxypropoxy)propan-1-ol Chemical compound CCCOC(C)COC(C)CO XYVAYAJYLWYJJN-UHFFFAOYSA-N 0.000 claims abstract description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims abstract description 4
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 26
- 239000011241 protective layer Substances 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 15
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000243 solution Substances 0.000 claims description 10
- 239000008367 deionised water Substances 0.000 claims description 6
- 229910021641 deionized water Inorganic materials 0.000 claims description 6
- 238000005406 washing Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 2
- GOOHAUXETOMSMM-UHFFFAOYSA-N Propylene oxide Chemical compound CC1CO1 GOOHAUXETOMSMM-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- SZXQTJUDPRGNJN-UHFFFAOYSA-N dipropylene glycol Chemical compound OCCCOCCCO SZXQTJUDPRGNJN-UHFFFAOYSA-N 0.000 claims 1
- 239000011259 mixed solution Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- -1 Ammonium fluoride N, N-dimethyl acetamide Dipropylene glycol monopropyl ether Chemical compound 0.000 description 1
- ZKGNPQKYVKXMGJ-UHFFFAOYSA-N N,N-dimethylacetamide Chemical compound CN(C)C(C)=O.CN(C)C(C)=O ZKGNPQKYVKXMGJ-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000007983 Tris buffer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000000449 nitro group Chemical group [O-][N+](*)=O 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
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Abstract
Description
본 발명은 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법에 관한 것으로, 보다 상세하게 설명하면 소정 화학 용액으로 세정(wet) 처리를 하여 패드 알루미늄 위의 C 및 F를 제거함과 동시에 표면에 산화막이 형성되도록 하여 더 이상의 산화를 억제할 수 있는 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법에 관한 것이다.The present invention relates to a pad aluminum structure of a semiconductor device and a method for treating the same. More specifically, the present invention relates to a wet chemical treatment with a predetermined chemical solution to remove C and F on the pad aluminum and to form an oxide film on the surface thereof. The present invention relates to a pad aluminum structure of a semiconductor device capable of further suppressing oxidation, and a method of treating the same.
도1a 및 도1b를 참조하면, 종래 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법이 순차 도시되어 있다.1A and 1B, a pad aluminum structure of a conventional semiconductor device and a processing method thereof are sequentially shown.
도1a에 도시된 바와 같이, 각종 반도체 소자가 형성된 실리콘 서브스트레이트(2')의 표면에는 최종적으로 패드 알루미늄(4')이 형성되며, 그 표면에는 제조 공정중 패드 알루미늄(4')의 갈바닉 현상 등을 억제하기 위해 TiN(6')가 형성되어 있다. 또한, 상기 패드 알루미늄(4')의 표면에는 통상 실리콘 산화막 또는 질화막으로 절연층(8')이 형성되어 있고, 패키징 공정시까지 와이어 본딩하는데 오랜 시간 경과할 경우에는 폴리이미드 또는 폴리벤조액솔 등의 보호층(10')이 더 형성되어 있다.As shown in Fig. 1A, the pad aluminum 4 'is finally formed on the surface of the silicon substrate 2' on which various semiconductor elements are formed, and the galvanic phenomenon of the pad aluminum 4 'during the manufacturing process is formed on the surface thereof. TiN 6 'is formed to suppress the back and the like. In addition, an insulating layer 8 'is usually formed on the surface of the pad aluminum 4' with a silicon oxide film or a nitride film, and when a long time passes for wire bonding until the packaging process, a polyimide or a polybenzoxol The protective layer 10 'is further formed.
이어서, 도1b에 도시된 바와 같이 소정 식각액으로 상기 보호층(8') 및 절연층(10')이 식각되고, 상기 TiN(6')도 식각되어 순수한 패드 알루미늄(4')이 노출될 때까지 식각 공정이 진행되며, 상기와 같이 외부로 노출된 순수한 패드 알루미늄(4')에 패키징 공정에서 와이어 본딩이 수행된다.Subsequently, when the protective layer 8 'and the insulating layer 10' are etched with a predetermined etchant, and the TiN 6 'is also etched as shown in FIG. 1B, the pure pad aluminum 4' is exposed. The etching process is performed until the wire bonding is performed in the packaging process on the pure pad aluminum 4 'exposed to the outside as described above.
한편, 이러한 패드 알루미늄(4')은 보호층(8') 및 절연층(10')의 식각시 CxFy계 가스를 사용하는데, 여기서 발생되는 C기 및 F기 폴리머(14')가 상기 패드 알루미늄(4') 표면에 존재함으로써, 상기 패드 알루미늄(4')의 표면을 지속적으로 부식시키는 단점이 있다.Meanwhile, the pad aluminum 4 'uses CxFy-based gas for etching the protective layer 8' and the insulating layer 10 ', and the C and F group polymers 14' generated from the pad aluminum 4 ' By being present at the 4 'surface, there is a disadvantage that the surface of the pad aluminum 4' is continuously eroded.
즉, 도2의 AES(Auger Electron Spectroscopy) 결과를 참조하면, 상기 패드 알루미늄(4')에는 알루미늄(Al) 및 산화막(O) 뿐만 아니라, 탄소(C) 및 불소(F)와 같은 원소가 확인됨으로써, 다수의 C기 및 F기 폴리머(14')가 존재함을 알 수 있다.That is, referring to the AES (Auger Electron Spectroscopy) results of FIG. 2, not only aluminum (Al) and oxide film (O) but also elements such as carbon (C) and fluorine (F) are identified in the pad aluminum 4 ′. As a result, it can be seen that a large number of C and F group polymers 14 'are present.
더불어, 도3a를 참조하면, 종래 반도체 소자의 패드 알루미늄 구조에서 깊이별 원소 분포에 대한 그래프가 도시되어 있고, 도3b를 참조하면, 열처리후의 깊이별 원소 분포에 대한 그래프가 도시되어 있다.In addition, referring to FIG. 3A, a graph of element distribution by depth in a pad aluminum structure of a conventional semiconductor device is illustrated. Referring to FIG. 3B, a graph of element distribution by depth after heat treatment is illustrated.
먼저 도3a에 도시된 바와 같이 종래 패드 알루미늄 구조는 표면에서 알루미늄(Al)과 산화막(O)의 비율이 유사하며, 약 10Å 정도에서 산화막(O)에 비해 알루미늄(Al)의 비율이 월등히 높아짐으로써, 상기 산화막이 너무 얇게 형성되어 패드 알루미늄을 적절하게 보호하지 못함을 알 수 있다.First, as shown in FIG. 3A, the ratio of aluminum (Al) and oxide film (O) is similar on the surface, and the ratio of aluminum (Al) is significantly higher than that of oxide film (O) at about 10 kPa. It can be seen that the oxide film is formed too thin to adequately protect the pad aluminum.
또한, 도3b에 도시된 바와 같이 열처리 후에는, 표면에서 알루미늄(Al)과 산화막(O)의 비율이 유사하며, 또한 약 70~80Å 정도에서 산화막에 비해 알루미늄의 비율이 현저히 높아 짐으로써, 상기 산화막이 너무 두꺼워 테스트 프로브(test probe)로 소자의 특성 검사시 검사 실패가 자주 발생하는 문제가 있다.In addition, after the heat treatment, as shown in Figure 3b, the ratio of aluminum (Al) and oxide film (O) on the surface is similar, and the ratio of aluminum is significantly higher than that of the oxide film at about 70 ~ 80Å Since the oxide film is too thick, there is a problem that a test failure occurs frequently when examining the characteristics of the device with a test probe.
종래 이러한 C기 및 F기 폴리머 제거 및 적절한 두께로 표면 산화막을 형성시키는 방법으로는 UV 오존 처리를 통해 부식 저항을 증가시키려는 시도가 있었으나, 표면 막의 균일한 두께 조절이 곤란한 문제가 있다. 이밖에도 MPA(Methyl-Phosphonic Acid)와 NTMP(Nitro Tris Methyl-Phosphonic acid) 용액을 이용한 표면 저항 특성 개선 시도가 있었으나, 이 역시 용액 합성이 어렵다는 점과 또한 그 농도 조절 등의 문제를 가지고 있다.Conventionally, there have been attempts to increase the corrosion resistance through UV ozone treatment as a method of removing the C and F polymers and forming the surface oxide film with an appropriate thickness, but it is difficult to control the uniform thickness of the surface film. In addition, there have been attempts to improve the surface resistance characteristics using methyl-phosphoic acid (MPA) and nitro tris methyl-phosphoic acid (NTMP) solutions, but this also has problems such as difficulty in synthesizing the solution and controlling its concentration.
본 발명은 상술한 종래의 문제점을 극복하기 위한 것으로서, 본 발명의 목적은 소정 화학 용액으로 세정(wet) 처리를 하여 패드 알루미늄 위의 C 및 F를 제거함과 동시에 표면에 산화막이 형성되도록 하여 더 이상의 산화를 억제할 수 있는 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법을 제공하는데 있다.The present invention is to overcome the above-mentioned conventional problems, an object of the present invention is to remove the C and F on the pad aluminum by the wet (wet) treatment with a predetermined chemical solution to form an oxide film on the surface at the same time The present invention provides a pad aluminum structure of a semiconductor device capable of suppressing oxidation and a method of treating the same.
도1a 및 도1b는 종래 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법을 도시한 설명도이다.1A and 1B are explanatory views showing a pad aluminum structure of a conventional semiconductor device and a processing method thereof.
도2는 종래 반도체 소자의 패드 알루미늄 구조에서 AES(Auger Electron Spectroscopy) 결과를 도시한 그래프이다.2 is a graph illustrating AES (Auger Electron Spectroscopy) results in a pad aluminum structure of a conventional semiconductor device.
도3a는 종래 반도체 소자의 패드 알루미늄 구조에서 깊이별 원소 분포를 도시한 그래프이고, 도3b는 열처리후의 깊이별 원소 분포를 도시한 그래프이다.FIG. 3A is a graph showing element distribution by depth in a pad aluminum structure of a conventional semiconductor device, and FIG. 3B is a graph showing element distribution by depth after heat treatment.
도4는 본 발명에 의한 반도체 소자의 패드 알루미늄 구조를 도시한 단면도이다.4 is a cross-sectional view showing a pad aluminum structure of a semiconductor device according to the present invention.
도5a 내지 도5d는 본 발명에 의한 반도체 소자의 패드 알루미늄 처리 방법을 순차 도시한 설명도이다.5A to 5D are explanatory views sequentially showing a pad aluminum treatment method of a semiconductor device according to the present invention.
도6은 본 발명에 의한 반도체 소자의 패드 알루미늄 구조에서 AES(Auger Electron Spectroscopy) 결과를 도시한 그래프이다.6 is a graph showing AES (Auger Electron Spectroscopy) results in the pad aluminum structure of the semiconductor device according to the present invention.
도7은 본 발명에 의한 반도체 소자의 패드 알루미늄 구조에서 깊이별 원소 분포를 도시한 그래프이다.7 is a graph showing element distribution by depth in the pad aluminum structure of the semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
2; 실리콘 서브스트레이트 4; 패드 알루미늄2; Silicon substrate 4; Pad aluminum
6; TiN 8; 절연층6; TiN 8; Insulation layer
10; 보호층 12; 산화막10; Protective layer 12; Oxide film
16; 식각홀16; Etching Hall
상기한 목적을 달성하기 위해 본 발명에 의한 반도체 소자의 패드 알루미늄 구조는 각종 반도체 소자가 형성된 실리콘 서브스트레이트와, 상기 실리콘 서브스트레이트의 표면에 형성된 패드 알루미늄과, 상기 패드 알루미늄 및 반도체 소자를 외부 환경으로부터 보호하기 위해 그 표면에 형성되어 있되, 상기 패드 알루미늄에와이어 본딩이 가능하도록 식각홀이 형성된 절연층과 보호층 및, 상기 식각홀 내부의 패드 알루미늄 표면에 대략 20~40Å의 두께에서, 상기 알루미늄과 비율이 유사하게 형성된 산화막을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the pad aluminum structure of the semiconductor device according to the present invention includes a silicon substrate on which various semiconductor devices are formed, a pad aluminum formed on a surface of the silicon substrate, and the pad aluminum and the semiconductor device from an external environment. It is formed on the surface for protection, the insulating layer and the protective layer formed with an etch hole to enable the pad aluminum wire bonding, and the thickness of the aluminum and the pad aluminum surface of the pad aluminum inside the etch hole in approximately 20 ~ 40 20 It is characterized in that the ratio comprises an oxide film formed similarly.
여기서, 상기 패드 알루미늄 표면에는 알루미늄과 산화막의 비율이 대략 2:3으로 형성됨이 바람직하다.Here, it is preferable that the ratio of aluminum and an oxide film is formed to be about 2: 3 on the pad aluminum surface.
상기한 목적을 달성하기 위해 본 발명에 의한 반도체 소자의 패드 알루미늄 처리 방법은 각종 반도체 소자가 형성된 실리콘 서브스트레이트 표면에 패드 알루미늄을 형성하고, 상기 패드 알루미늄을 포함한 표면에는 절연층 및 보호층을 순차 증착하는 단계와, 상기 패드 알루미늄에 와이어 본딩이 가능하도록 상기 절연층 및 보호층을 식각하여 식각홀을 형성하는 단계와, 상기 식각홀을 통해 외부로 노출된 상기 패드 알루미늄에 세정 용액으로 세정하여 표면의 C 및 F기 폴리머를 제거하는 단계와, 에탄올과 탈이온수로 세척한 후, 고온의 질소(N2) 가스로 스핀 드라이(spin dry)하여 상기 식각홀을 통해 노출된 패드 알루미늄에 일정 두께의 산화막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the method for processing a pad aluminum of a semiconductor device according to the present invention forms pad aluminum on a surface of a silicon substrate on which various semiconductor devices are formed, and sequentially deposits an insulating layer and a protective layer on the surface including the pad aluminum. Forming an etching hole by etching the insulating layer and the protective layer to enable wire bonding to the pad aluminum, and cleaning the surface of the pad aluminum exposed to the outside through the etching hole with a cleaning solution. Removing the C and F polymers, washing with ethanol and deionized water, and spin-drying with hot nitrogen (N 2) gas to form an oxide film having a predetermined thickness on the pad aluminum exposed through the etching hole. Characterized in that it comprises a step of forming.
여기서, 상기 세정 용액은 40~60%의 암모니엄 플로라이드(Ammonium Fluoride)와 20~30%의 엔, 엔-디메틸 아세타마이드(N,N-dimethyl acetamide), 그리고 디프로필렌 글리콜 모노프로필 에더(Dipropylene glycol monopropyl ether)의 혼합 용액일 수 있다.Here, the cleaning solution is 40 to 60% of ammonium fluoride (Ammonium Fluoride) and 20 to 30% of N, N-dimethyl acetamide (N, N-dimethyl acetamide), and dipropylene glycol monopropyl ether ( Dipropylene glycol monopropyl ether).
또한, 상기 세정은 온도 20~30℃, 시간 5~10분간 처리 됨이 바람직하다.In addition, the washing is preferably processed for a temperature of 20 ~ 30 ℃, 5 to 10 minutes.
더불어, 상기 에탄올과 탈이온수로 세척하는 공정도 각각 5~10분간 수행됨이바람직하다.In addition, the process of washing with ethanol and deionized water is also preferably performed for 5 to 10 minutes each.
이와 같이 하여 본 발명에 의한 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법에 의하면, 간단한 세정 처리를 통해서 C 및 F기 폴리머를 완전히 제거함과 동시에, 표면에 균일한 산화막을 형성할 수 있는 장점이 있다.Thus, according to the pad aluminum structure of the semiconductor element and the processing method thereof according to the present invention, there is an advantage that a uniform oxide film can be formed on the surface while the C and F group polymers are completely removed through a simple cleaning process.
또한, 열처리를 통해 보호층으로 PBO(Polybenzoxasole) 또는 폴리이미드(polyimide)를 이용할 경우, 에칭 공정후 에싱(ashing) 공정없이 세정 공정만으로 폴리머를 제거할 수 있어 공정이 단순화되는 장점이 있다.In addition, when PBO (Polybenzoxasole) or polyimide (polyimide) is used as a protective layer through heat treatment, the polymer may be removed only by a cleaning process without an ashing process after the etching process, thereby simplifying the process.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.
도4를 참조하면, 본 발명에 의한 반도체 소자의 패드 알루미늄 구조가 도시되어 있다.4, a pad aluminum structure of a semiconductor device according to the present invention is shown.
도시된 바와 같이 먼저 각종 반도체 소자가 형성된 실리콘 서브스트레이트(2)가 구비되어 있다. 상기 실리콘 서브스트레이트(2)의 최상층 표면에는 일정 두께의 패드 알루미늄(4)이 형성되어 있다. 상기 패드 알루미늄(4) 및 반도체 소자를 외부 환경으로부터 보호하기 위해 그 표면에는 절연층(8)과 보호층(10)이 순차 형성되어 있되, 상기 패드 알루미늄(4)에 와이어 본딩이 가능하도록 식각홀(16)이 형성되어 있다. 여기서, 상기 절연층(8)은 통상적인 실리콘 산화막 또는 질화막이고, 상기 보호층(10)은 PBO(Polybenzoxasole) 또는 폴리이미드(polyimide)일 수 있다. 더불어, 상기 식각홀(16) 내부의 패드 알루미늄(4) 표면에 대략 20~40Å의 두께에서, 상기 알루미늄과 비율이 유사하게 형성된 산화막(12)이 형성되어 있다. 여기서, 상기 패드 알루미늄(4) 표면에는 알루미늄(Al)과 산화막(O)(12)의 비율이 대략 2:3으로 형성되어 있다. 도면중 미설명 부호 6은 TiN으로서 상기 식각홀(16)과 대응되는 영역은 식각 공정에 의해 상기 TiN이 제거된 상태이다.As shown, first, a silicon substrate 2 on which various semiconductor devices are formed is provided. A pad aluminum 4 having a predetermined thickness is formed on the top surface of the silicon substrate 2. In order to protect the pad aluminum 4 and the semiconductor device from the external environment, an insulating layer 8 and a protective layer 10 are sequentially formed on the surface thereof, and an etching hole is provided to enable wire bonding to the pad aluminum 4. 16 is formed. Here, the insulating layer 8 may be a conventional silicon oxide film or nitride film, and the protective layer 10 may be polybenzoxasole (PBO) or polyimide. In addition, an oxide film 12 having a thickness similar to that of the aluminum is formed on the surface of the pad aluminum 4 inside the etching hole 16 at a thickness of approximately 20 to 40 μm. Here, the ratio of the aluminum (Al) and the oxide film (O) 12 is approximately 2: 3 on the surface of the pad aluminum 4. In the drawing, reference numeral 6 denotes TiN, and a region corresponding to the etching hole 16 is in a state in which TiN is removed by an etching process.
이와 같이 함으로써, 본 발명에 의한 반도체소 소자의 패드 알루미늄(4) 구조에 의하면, 패드 알루미늄(4) 표면에 알루미늄(Al)과 산화막(O)(12)의 비율이 대략 2:3으로 형성되어 있고, 또한 대략 20~40Å의 두께에서 상기 알루미늄과 산화막의 비율이 유사하게 형성됨으로써, 프로브 테스트(probe test)시에 산화막(12)으로 인한 테스트 에러(test error)를 감소시킴과 더불어, 패키징(packaging)시에 형성될 수 있는 부식을 억제할 수 있게 된다.By doing in this way, according to the pad aluminum 4 structure of the semiconductor element of this invention, the ratio of aluminum (Al) and the oxide film (O) 12 is formed in the surface of the pad aluminum 4 at approximately 2: 3, In addition, since the ratio of the aluminum and the oxide film is similarly formed at a thickness of about 20 to 40 kPa, the test error due to the oxide film 12 is reduced during the probe test, and the packaging ( Corrosion that can be formed during packaging can be suppressed.
도5a 내지 도5d를 참조하면, 본 발명에 의한 반도체 소자의 패드 알루미늄 처리 방법이 도시되어 있다.5A to 5D, there is shown a pad aluminum processing method of a semiconductor device according to the present invention.
먼저 도5a에 도시된 바와 같이, 각종 반도체 소자가 형성된 실리콘 서브스트레이트(2) 표면에 패드 알루미늄(4)을 형성하고, 상기 패드 알루미늄(4)을 포함한 표면에는 절연층(8) 및 보호층(10)을 순차 증착한다. 여기서, 상기 절연층(8)은 통상적인 실리콘 산화막 또는 질화막이고, 상기 보호층(10)은 PBO(Polybenzoxasole)또는 폴리이미드(polyimide)일 수 있다.First, as shown in FIG. 5A, a pad aluminum 4 is formed on a surface of a silicon substrate 2 on which various semiconductor devices are formed, and an insulating layer 8 and a protective layer are formed on a surface including the pad aluminum 4. 10) are sequentially deposited. Here, the insulating layer 8 may be a conventional silicon oxide film or nitride film, and the protective layer 10 may be polybenzoxasole (PBO) or polyimide (polyimide).
이어서, 도5b에 도시된 바와 같이, 상기 패드 알루미늄(4)에 와이어 본딩이 가능하도록 상기 절연층(8) 및 보호층(10)을 식각하여 식각홀(16)을 형성한다.Subsequently, as illustrated in FIG. 5B, the insulating layer 8 and the protective layer 10 are etched to form an etching hole 16 to enable wire bonding to the pad aluminum 4.
이어서, 도5c에 도시된 바와 같이, 상기 식각홀(16)을 통해 외부로 노출된 상기 패드 알루미늄(4)에 세정 용액으로 세정하여 표면의 C 및 F기 폴리머를 제거한다. 즉, 아래 표1과 같은 조건으로 세정 처리를 수행한다.Subsequently, as illustrated in FIG. 5C, the pad aluminum 4 exposed to the outside through the etching hole 16 is washed with a cleaning solution to remove C and F group polymers on the surface. That is, the cleaning process is performed under the conditions shown in Table 1 below.
이어서, 도5d에 도시된 바와 같이, 에탄올과 탈이온수로 세척한 후, 고온의 질소(N2) 가스로 스핀 드라이(spin dry)하여, 상기 식각홀(16)을 통해 노출된 패드 알루미늄(4)에 일정 두께의 산화막(12)이 형성되도록 하여, 본 발명에 의한 패드 알루미늄(4)의 처리 공정이 완료된다.Subsequently, as shown in FIG. 5D, the pad aluminum 4 exposed through the etching hole 16 is washed with ethanol and deionized water, and then spin-dried with hot nitrogen (N 2) gas. The oxide film 12 having a predetermined thickness is formed on the substrate, thereby completing the process for treating the pad aluminum 4 according to the present invention.
여기서, 상기 에탄올과 탈이온수로 세척하는 공정은 각각 5~10분간 수행됨이 바람직하다.Here, the process of washing with ethanol and deionized water is preferably performed for 5 to 10 minutes each.
도6을 참조하면, 본 발명에 의한 반도체 소자의 패드 알루미늄 처리 공정을 완료한 후, AES(Auger Electron Spectroscopy) 결과 그래프가 도시되어 있다.Referring to FIG. 6, after completing the pad aluminum treatment process of the semiconductor device according to the present invention, an AES (Auger Electron Spectroscopy) result graph is shown.
도시된 바와 같이 AES 결과 그래프에는 산화막(O)(12)과 알루미늄(Al) 만이 검출되었을 뿐 종래와 같은 탄소(C) 또는 불소(F)와 같은 원소는 검출되지 않음으로써, 본 발명에 의한 패드 알루미늄(4)은 순수한 알루미늄 및 산화막(12)으로만 존재함을 알 수 있다.As shown in the graph, only the oxide (O) 12 and aluminum (Al) were detected in the AES result graph, but elements such as carbon (C) or fluorine (F) were not detected. It can be seen that aluminum 4 exists only as pure aluminum and oxide film 12.
또한, 도7을 참조하면, 본 발명에 의한 반도체 소자의 패드 알루미늄 처리 공정을 완료한 후, 깊이별 원소 분포 그래프가 도시되어 있다.In addition, referring to FIG. 7, after the pad aluminum treatment process of the semiconductor device according to the present invention is completed, an element distribution graph for each depth is shown.
도시된 바와 같이, 패드 알루미늄(4) 표면에 알루미늄과 산화막(12)의 비율은 대략 2:3(알루미늄 60; 산화막 40)으로 형성되어 있고, 또한 대략 20~40Å의 두께에서 상기 알루미늄과 산화막(12)의 비율이 유사하게 존재함을 알 수 있다. 따라서, 프로브 테스트(probe test)시에 산화막(12)으로 인한 테스트 에러(test error)가 감소되고, 패키징(packaging)시에 형성될 수 있는 부식이 효과적으로 억제됨을 알 수 있다.As shown, the ratio of the aluminum and the oxide film 12 on the surface of the pad aluminum 4 is approximately 2: 3 (aluminum 60; the oxide film 40), and the aluminum and the oxide film ( It can be seen that the ratio of 12) exists similarly. Accordingly, it can be seen that a test error due to the oxide film 12 is reduced during the probe test, and corrosion that may be formed during packaging is effectively suppressed.
상술한 바와같이, 본 발명에 따른 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법에 의하면, 간단한 세정 처리를 통해서 C 및 F기 폴리머를 완전히 제거함과 동시에, 표면에 균일한 산화막을 형성할 수 있는 효과가 있다.As described above, according to the pad aluminum structure of the semiconductor device and the processing method thereof according to the present invention, the effect of being able to completely remove the C and F group polymers and to form a uniform oxide film on the surface through a simple cleaning treatment. have.
또한, 열처리를 통해 보호층으로 PBO(Polybenzoxasole) 또는 폴리이미드(polyimide)를 이용할 경우, 에칭 공정후 에싱(ashing) 공정없이 세정 공정만으로 폴리머를 제거할 수 있어 공정이 단순화되는 효과가 있다.In addition, when using PBO (Polybenzoxasole) or polyimide (polyimide) as a protective layer through the heat treatment, the polymer can be removed only by the cleaning process without an ashing process after the etching process, thereby simplifying the process.
이상에서 설명한 것은 본 발명에 따른 반도체 소자의 패드 알루미늄 구조 및 그 처리 방법을 실시하기 위한 하나의 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자가라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.What has been described above is just one embodiment for carrying out the pad aluminum structure of the semiconductor device and the processing method thereof according to the present invention, and the present invention is not limited to the above-described embodiment, which is claimed in the following claims. As will be apparent to those skilled in the art without departing from the gist of the present invention, the technical spirit of the present invention to the extent that various changes can be made.
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| KR100835410B1 (en) * | 2006-12-27 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Method for formation of aluminum bonding pad |
| WO2012148967A3 (en) * | 2011-04-25 | 2013-01-17 | Air Products And Chemicals, Inc. | Cleaning lead-frames to improve wirebonding process |
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| KR100212170B1 (en) * | 1996-04-24 | 1999-08-02 | 김영환 | Forming method for bonding pad of semiconductor device |
| JP3886712B2 (en) * | 2000-09-08 | 2007-02-28 | シャープ株式会社 | Manufacturing method of semiconductor device |
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| KR100835410B1 (en) * | 2006-12-27 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Method for formation of aluminum bonding pad |
| WO2012148967A3 (en) * | 2011-04-25 | 2013-01-17 | Air Products And Chemicals, Inc. | Cleaning lead-frames to improve wirebonding process |
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