KR20040059829A - Method for forming high dielectric capacitor in semiconductor device - Google Patents
Method for forming high dielectric capacitor in semiconductor device Download PDFInfo
- Publication number
- KR20040059829A KR20040059829A KR1020020086333A KR20020086333A KR20040059829A KR 20040059829 A KR20040059829 A KR 20040059829A KR 1020020086333 A KR1020020086333 A KR 1020020086333A KR 20020086333 A KR20020086333 A KR 20020086333A KR 20040059829 A KR20040059829 A KR 20040059829A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- alumina
- hafnium oxide
- semiconductor device
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 캐패시터 형성 공정에 관한 것이며, 더 자세히는 알루미나-산화하프늄(Al2O3-HfO2) 박막을 유전체로 사용하는 캐패시터 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor forming process in a semiconductor device manufacturing process, and more particularly, to a capacitor forming process using an alumina-hafnium oxide (Al 2 O 3 -HfO 2 ) thin film as a dielectric. will be.
반도체 메모리 소자의 고집적화에 따라 동일 레이아웃 면적에서 보다 큰 캐패시턴스를 확보하기 위한 노력이 계속되고 있다. 캐패시터의 캐패시턴스는 유전율(ε) 및 전극의 유효 표면적에 비례하고, 전극간 거리에 반비례하기 때문에, 종래에는 주로 캐패시터 하부전극의 표면적을 확보하거나 유전체의 박막화로 전극간 거리를 최소화하는 방향으로 많은 연구가 진행되어 왔다. 그러나, 이 중 유전체의 박막화는 누설전류 증가를 수반하는 문제점이 있으며, 이에 따라 캐패시터 구조를 플라나 스택(Planar stack), 콘케이브(Concave), 실린더(cylinder)와 같은 3차원 구조로 형성하여 캐패시터의 유효 표면적을 증대시키는 방법을 주로 사용하여 왔다.As semiconductor memory devices become more integrated, efforts have been made to secure larger capacitances in the same layout area. Since the capacitance of the capacitor is proportional to the dielectric constant (ε) and the effective surface area of the electrode, and is inversely proportional to the distance between the electrodes, conventionally, many studies have been conducted mainly to secure the surface area of the capacitor lower electrode or to minimize the distance between electrodes by thinning the dielectric. Has been going on. However, thinning of the dielectric has a problem of increasing leakage current. Accordingly, the capacitor structure is formed into a three-dimensional structure such as a planar stack, a concave, and a cylinder to form a capacitor. The method of increasing the effective surface area has been mainly used.
그러나, 반도체 소자의 고집적화에 수반되는 디자인 룰의 축소에 따라 이러한 구조적인 개선을 통해 캐패시턴스를 확보하는 방법은 공정 상에 한계에 직면하게 되었다.However, with the reduction of design rules associated with high integration of semiconductor devices, the method of securing capacitance through such structural improvements has faced limitations in the process.
이에 따라, 1 기가비트 이상의 DRAM에서는 기존의 유전체 재료인 NO(nitride/oxide) 박막을 Ta205, HfO5등의 고유전체 박막으로 대체하는 연구가 활발히 진행되고 있다. 특히, 많은 선행 연구가 이루어져 양산에 적용할 가능성이 클것으로 예상되었던 Ta205박막은 열적 안정성이 떨어지고, 공정 상의 한계에 의해 5nm 이하의 얇은 두께에서 특성을 제대로 확보하기 어렵다는 문제점이 지적되고 있다.Accordingly, in the DRAM of 1 gigabit or more, researches are being actively conducted to replace NO (nitride / oxide) thin films, which are existing dielectric materials, with high dielectric thin films such as Ta 2 0 5 and HfO 5 . In particular, it is pointed out that Ta 2 0 5 thin film, which was expected to be applied to mass production due to many previous studies, has poor thermal stability, and it is difficult to properly obtain characteristics at a thickness of 5 nm or less due to process limitations. .
최근 이러한 Ta205박막의 한계를 극복하기 위한 대안으로 알루미나(Al2O3)와 산화하프늄(HfO2)의 적층 구조로 이루어진 Al2O3-HfO2박막이 대두되고 있다. Al2O3-HfO2박막은 유전 상수는 다소 작은 편이나, 열적 안정성과 누설전류 특성이 우수한 장점이 있다.Recently, as an alternative to overcome the limitations of the Ta 2 0 5 thin film, an Al 2 O 3 -HfO 2 thin film having a laminated structure of alumina (Al 2 O 3 ) and hafnium oxide (HfO 2 ) has emerged. Al 2 O 3 -HfO 2 thin film has a relatively small dielectric constant, but has excellent thermal stability and leakage current characteristics.
통상적으로, 원자층증착법(ALD) 등으로 Al2O3-HfO2박막을 증착한 후에는 박막 내에 존재하는 탄소(불순물)를 제거하고 산소 공핍을 제거하기 위하여 산소 분위기에서 후속 열처리를 수행하고 있는데, 이때 하부 전극(폴리실리콘)이 산화되어 캐패시턴스를 저하시키는 문제점이 있었다.Typically, after depositing the Al 2 O 3 -HfO 2 thin film by atomic layer deposition (ALD) or the like, subsequent heat treatment is performed in an oxygen atmosphere to remove carbon (impurities) present in the thin film and to remove oxygen depletion. In this case, there is a problem in that the lower electrode (polysilicon) is oxidized to lower the capacitance.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, Al2O3-HfO2박막의 후속 열처리에 따른 하부 전극의 산화를 방지할 수 있는 반도체 소자의 고유전체 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a method of forming a high-k dielectric capacitor of a semiconductor device capable of preventing oxidation of a lower electrode caused by subsequent heat treatment of an Al 2 O 3 -HfO 2 thin film. Its purpose is to.
도 1 내지 도 5는 본 발명의 일 실시예에 따른 Al2O3-HfO2라미네이트 캐패시터 형성 공정을 나타낸 단면도.1 to 5 are cross-sectional views illustrating a process of forming an Al 2 O 3 —HfO 2 laminate capacitor according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 기판10: substrate
11 : 하부 전극용 전도막11: conductive film for lower electrode
12a : Al2O3층12a: Al 2 O 3 layer
12b : HfO2층12b: HfO 2 layer
12 : Al2O3-HfO2라미네이트층12: Al 2 O 3 -HfO 2 laminate layer
13 : 상부 전극용 전도막13: conductive film for upper electrode
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 기판 상에 하부 전극용 전도막을 형성하는 단계; 상기 하부 전극용 전도막 상에 알루미나층과 산화하프늄층을 적어도 한번 적층하여 알루미나-산화하프늄 박막을 형성하는 단계; 질소 분위기에서 열처리하여 상기 알루미나-산화하프늄 박막을 치밀화하는 단계; 상기 알루미나-산화하프늄 박막을 산소계 처리하는 단계; 및 상기 알루미나-산화하프늄 박막 상에 상부 전극용 전도막을 형성하는 단계를 포함하는 반도체 소자의 고유전체 캐패시터 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, forming a conductive film for the lower electrode on the substrate; Stacking an alumina layer and a hafnium oxide layer at least once on the lower electrode conductive film to form an alumina-hafnium oxide thin film; Heat treating in a nitrogen atmosphere to densify the alumina-hafnium oxide thin film; Oxygen-based treatment of the alumina-hafnium oxide thin film; And forming a conductive film for the upper electrode on the alumina-hafnium oxide thin film.
본 발명은 Al2O3-HfO2박막을 적층한 후, N2분위기에서 열처리를 수행하여 박막을 치밀화한 다음, 산화 분위기에서의 급속열처리 또는 오존 플라즈마 처리를 수행하여 박막 내에 존재하는 탄소(불순물)를 제거하고 산소 공핍을 제거함으로써 하부 전극의 산화를 방지한다.According to the present invention, after stacking an Al 2 O 3 -HfO 2 thin film, heat treatment is performed in an N 2 atmosphere to densify the thin film, and then rapid heat treatment or an ozone plasma treatment in an oxidizing atmosphere is performed. ) To prevent oxidation of the lower electrode by removing oxygen depletion.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1 내지 도 5는 본 발명의 일 실시예에 따른 Al2O3-HfO2캐패시터 형성 공정을 나타낸 단면도이다.1 to 5 are cross-sectional views illustrating a process of forming an Al 2 O 3 —HfO 2 capacitor according to an embodiment of the present invention.
우선, 도 1에 도시된 바와 같이 기판(10) 상에 하부 전극용 폴리실리콘막(10)을 증착하고, 폴리실리콘막(10)의 표면을 HF 용액 또는 HF+NH4OH용액을 사용하여 세정한다. 이어서, 고온 산소 분위기에서의 후속 열공정에 의한 폴리실리콘막(10)의 산화를 억제하기 위하여 폴리실리콘막(10)에 대해 급속열질화(RTN) 공정 또는 NH3플라즈마 처리를 수행할 수 있다.First, as shown in FIG. 1, a polysilicon film 10 for lower electrodes is deposited on the substrate 10, and the surface of the polysilicon film 10 is cleaned using HF solution or HF + NH 4 OH solution. do. Subsequently, in order to suppress oxidation of the polysilicon film 10 by a subsequent thermal process in a high temperature oxygen atmosphere, a rapid thermal nitriding (RTN) process or an NH 3 plasma treatment may be performed on the polysilicon film 10.
다음으로, 도 2에 도시된 바와 같이 폴리실리콘막(11) 상에 Al2O3-HfO2박막(12)을 증착한다. 이때, Al2O3-HfO2박막(12)은 원자층증착법으로 증착하며, 자세한 레시피는 다음과 같다.Next, as shown in FIG. 2, an Al 2 O 3 —HfO 2 thin film 12 is deposited on the polysilicon film 11. At this time, the Al 2 O 3 -HfO 2 thin film 12 is deposited by atomic layer deposition, detailed recipe is as follows.
가) 웨이퍼를 원자층증착 챔버에 로딩하고, 웨이퍼 온도는 200∼400℃, 챔버 압력은 0.1∼10Torr로 유지한다.A) The wafer is loaded into the atomic layer deposition chamber, and the wafer temperature is maintained at 200 to 400 ° C. and the chamber pressure is 0.1 to 10 Torr.
나) 알루미늄 소오스인 TMA((CH3)3Al)(상온에서 가스 상태)를 500.1∼3초 동안 플로우시킨 후, 0.1∼5초 동안 N2퍼지를 실시한다.B) After flowing TMA ((CH 3 ) 3 Al) (a gas state at room temperature), which is an aluminum source, for 500.1 to 3 seconds, N 2 purge is performed for 0.1 to 5 seconds.
다) 반응 가스인 O3가스를 0.1∼3초 동안 플로우시킨 후, 0.1∼5초 동안 N2퍼지를 실시한다. 이 과정까지 마치면 폴리실리콘막(11) 상에 Al2O3층(12a)이 형성된다.C) After flowing O 3 gas which is a reaction gas for 0.1 to 3 seconds, N 2 purge is performed for 0.1 to 5 seconds. After this process, the Al 2 O 3 layer 12a is formed on the polysilicon film 11.
라) 챔버 압력은 0.1∼10Torr로 유지한 채로 서브 히터 온도를 200∼400℃로 유지한다.D) The sub-heater temperature is maintained at 200 to 400 ° C while the chamber pressure is maintained at 0.1 to 10 Torr.
마) 하프늄 소오스인 Hf(NCH2C2H5)4(50∼60℃ 온도에서 기화)를 0.1∼3초 동안 플로우시킨 후, 0.1∼5초 동안 N2퍼지를 실시한다.E) Hf (NCH 2 C 2 H 5 ) 4 (vaporized at 50-60 ° C.), which is a hafnium source, is flowed for 0.1 to 3 seconds, followed by N 2 purge for 0.1 to 5 seconds.
마) 반응 가스인 O3가스를 0.1∼3초 동안 플로우시킨 후, 0.1∼5초 동안 N2퍼지를 실시한다. 이 과정까지 마치면 Al2O3층(12a) 상에 HfO2층(12b)이 형성된다.E) After flowing O 3 gas which is a reaction gas for 0.1 to 3 seconds, N 2 purge is performed for 0.1 to 5 seconds. After this process, the HfO 2 layer 12b is formed on the Al 2 O 3 layer 12a.
바) 상기 가)∼마) 과정을 2∼3회 반복하면 Al2O3-HfO2박막(12)을 얻을 수 있다.F) Repeat the above steps a) to 3 ) to obtain an Al 2 O 3 -HfO 2 thin film 12.
계속하여, 도 3에 도시된 바와 같이 Al2O3-HfO2박막(12)을 N2분위기에서 600∼800℃ 온도로 10∼30분 동안 열처리한다.Subsequently, as shown in FIG. 3, the Al 2 O 3 —HfO 2 thin film 12 is heat-treated at 600 to 800 ° C. for 10 to 30 minutes in an N 2 atmosphere.
다음으로, 도 4에 도시된 바와 같이 Al2O3-HfO2박막(12)을 400∼800℃ 온도로 5∼30분 동안 산소계 열처리를 수행한다. 산소계 열처리는 분위기 가스로 N2O 가스 또는 O2가스를 사용하여 급속열처리로 수행하는 것이 바람직하며, 이를 대신하여 오존 플라즈마 처리를 수행할 수 있다. 오존 플라즈마 처리시에는 10000∼200000ppm 농도의 오존 가스를 공급하고 50∼400W의 RF 파워를 사용하여 플라즈마를 생성한다.Next, as shown in FIG. 4, the Al 2 O 3 —HfO 2 thin film 12 is subjected to oxygen-based heat treatment at 400 to 800 ° C. for 5 to 30 minutes. Oxygen-based heat treatment is preferably carried out by rapid heat treatment using N 2 O gas or O 2 gas as the atmosphere gas, it may be performed instead of ozone plasma treatment. In the ozone plasma treatment, ozone gas with a concentration of 10000 to 200000 ppm is supplied and plasma is generated using RF power of 50 to 400 W.
이어서, 도 5에 도시된 바와 같이 Al2O3-HfO2박막(12) 상에 상부 전극용 전도막(13)을 증착한다. 이때, 상부 전극용 전도막(13)으로는 TiN막과 폴리실리콘막의 적층 구조를 사용하는 것이 바람직하다.Subsequently, as shown in FIG. 5, the conductive film 13 for the upper electrode is deposited on the Al 2 O 3 —HfO 2 thin film 12. At this time, it is preferable to use a laminated structure of a TiN film and a polysilicon film as the upper electrode conductive film 13.
이후, 사진 및 식각 공정을 통해 상부 전극용 전도막(13), Al2O3-HfO2박막(12), 하부 전극용 폴리실리콘막(11)을 패터닝하여 단위 캐패시터를 디파인한다.Subsequently, the unit capacitor is defined by patterning the upper electrode conductive layer 13, the Al 2 O 3 —HfO 2 thin film 12, and the lower electrode polysilicon layer 11 through a photograph and an etching process.
이상에서 살펴본 바와 같이 본 발명에서는 Al2O3-HfO2박막 증착 후 N2분위기에서의 열처리를 거쳐 Al2O3-HfO2박막의 막질을 치밀화하는 과정을 거치기 때문에 후속 열처리 공정에서의 하부 전극의 산화를 방지할 수 있다.As described above, in the present invention, since the Al 2 O 3 -HfO 2 thin film is deposited and subjected to heat treatment in an N 2 atmosphere, the film quality of the Al 2 O 3 -HfO 2 thin film is densified, so that the lower electrode in the subsequent heat treatment process Oxidation can be prevented.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 상부 전극용 전도막까지 적층이 완료된 후에 패터닝 공정을 수행하는 경우를 일례로 들어 설명하였으나, 본 발명은 중간 과정에서 패터닝을 수행하는 경우에도 적용된다.For example, in the above-described embodiment, the case in which the patterning process is performed after the lamination is completed up to the conductive film for the upper electrode has been described as an example. However, the present invention is applied to the case where the patterning is performed in the intermediate process.
또한, 전술한 실시예에서는 스택형 캐패시터를 일례로 들어 설명하였으나, 본 발명은 컨케이브(concave)형 캐패시터, 실린더형 캐패시터 등 다른 구조의 캐패시터 형성시에도 적용된다.In addition, in the above-described embodiment, the stack type capacitor has been described as an example, but the present invention is also applied to the formation of capacitors having other structures such as a concave type capacitor and a cylindrical type capacitor.
또한, 전술한 실시예에서는 하부 전극용 전도막으로 폴리실리콘막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 다른 전도막으로 하부 전극을 형성하는 경우에도 적용된다.In addition, in the above-described embodiment, the case where the polysilicon film is used as the conductive film for the lower electrode is described as an example, but the present invention is also applicable to the case of forming the lower electrode with another conductive film.
전술한 본 발명은 하부 전극의 산화에 의한 캐패시턴스 저하를 방지하여 반도체 소자의 신뢰도 및 수율을 개선하는 효과가 있다.The present invention described above has the effect of improving the reliability and yield of the semiconductor device by preventing capacitance decrease due to oxidation of the lower electrode.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086333A KR20040059829A (en) | 2002-12-30 | 2002-12-30 | Method for forming high dielectric capacitor in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086333A KR20040059829A (en) | 2002-12-30 | 2002-12-30 | Method for forming high dielectric capacitor in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040059829A true KR20040059829A (en) | 2004-07-06 |
Family
ID=37351795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020086333A KR20040059829A (en) | 2002-12-30 | 2002-12-30 | Method for forming high dielectric capacitor in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040059829A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113948520A (en) * | 2019-03-26 | 2022-01-18 | 湘潭大学 | Hafnium oxide based ferroelectric capacitor and preparation method thereof |
-
2002
- 2002-12-30 KR KR1020020086333A patent/KR20040059829A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113948520A (en) * | 2019-03-26 | 2022-01-18 | 湘潭大学 | Hafnium oxide based ferroelectric capacitor and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100568448B1 (en) | method of fabricating high-k dielectric layer having reduced impurity | |
| KR100604845B1 (en) | Metal-Insulator-Metal capacitor having insulating layer with nitrogen and method for manufacturing the same | |
| KR100507860B1 (en) | Capacitor having oxidation barrier and method for fabricating the same | |
| US20100164064A1 (en) | Capacitor and Method for Manufacturing the Same | |
| KR100671604B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100717824B1 (en) | Capacitor and method for manufacturing the same | |
| KR100670671B1 (en) | Method for forming hafnium oxide layer in semiconductor device | |
| KR20040059829A (en) | Method for forming high dielectric capacitor in semiconductor device | |
| KR20000042429A (en) | Method for manufacturing ferroelectric capacitor of semiconductor device | |
| KR100532960B1 (en) | Method for forming capacitor of semiconductor device | |
| JP2006147896A (en) | Forming method of thin film and manufacturing method of semiconductor device | |
| JP2006156516A (en) | Method of manufacturing metallic silicate nitride film and method of manufacturing semiconductor device | |
| KR100551884B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100624927B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100507865B1 (en) | Method for manufacturing capacitor in semiconductor device | |
| KR100538805B1 (en) | Method of manufacturing capacitor for semiconductor device | |
| KR100231604B1 (en) | Manufacturing method of capacitor of semiconductor device | |
| KR101062812B1 (en) | Method for forming hafnium oxide capacitor in semiconductor device | |
| KR100925028B1 (en) | A dielectric layer, forming method thereof and a capacitor of semiconductor device and forming method thereof using the same | |
| KR20040061278A (en) | Method for fabricating capacitor of semiconductor device | |
| KR20040060416A (en) | Method for fabricating capacitor of semiconductor device | |
| KR20040006409A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| JP4106513B2 (en) | Capacitor manufacturing method for semiconductor device | |
| KR20040057751A (en) | Method for fabricating capacitor having stack dielectric layer by alumina and hafnium dioxide | |
| KR20040051298A (en) | Method for fabricating capacitor having stack dielectric layer by alumina and hafnium dioxide |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application | ||
| J201 | Request for trial against refusal decision | ||
| J301 | Trial decision |
Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20090213 Effective date: 20100415 |