KR20040059758A - Method for fabricating silicide region in CMOS image sensor - Google Patents

Abstract

PURPOSE: A method for forming silicide in a CMOS(complementary metal oxide semiconductor) image sensor is provided to minimize damage to gate polysilicon and a spacer by performing a CMP(chemical mechanical polishing) process and introducing a buffer nitride layer when silicide is formed on gate polysilicon in a pixel region. CONSTITUTION: Gate polysilicon(21) and a buffer nitride layer are sequentially formed on a substrate(20). The gate polysilicon and the buffer nitride layer are patterned to form a gate electrode and a spacer at both sidewalls of the gate electrode. A silicide blocking layer(24) is formed along a step on the resultant structure, and a planarization layer is formed on the silicide blocking layer. A CMP process is performed until a predetermined thickness of the buffer nitride layer is exposed. The buffer nitride layer remaining on the gate polysilicon is removed. Silicide(26) is formed on the gate polysilicon.

Description

Method for fabricating silicide region in CMOS image sensor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, in the process of forming silicide in the gate polysilicon of the pixel region, by using chemical mechanical polishing and using a buffer nitride film instead of the conventional etching process. The present invention relates to a method of manufacturing a CMOS image sensor that minimizes loss of polysilicon and loss of spacers, and enables uniform silicide formation even in a large area of polysilicon.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to each other. Complementary MOS image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method, and implements an image by using a CMOS manufacturing technology, which consumes less power and uses 30 to 40 masks as many as 20 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.

FIG. 1A is a circuit diagram showing a unit pixel composed of one photodiode PD and four MOS transistors in a conventional CMOS image sensor, and includes a photodiode 100 for generating photocharges by receiving light. The transfer transistor 101 for transporting the photocharges collected from the photodiode 100 to the floating diffusion region 102 and the potential of the floating diffusion region 102 to a desired value are discharged to discharge the floating diffusion region 102. A reset transistor 103 for resetting the drive transistor, a drive transistor 104 serving as a source follower buffer amplifier, and a select transistor enabling addressing as a switching role. 105). Outside the unit pixel, a load transistor 106 is formed to read an output signal. Three nodes 110, 111, and 112 are separately shown, which will be described later with reference to FIG. 1B.

FIG. 1B is a layout view of the unit pixel illustrated in FIG. 1A, which illustrates an isolation defining an active region in which a photodiode and a diffusion region are to be formed, and a polysilicon constituting a gate of each transistor. It is.

Referring to this, a square active region forms the photodiode 100, and the active region forming the photodiode is bent in a 'b' shape on the upper surface thereof and then extended in the X-axis direction. The gate polysilicon 101 of the transfer transistor Tx is formed over a bottleneck of a portion where the active region constituting the photodiode is bent by a letter 'a', and the floating diffusion region 102 is formed of the gate polysilicon 101 of the transfer transistor. The substrate is laid out at 90 ° from the Y-axis direction in contact with the other side to be in contact with one side of the gate polysilicon 103 of the reset transistor. In the floating diffusion region 102, an FD contact 110 is formed to electrically connect the floating diffusion region 102 and the gate polysilicon 104 of the drive transistor Dx.

Next, the active region formed on the other side of the gate polysilicon 103 of the reset transistor Rx extends in the X-axis direction and is formed downward by 90 ° in the Y-axis direction from the middle to form the drive transistor Dx. It meets the gate polysilicon 104.

A V _DD contact 111 for applying a power supply voltage is formed in an active region of the reset transistor Rx extending in the X-axis direction from the other side of the gate polysilicon 103, and the gate of the drive transistor Dx is formed. In the polysilicon 104, a contact 114 for electrical connection with the floating diffusion region 102 is formed.

The active region that meets the gate polysilicon 104 of the drive transistor Dx continues to extend in the Y-axis direction to meet the gate polysilicon 105 of the select transistor Sx, and furthermore, the gate of the select transistor Sx. The Sx contact 112 is formed in the active region formed over the polysilicon 105. The Sx contact 112 is a contact for outputting the unit pixel.

Referring to the layout diagram shown in FIG. 1B, the gate polysilicon 103 of the reset transistor is also connected to an adjacent pixel and formed to have a considerable length in a pixel array in which several hundred pixels are collected. The gate polysilicon 105 of the select transistor is likewise connected to adjacent pixels and has a considerable length in terms of the pixel array.

Conventionally, in the unit pixels thus formed, silicide is formed only on the upper portions of the gate polysilicon 101, 103, 104, and 105, and no silicide is formed on the active region. This is because when the silicide is formed on the photodiode 100 formed in the active region, the optical characteristics of the device may be reduced, so that the silicide is not formed on the active region of the unit pixel.

1C to 1E are diagrams illustrating a silicide forming method of a CMOS image sensor according to the related art, and a process cross-sectional view illustrating a process of forming silicide only on an upper portion of a gate polysilicon of a unit pixel.

Referring to FIGS. 1C to 1E, as shown in FIG. 1C, an isolation layer (not shown) defining an active region and a field region is formed on a semiconductor substrate 10. A device isolation film using a trench structure may be used as the device isolation film, or a device isolation film may be manufactured using a thermal oxide film.

Next, the gate polysilicon is coated on the substrate 10 and patterned to form the gate electrode 11, and then the nitride film spacers 12 are formed on both sidewalls of the gate electrode 11. Although not shown in Fig. 1C, a light receiving element including a photodiode or the like is formed in the substrate of the pixel region.

Next, a high temperature low density dielectric (HLD) oxide film 13 is deposited on the entire structure including the gate electrode, and an antireflection film 14 is coated on the HLD film 13.

Next, as shown in FIG. 1D, the anti-reflection film 14 and the HLD film 13 are sequentially etched to expose the upper surface of the gate polysilicon 11 by applying a front etching process.

At this time, the upper portion of the gate polysilicon 11 is damaged in this front etching process (indicated by A), and the nitride film spacer 12 is also injured (indicated by B).

As described above, when the gate polysilicon is exposed through the entire surface etching process, the gate polysilicon may be exposed at some portions according to the area of the gate polysilicon, and the portion of the gate polysilicon may not be exposed due to the remaining HLD film. A phenomenon in which the degree of damage of the gate polysilicon is changed occurs.

Accordingly, even when silicide is formed on the gate polysilicon through the subsequent process, the resistance of the polysilicon line is nonuniform, and when the nitride film spacer 12 is damaged, seriously affects the characteristics of the transistor. There was a disadvantage.

The present invention has been made to solve the above-described problems. When silicide is formed on the gate polysilicon of the pixel region, chemical mechanical polishing is applied instead of conventional front etching, and a buffer nitride film is introduced to the gate polysilicon. It is an object of the present invention to provide a method for forming silicide of a CMOS image sensor that minimizes damage to a spacer.

1A is a circuit diagram showing the configuration of a unit pixel of a conventional CMOS image sensor;

1B is a layout diagram showing a layout of unit pixels of a conventional CMOS image sensor;

1C to 1E are process flowcharts illustrating a silicide forming method of a CMOS image sensor according to the prior art;

2A to 2F are process flowcharts illustrating a silicide forming method of a CMOS image sensor according to an embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

20: substrate

21: gate polysilicon

22: buffer nitride film

23: spacer

24: silicide prevention film

25: antireflection film

26: silicide

According to an aspect of the present invention, there is provided a method of forming silicide on a gate polysilicon of a pixel region in a CMOS image sensor, the method comprising: sequentially forming a gate polysilicon and a buffer nitride film on a substrate; Patterning the gate polysilicon and the buffer nitride layer to form a gate electrode, and forming spacers on both sidewalls of the gate electrode; Forming a silicide prevention film along a step on the entire structure, and forming a planarization film on the silicide prevention film; Performing chemical mechanical polishing until the buffer nitride film is exposed to a predetermined thickness; Removing the buffer nitride film remaining on the gate polysilicon; And forming a silicide on the gate polysilicon.

The present invention relates to a silicide forming method of a CMOS image sensor that prevents loss of gate polysilicon and spacers by applying chemical mechanical polishing and applying a buffer nitride film when silicide is formed on the gate polysilicon in the pixel region.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A to 2F are diagrams illustrating a silicide forming method of a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a gate polysilicon 21 and a buffer nitride film 22 are sequentially stacked on the semiconductor substrate 20. Although not shown in FIG. 2A, a gate insulating film (not shown) is formed under the gate polysilicon. The gate polysilicon 21 is formed to a thickness of 1000 to 1500 kPa, and the buffer nitride film 22 is formed to a thickness of 1500 to 2000 kPa. The buffer nitride film 22 serves as an etch stop film in subsequent chemical mechanical polishing.

Next, as shown in FIG. 2B, the gate polysilicon 21 and the buffer nitride film 22 are patterned using an appropriate mask to form the gate electrode 21. Then, a spacer forming material is applied and the entire surface is etched. Thus, spacers 23 are formed on both sidewalls of the gate electrode 21.

As the spacer forming material, a nitride film or an oxide film may be used. When the nitride spacer is used, the buffer nitride film 22 is also etched during the entire etching to form the nitride spacer, so that the thickness of the buffer nitride film is formed in FIG. 2A. It is desirable to increase the thickness to close to 2000 Hz.

Subsequently, the HLD oxide film 24 is coated on the entire structure as shown in FIG. 2C, and then a thick BPSG (Boro Phospo Silicate Glass) film 25 is formed on the upper portion thereof, and the surface thereof is planarized. Here, the HLD oxide film 24 is a silicide prevention film for preventing silicide formation metal material from reacting with silicon to form silicide, and the BPSG film was used for planarization purposes.

Next, as shown in FIG. 2D, chemical mechanical polishing (CMP) is performed. At this time, the etching target of the chemical mechanical polishing (CMP) is set to such an extent that about 500 kPa (marked as 'A' in FIG. 2D) after the buffer nitride film 22 is exposed. Such a buffer nitride film 22 serves as an etch stop film during chemical mechanical polishing, and also serves to prevent the gate polysilicon 21 from being damaged.

As described above, in one embodiment of the present invention, the HLD oxide film 21 formed on the gate polysilicon 21 is removed by chemical mechanical polishing instead of the conventional surface etching method.

Therefore, the gate polysilicon is exposed to a portion of the gate polysilicon according to the area of the gate polysilicon, and the portion of the gate polysilicon is not exposed due to the remaining HLD film. Fixed the problem of changing.

Next, as shown in FIG. 2E, the remaining buffer nitride film 22 is removed using a dry etching method or a wet etching method. At this time, the etching target of dry etching or wet etching is set to such an extent that damage of the gate polysilicon 21 can be minimized.

Even when the etching process is performed using such an etching target, when the buffer nitride film 2 is removed by the dry etching method, the gate polysilicon 21 may be damaged by plasma damage or the like. In the case of removing the buffer nitride layer 22, the damage of the gate polysilicon 21 may be minimized.

If the spacer 23 is formed of a nitride film, when the buffer nitride film 22 is removed through the dry etching method or the wet etching method, the nitride film spacer 23 may also be etched together. It is preferable to use an oxide film as a forming material. Next, the silicide forming process is performed to form silicide 26 on the gate polysilicon 21.

When the present invention is applied to the CMOS image sensor, it is possible to prevent the damage of the gate polysilicon and the damage of the spacer in the process of forming silicide on the gate polysilicon of the pixel region, and the silicide characteristics according to the area of the polysilicon The conventional problem that has changed can be solved.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied to the CMOS image sensor, it is possible to prevent damage to the gate polysilicon and damage to the spacer in the process of forming silicide on the gate polysilicon of the pixel region, thereby improving the characteristics of the device. It is possible to solve the conventional problem of changing the silicide properties according to the area of the polysilicon, and thus stable silicide formation is possible.

Claims (8)

In the method of forming silicide on the gate polysilicon of the pixel region in the CMOS image sensor Stacking and sequentially forming a gate polysilicon and a buffer nitride film on the substrate; Patterning the gate polysilicon and the buffer nitride layer to form a gate electrode, and forming spacers on both sidewalls of the gate electrode; Forming a silicide prevention film along a step on the entire structure, and forming a planarization film on the silicide prevention film; Performing chemical mechanical polishing until the buffer nitride film is exposed to a predetermined thickness; Removing the buffer nitride film remaining on the gate polysilicon; And Forming a silicide on the gate polysilicon Silicide forming method of the CMOS image sensor comprising a. The method of claim 1, Removing the buffer nitride film remaining on the gate polysilicon using a wet etching method. The method according to claim 1 or 2, The spacer is a silicide forming method of the CMOS image sensor, characterized in that using the oxide spacer. The method of claim 1, The silicide prevention layer is a silicide forming method of a CMOS image sensor, characterized in that the HLD oxide film. The method of claim 1, And the buffer nitride film is formed to have a thickness of 1500 to 2000 GPa. The method of claim 4, wherein The silicide prevention method is a silicide forming method of a CMOS image sensor, characterized in that the formation of the HLD oxide film flows a BPSG oxide film having excellent gap-fill ability, the double layer. The method of claim 1, Removing the buffer nitride film remaining on the gate polysilicon using a dry etching method. The method according to claim 1 or 2, The spacer is a silicide forming method of the CMOS image sensor, characterized in that using the nitride film spacer.