KR20040057150A - Test substrate and test method for improving test efficiency - Google Patents

Abstract

PURPOSE: A test substrate having an enhance test efficiency for an LCD(Liquid Crystal Display) and a test method thereof are provided to measure all test patterns by using one kind of pin card. CONSTITUTION: A TFT(Thin Film Transistor) characteristic measuring test pattern(300), a resistance measuring test pattern(310) and two capacitance measuring test patterns(320) are formed at a test pattern region of a mother substrate. The TFT characteristic measuring test pattern(300) needs three outside terminals(302,304) connected to a source electrode, a gate electrode and a drain electrode. The resistance measuring test pattern(310) is used by using four outside terminals(322,324,326,328), so that the additional resistance such as line resistance is removed and then the resistance is measured exactly. The two capacitance measuring test patterns(320) needs two outside terminals(322,324) connected to two conductive films by interposing an insulation film.

Description

TEST SUBSTRATE AND TEST METHOD FOR IMPROVING TEST EFFICIENCY}

The present invention relates to a test substrate and a test method of a liquid crystal display device having improved test efficiency. More particularly, the present invention relates to a liquid crystal display device having improved test efficiency by arranging external terminals of each test pattern constituting a test element group in the same manner. A test substrate and a test method are provided.

A liquid crystal display device has a matrix form by a plurality of data lines arranged in a vertical direction on a thin film transistor (TFT) substrate and a plurality of gate lines arranged in a horizontal direction. Pixels are formed. Each pixel is composed of a TFT, which is a switch element, a storage capacitor Cs for maintaining a constant voltage applied to the liquid crystal layer, and a pixel electrode, which is a transparent electrode. The TFT substrate is bonded to a color filter substrate with a liquid crystal layer interposed therebetween.

1 is a plan view showing a mother substrate used when manufacturing a TFT substrate.

Several TFT substrates are manufactured from one mother substrate 100. 1 shows the case where six TFT substrates are formed.

The mother substrate 100 is divided into a test pattern region 110 and a panel region 120. A test pattern 130 is formed in the test pattern region 110, and a TFT array is formed in the panel region 120.

The test pattern 130 is formed to inspect the electrical characteristics of the TFT array, and the test pattern 130 is separately designed in the test pattern region 210 so that the characteristics of the TFT, capacitance of capacitance and contact resistance, etc. Indirectly measured to determine whether there is a defect or the trend of process parameters. Several kinds of test patterns 130 are gathered to form a test element group (hereinafter, TEG).

Conventionally, since the test pattern of the TEG is different for each test item of the liquid crystal display device, a pin card is required. Therefore, an expensive pin card has to be prepared and tested for each test pattern. Therefore, since a plurality of pin cards according to each test pattern have to be prepared and replaced, there is a problem in that the manufacturing process is delayed and the production efficiency and the efficiency of the equipment are lowered.

Accordingly, an object of the present invention is to provide a method for measuring all test patterns using one kind of pin card in order to increase the efficiency of equipment.

Other objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

1 is a plan view showing a mother substrate used when manufacturing a TFT substrate.

Fig. 2A is a plan view showing one pixel in the TFT array formed in the panel region, and Fig. 2B is an equivalent circuit diagram thereof.

3 is a plan view showing a test pattern according to an embodiment of the present invention.

4 is a vertical sectional view and a plan view of a test pattern for TFT characteristic measurement according to an embodiment of the present invention.

5 is a vertical sectional view and a plan view of the test pattern for measuring the storage capacity according to the embodiment of the present invention.

Figure 6 is a plan view showing a test pattern for measuring contact resistance according to an embodiment of the present invention.

7 is a pin card for testing each test pattern according to an embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

100: mother substrate 110, 480, 520, 600: test pattern area

120: panel area 130: test pattern

200: data wiring 210: gate wiring

220, 500: storage capacitor electrode 230, 470, 570, 640: pixel electrode

240: data pad 250: gate pad

262 and 400 gate electrodes 264 and 420 a source electrode

266, 430, and 610: drain electrode 300: test pattern for TFT characteristic measurement

310: test pattern for resistance measurement 320: test pattern for capacity measurement

302, 304, 306, 308, 312, 314, 316, 318, 322, 324, 326, 328: external terminals

410: gate insulating film 440: semiconductor layer

480, 510, 620: Shield 630: Contact hole

700: pin 710: holder

720: pin card

The present invention is a mother substrate divided into a plurality of panel region and a test pattern region surrounding the panel region to achieve the above object; A thin film transistor array formed in the panel region; A test pattern for measuring thin film transistor characteristics formed on the test pattern region, the external terminal being arranged to measure with a kind of pin card; Capacity test pattern; And it provides a test substrate of the liquid crystal display device with improved test efficiency comprising a test pattern for measuring resistance.

The external terminals of each test pattern are preferably arranged identically in the same number. In an exemplary embodiment of the present invention, four external terminals of the test pattern are provided, one of four external terminals is a dummy terminal, and the test pattern for capacitance measurement is two of four external terminals. A test substrate of a liquid crystal display device which is a dummy terminal is provided.

In addition, the present invention comprises the steps of preparing a mother substrate divided into a panel region and a test pattern region surrounding the panel region to achieve the object; Forming a thin film transistor array in the panel region and simultaneously forming a plurality of test patterns in the test pattern region to measure thin film transistor characteristics, capacitance, and resistance; And measuring the thin film transistor characteristics, capacitance, and resistance while moving one type of pin card.

In the embodiment of the present invention, each test pattern is formed to have the same number and the same number of external terminals.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the relationship between the test pattern formed in the test pattern region of the mother substrate and the TFT array formed in the panel region will be described with reference to FIGS. 2A and 2B.

FIG. 2A is a plan view showing one pixel in the TFT array formed in the panel region, and FIG. 2B is an equivalent circuit diagram thereof.

The data line 200 and the gate line 210 are arranged vertically and horizontally in the panel region to form a pixel region, and a TFT (A) is formed at the intersection of the data line 200 and the gate line 210. A portion of the gate wiring 210 protrudes to form a gate electrode 262 of the TFT (A), and a portion of the data wiring 200 protrudes to form a source electrode 264 of the TFT (A). Configure A drain electrode 266 is formed at a predetermined distance from the source electrode 264. In addition, the storage capacitor electrode 220 is formed to cross the pixel region. The storage capacitor electrode 220 may use a gate wiring 210 to secure an aperture ratio.

After depositing a passivation layer on the TFT (A), a pixel electrode 230 is formed in the pixel region so that the drain electrode 266 and the TFT (A) are electrically connected by forming a contact hole.

At the ends of the data line 200 and the gate line 210, a data pad 240 and a gate pad 250 in which the pixel electrode and the wires 200 and 210 are in contact through the contact hole H are provided. ) Is formed. Signals are received from a driver integrated circuit through the pads 240 and 250.

As described above, since the TFT array is composed of a plurality of conductive wires, parasitic capacitance exists between the wires. In addition, since each wiring has a finite conductivity, wiring resistance exists, and contact resistance also exists between each wiring contacted through the contact hole and the pixel electrode.

An equivalent circuit diagram considering the parasitic capacitance, wiring resistance, contact resistance, and the like is shown in FIG. 2B. The same capacitance and resistance as those in FIG. 2A are denoted by the same symbols (A to I).

B is a parasitic capacitance Cgs formed between the gate electrode 262 and the source electrode 264, C is a parasitic capacitance Cgd formed between the gate electrode 262 and the drain electrode 266, and D is a storage capacitor. Accumulation capacitance Cs formed between the electrode 220 and the pixel electrode 230, E is the data line 200 resistor, F is the gate line 210 resistor, G is the drain electrode 266 and the pixel electrode 230. The contact resistance, H and I, between) denotes the contact resistance at each pad 230, 250. Clc represents the capacitance by the liquid crystal layer, and Vcom represents the common voltage applied to the color filter substrate.

According to the embodiment of the present invention, the TFT (A), the resistors (E, F, G, H, I), and the capacitors (B, C, D) and the like shown in FIGS. 2A and 2B are simultaneously formed with the TFT array. To form.

3 is a plan view showing a test pattern according to an embodiment of the present invention.

One TFT characteristic measurement test pattern 300, one resistance measurement test pattern 310, and two capacitance measurement test patterns 320 are formed in the test pattern region of the mother substrate.

The test pattern 300 for TFT characteristic measurement requires three external terminals 302, 304, and 306 connected to the source electrode, the gate electrode, and the drain electrode. The resistance measurement test pattern 310 may be measured using two external terminals, but by using four external terminals 322, 324, 326, and 328, additional resistance such as line resistance is removed to accurately measure resistance. can do. The capacitance measurement test pattern 220 requires two external terminals 322 and 324 connected to two conductor films having an insulating film therebetween.

Each test pattern 300, 310, 320 is formed by arranging four external terminals in the same manner as shown. In an embodiment of the present invention, each external terminal is disposed at a vertex of a rectangle having a width a and a length b, but is not limited thereto.

One of the external terminals 302, 304, 306, 308 of the test pattern 300 for TFT characteristic measurement and two of the external terminals 322, 324, 326, 328 of the test pattern 320 for capacitance measurement are TFTs. And dummy terminals 308, 326, and 328 formed separately from the capacitance.

The dummy terminals 308, 326, and 328 are not involved in measuring the characteristics of the test patterns 300, 310, and 320. However, if the pin card contact portion is in direct contact with the substrate, the surface of the substrate may be damaged, thereby preventing the surface damage by forming the dummy terminals 308, 326, and 328. In addition, by forming the dummy terminals 302, 326, and 328, the same height as that of the other external terminals 302, 304, 306, 322, and 324 can be formed. Therefore, when the pin card contacts the external terminals 302, 304, 306, 308, 312, 314, 316, 318, 322, 324, 326, and 328, the pin card contacts with a uniform pressure to prevent damage to the pin card contacts. can do.

As illustrated, the capacitance measurement test pattern 320 has a larger area than the TFT measurement test pattern 300 and the resistance measurement test pattern 310. Therefore, in order to effectively use the test pattern region of the mother substrate, it is preferable to alternately form the capacitance measurement test pattern 320 and the TFT measurement test pattern 300 or the resistance measurement test pattern 310.

Although only four test patterns are illustrated in FIG. 3, other test patterns that require testing may be formed in the test pattern region. That is, the resistance measurement test pattern 310 may form a test pattern for wiring resistance or a test pattern for contact resistance. In addition, the capacity measurement test pattern 320 may also form a test pattern for measuring not only the storage capacity but also various parasitic capacitances.

Although the test pattern for measuring the storage capacitor electrode and the contact resistance has been described, a test pattern requiring measurement can be manufactured.

Hereinafter, the structure and formation method of each test pattern are demonstrated.

4 is a vertical sectional view and a plan view of a test pattern for TFT characteristic measurement according to an embodiment of the present invention.

The vertical cross section shows the cross section along line IV-IV of the plan view.

First, the gate electrode 400 and the four external terminals 302, 304, 306, and 308 are formed in the test pattern region 480 in the same layer as the gate wiring of the panel region. Thereafter, the gate insulating layer 410 and the semiconductor layer 440 are formed on the gate electrode 400. After the semiconductor layer 440 is patterned, the source electrode 420 and the drain electrode 430 are formed to be connected to each of the external terminals 302 and 306, and the passivation layer 460 and the pixel electrode 470 are formed thereon. This completes the test pattern for TFT measurement.

5 is a vertical sectional view and a plan view of a test pattern for measuring a storage capacity according to an embodiment of the present invention.

The vertical sectional view shows the cross section along the V-V line of the plan view.

First, four external terminals 322, 324, 326, and 328 and the storage capacitor electrode 520 are formed in the test pattern region 520 in the same layer as the gate wiring of the panel region. At this time, the storage capacitor electrode 520 should be formed to the same size as the storage capacitor electrode formed in the TFT array. This is because the capacitance is proportional to the area of the electrode. Thereafter, the insulating film 510 is formed on the storage capacitor electrode 520, and then the pixel electrode 570 is formed on the storage capacitor electrode 520, and then connected to the external terminal 324 to complete the storage capacitor measurement test pattern.

6 is a plan view illustrating a test pattern for measuring contact resistance according to an embodiment of the present invention.

The vertical cross section shows the cross section along the line VI-VI of the plan view.

First, four external terminals 312, 314, 316, and 318 and a drain electrode 610 are formed in the test pattern region 600 in the same layer as the data wiring of the panel region. Thereafter, a passivation layer 620 is formed on the drain electrode 610, and a portion thereof is etched to form a contact hole 630. When the pixel electrode 640 is formed on the passivation layer 620 to be in contact with the drain electrode 610 through the contact hole 630, a test pattern for measuring contact resistance is completed. Of the four external terminals of the resistance measurement test pattern, two external terminals are used as current application terminals, and the other two external terminals are used as voltage measurement terminals.

Next, the test method of each test pattern is demonstrated.

The test is divided into TFT characteristics, resistance and capacitance measurements.

The method of measuring the characteristics of the TFT using the TFT characteristic measurement test pattern 300 is as follows.

A voltage of a predetermined value is applied to the external terminal 304 connected to the gate electrode 400 and the external terminal 302 connected to the source electrode 420, and the source electrode is changed while changing the voltage applied to the gate electrode 400. The current flowing in the channel between 420 and the drain electrode 430 is measured. For example, if 10V is applied to the source electrode 420 as the pixel voltage and the applied voltage of the gate electrode 400 is changed to -20V to 20V, the voltage-current characteristics of the TFT can be measured. The on voltage of the TFT is about 20V and the off voltage is about -5V. For the TFT to operate as a switch, the current ratio of the on-off must be 100 or more.

The method of measuring the accumulated capacity is as follows.

A constant voltage, for example, 5V, is applied to the two external terminals 322 and 324 connected to the test pattern 320 for storing capacitance measurement, and the storage capacitance is measured from these external terminals 322 and 324. In the panel region, the voltage is a voltage applied to one pixel.

The method of measuring contact resistance is as follows.

A constant current is applied to two of the four external terminals 312, 314, 316, and 318 connected to the test pattern 310 for measuring contact resistance, and the remaining two external terminals 314 and 316 are provided. When the voltage is measured, the total resistance of the test pattern 310 for measuring contact resistance can be obtained by dividing the applied current by the measured voltage. In order to measure the accurate contact resistance, the line resistance of the drain electrode 610 is measured using two external terminals 312 and 316 connected to the drain electrode 610, and the two external terminals 314, connected to the pixel electrode 640. After measuring the line resistance of the pixel electrode 640 using the 318, the two line resistances are subtracted from the total resistance to obtain an accurate contact resistance.

Next, the pin card used in the embodiment of the present invention will be described.

7 is a pin card for testing each test pattern according to an embodiment of the present invention.

The pin card consists of a pin 700 and a holder 710 for fixing the pin. The holder 710 moves in the front, rear, left, and right directions to test a test pattern at a desired position.

The pin card may use a pin card that is used in a conventional test pattern for resistance measurement. Since the test pattern for resistance measurement has conventionally used four external terminals, a pin card having four pins as described above has been used.

The placement of each pin on the pin card is made so that the pin tip points to a rectangular vertex of width a and length b. It can be manufactured in any form if it is made to match the arrangement of the external terminals of the test pattern.

By using such a pin card and the test pattern, in the embodiment of the present invention, all the test patterns can be measured with one pin card.

While many details are set forth in the foregoing description, it should be construed as an illustration of preferred embodiments rather than to limit the scope of the invention. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the claims and the equivalents of the claims.

According to the present invention, since the test is not performed by replacing the pin card according to each test pattern, the efficiency of the equipment can be increased. That is, whenever a new test pattern is formed, there is no need to manufacture a new pin card accordingly.

In addition, since the pin card is not replaced, the process time required for measuring the test pattern is shortened.

Claims (6)

A mother substrate divided into a plurality of panel regions and a test pattern region surrounding the panel region; A thin film transistor array formed in the panel region; A test pattern for measuring thin film transistor characteristics formed on the test pattern region, the external terminal being arranged to measure with a kind of pin card; Capacity test pattern; And a test pattern for resistance measurement. The test board of claim 1, wherein the external terminals of each test pattern are identically arranged in the same number. 3. The test board of claim 2, wherein the external terminals of the test pattern are four. The test pattern of claim 3, wherein one of four external terminals is a dummy terminal and two of the four external terminals are dummy terminals. Test board of improved liquid crystal display device. Preparing a mother substrate divided into a panel region and a test pattern region surrounding the panel region; Forming a thin film transistor array in the panel region and simultaneously forming a plurality of test patterns in the test pattern region to measure thin film transistor characteristics, capacitance, and resistance; And And measuring the thin film transistor characteristics, capacitance, and resistance while moving one type of pin card. 6. The test method of claim 5, wherein each test pattern is formed to have the same number and the same number of external terminals.