KR20040056833A - Semiconductor device and fabrication method thereof - Google Patents
Semiconductor device and fabrication method thereof Download PDFInfo
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- KR20040056833A KR20040056833A KR1020020083415A KR20020083415A KR20040056833A KR 20040056833 A KR20040056833 A KR 20040056833A KR 1020020083415 A KR1020020083415 A KR 1020020083415A KR 20020083415 A KR20020083415 A KR 20020083415A KR 20040056833 A KR20040056833 A KR 20040056833A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000012421 spiking Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로서, 더욱 상세하게는 낮은 캐패시턴스를 갖도록 하는 반도체 소자의 트렌치 및 트렌치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to trenches and trench manufacturing methods for semiconductor devices having low capacitance.
반도체 소자의 격리구조로서 트렌치 격리구조 (STI : shallow trench isolation)가 많이 사용되고 있다. 트렌치 격리구조에서는 반도체 기판 내에 트렌치를 형성하고 그 내부에 절연물질을 충진시킴으로써 필드영역의 크기를 목적한 트렌치의 크기로 제한하기 때문에 반도체 소자의 미세화에 유리하다.As the isolation structure of the semiconductor device, a trench trench structure (STI: shallow trench isolation) is widely used. In the trench isolation structure, by forming a trench in a semiconductor substrate and filling an insulating material therein, the size of the field region is limited to the desired trench size, which is advantageous for miniaturization of semiconductor devices.
도 1은 종래 트렌치 격리구조를 사용하여 반도체 소자를 제조한 것을 도시한 단면도로서, 여기에는, 실리콘웨이퍼(1)에 형성된 트렌치(2)에 의해 각 모스 트랜지스터 소자가 분리되어 있는 것이 도시되어 있다.FIG. 1 is a cross-sectional view showing the manufacture of a semiconductor device using a conventional trench isolation structure, in which each MOS transistor device is separated by a trench 2 formed in the silicon wafer 1.
그러나, 이러한 종래 트렌치 격리구조에서는 트렌치의 상부가 날카로운 모서리를 가져 그 모서리 부분에 응력이 집중되고, 트렌치 형성 과정에서 트렌치의 측벽 가장자리 부분이 움푹 패이기 쉬운 점 등에 의해 트렌치의 모서리 부분은 매우 취약한 부분이다.However, in the conventional trench isolation structure, the upper portion of the trench has sharp edges, and stress is concentrated at the corner portions thereof, and the edge portions of the trenches are very fragile due to the fact that the sidewall edges of the trenches are easy to dent in the trench formation process. to be.
그런데 반도체 소자가 점차 고집적화되면서 취약한 트렌치의 모서리 부분에 콘택이 위치하도록 오정렬되기가 쉬워지며, 이 경우 컨택 스파이킹에 의해 누설전류가 발생하는 등 소자에 치명적인 불량 요인으로 작용하는 문제점이 있었다.However, as semiconductor devices become increasingly integrated, it is easy to misalign them so that the contacts are located at the corners of the vulnerable trenches. In this case, there is a problem in that a leakage current is generated by contact spiking, which causes a fatal defect in the device.
또한 트렌치를 매립하도록 필드 산화막을 형성할 때 필드 산화막의 일부가 함몰하는 디핑(dipping) 현상이 발생하거나, 또는 트렌치 상부의 라이너 산화막이 경사를 가지는 덴트(dent) 현상이 발생한다.In addition, when the field oxide film is formed to fill the trench, a dipping phenomenon occurs in which a part of the field oxide film is recessed, or a dent phenomenon occurs in which the liner oxide film on the trench is inclined.
따라서 게이트산화막이 목적하는 두께로 균일하게 형성되지 못하고 부분적으로 얇게 형상되는 시닝(thinning) 현상을 초래하며, 이러한 시닝 현상으로 인해 게이트산화막의 절연파괴 전압 및 절연파괴 전하량 값이 저하되는 등 게이트산화막의 불량이 발생하는 문제점이 있었다.Therefore, the gate oxide film is not uniformly formed to a desired thickness, but causes a thinning phenomenon that is partially thin. The thinning phenomenon causes the gate oxide film to have low dielectric breakdown voltage and dielectric breakdown charge value. There was a problem that a defect occurs.
또 다른 문제점으로는 산화막으로 트렌치를 매립한 후 화학기계적 연마하는 중에 야기되는 스크래치(scratch) 문제 등으로 인해 소자의 수율이 저하되는 문제점이 있었다.Another problem is that the yield of the device is lowered due to a scratch problem caused during the chemical mechanical polishing after filling the trench with an oxide film.
본 발명은 이와 같은 종래 기술의 문제점을 해결하기 위해 제안된 것으로,그 목적은 산화막으로 트렌치를 매립함으로 인해 발생하는 발생하는 문제점을 해결하는 것이다.The present invention has been proposed to solve such problems of the prior art, and an object thereof is to solve a problem caused by filling a trench with an oxide film.
본 발명의 다른 목적은 컨택 오정렬에 대한 마진을 확보하는 것이다.Another object of the present invention is to secure a margin for contact misalignment.
도 1은 종래 트렌치 격리구조를 사용하여 모스 트랜지스터를 제조한 것을 도시한 단면도이다.1 is a cross-sectional view illustrating a MOS transistor fabricated using a conventional trench isolation structure.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
상술한 목적을 달성하기 위해 본 발명에서는 실리콘웨이퍼 상에 트렌치 깊이에 해당하는 두께로 산화막을 증착한 후 선택적으로 식각함으로써 트렌치산화막을 형성하고, 노출된 실리콘웨이퍼 상에 활성영역으로서 실리콘 에피택셜층을 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, a trench oxide film is formed by depositing an oxide film with a thickness corresponding to the depth of the trench on the silicon wafer and then selectively etching, and forming a silicon epitaxial layer as an active region on the exposed silicon wafer. It is characterized by forming.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 실리콘웨이퍼 상에 목적하는 트렌치의 깊이에 해당하는 두께로 산화막을 형성하고, 산화막을 선택적으로 식각하여 목적하는 트렌치의 폭으로 남김으로써 활성영역구를 형성하는 단계; 활성영역구를 통해 노출된 실리콘웨이퍼 상에 산화막보다 얇은 두께를 가지는 실리콘 에피택셜층을 성장시키는 단계; 실리콘 에피택셜층 상에 소정폭의 게이트산화막 및 게이트를 형성하는 단계; 게이트를 마스크로 하여 실리콘 에피택셜층 내에 불순물을 도핑하여 엘디디(LDD : lightly doped drain) 영역을 형성하는 단계; 실리콘 에피택셜층 상부의 산화막 측벽 및 게이트의 측벽에 사이드월을 형성하는 단계; 및 게이트 및 사이드월을 마스크로 하여 실리콘 에피택셜층 내에 엘디디 영역 형성 시보다 고농도로 불순물을 도핑하여 소스 및 드레인 영역을 형성하는 단계를 포함하여 이루어진다.That is, in the method of fabricating a semiconductor device according to the present invention, an active layer is formed by forming an oxide film on a silicon wafer at a thickness corresponding to the desired depth of the trench, and selectively etching the oxide film to leave the desired trench width. Doing; Growing a silicon epitaxial layer having a thickness thinner than that of an oxide film on the silicon wafer exposed through the active region sphere; Forming a gate oxide film and a gate having a predetermined width on the silicon epitaxial layer; Doping impurities into the silicon epitaxial layer using the gate as a mask to form a lightly doped drain (LDD) region; Forming sidewalls on the oxide sidewalls and the sidewalls of the gates over the silicon epitaxial layer; And forming a source and a drain region by doping impurities at a higher concentration than the formation of the LED region in the silicon epitaxial layer using the gate and the sidewall as masks.
여기서 산화막은 3000-5000Å 두께로 형성하는 것이 바람직하고, 실리콘 에피택셜층은 산화막보다 700-1300Å 더 얇은 두께로 성장시키는 것이 바람직하다.The oxide film is preferably formed to a thickness of 3000-5000 kPa, and the silicon epitaxial layer is preferably grown to a thickness of 700-1300 kPa thinner than the oxide film.
이하 본 발명의 일 실시예에 따른 반도체 소자 및 그 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 2d는 본 발명의 일 실시예에 따라 제조된 반도체 소자를 도시한 단면도로서, 이에 도시된 바와 같이, 실리콘웨이퍼(11) 상에는 트렌치산화막(12')이 목적하는 트렌치의 깊이에 해당하는 두께를 가지도록 형성되고, 목적하는 트렌치의 폭에 해당하는 폭을 가지도록 패터닝되어 있다.FIG. 2D is a cross-sectional view illustrating a semiconductor device manufactured according to an embodiment of the present invention. As shown in FIG. 2D, the trench oxide film 12 ′ has a thickness corresponding to a desired trench depth on the silicon wafer 11. It is formed to have, and is patterned to have a width corresponding to the width of the desired trench.
트렌치산화막(12')의 사이 및 실리콘웨이퍼(11) 상에는 소자 활성영역으로서 트렌치산화막(12')보다 두께가 얇은 실리콘 에피택셜층(13)이 형성되어 있다.Between the trench oxide film 12 'and on the silicon wafer 11, a silicon epitaxial layer 13 having a thickness thinner than the trench oxide film 12' is formed as an element active region.
실리콘 에피택셜층(13) 상에는 게이트산화막(14) 및 게이트(15)가 소정폭으로 형성되어 있고, 게이트(15)의 외방 및 실리콘웨이퍼(11) 내에는 불순물이 저농도로 도핑된 엘디디 영역(16)이 형성되어 있다.The gate oxide film 14 and the gate 15 are formed on the silicon epitaxial layer 13 to have a predetermined width, and the LED region in which impurities are doped with low concentration is formed outside the gate 15 and in the silicon wafer 11. 16) is formed.
실리콘 에피택셜층(13) 상부의 트렌치산화막(12') 측벽 및 게이트(15)의 측벽에는 사이드월(17)이 형성되어 있고, 사이드월(17)의 외방으로 엘디디 영역(16)보다 더 깊은 실리콘에피택셜층(13) 내에 불순물이 고농도로 도핑된 소스 및 드레인 영역(18)이 형성되어 있다.Sidewalls 17 are formed on the sidewalls of the trench oxide film 12 ′ and the sidewalls of the gate 15 on the silicon epitaxial layer 13 and outward from the LED region 16. Source and drain regions 18 doped with a high concentration of impurities are formed in the deep silicon epitaxial layer 13.
여기서, 사이드월(17)은 실리콘 에피택셜층(13) 상부의 트렌치산화막(12') 측벽에도 형성되어 있어서, 콘택이 트렌치산화막(12')의 가장자리에 위치하도록 오정렬된 경우 컨택 스파이킹 현상을 방지해준다.Here, the sidewalls 17 are also formed on the sidewalls of the trench oxide film 12 'on the silicon epitaxial layer 13, so that contact spikes may occur when the contacts are misaligned at the edges of the trench oxide film 12'. Prevents.
그러면, 상술한 구조의 본 발명에 따른 반도체 소자 제조 방법을 도 2a 내지2d를 참조하여 설명한다.Next, a method of manufacturing a semiconductor device according to the present invention having the above-described structure will be described with reference to FIGS. 2A to 2D.
먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11) 상에 트렌치 영역이 될 산화막(12)을 형성한다. 이 때 산화막(12)은 목적하는 트렌치 깊이에 해당하는 두께로 증착하면 되며, 보통 3000-5000Å의 두께로 증착한다.First, as shown in FIG. 2A, an oxide film 12 to be a trench region is formed on the silicon wafer 11. At this time, the oxide film 12 may be deposited to a thickness corresponding to the desired trench depth, and is usually deposited to a thickness of 3000-5000Å.
산화막(12)의 증착방법을 특별히 한정할 필요는 없으며 통상적인 방법을 이용하며, 일 예로서, 상압화학기상증착(APCVD) 또는 저압화학기상증착(LPCVD) 방법으로 티이오에스(TEOS)막을 형성할 수 있다.There is no need to specifically limit the deposition method of the oxide film 12, and a conventional method is used, and as an example, a TEOS film is formed by an atmospheric pressure chemical vapor deposition (APCVD) or a low pressure chemical vapor deposition (LPCVD) method. Can be.
다음, 도 2b에 도시된 바와 같이, 소자 활성영역(active area) 형성을 위해 목적하는 활성영역의 폭에 해당하는 크기로 산화막(12)을 선택적으로 식각하여 활성영역구(100)를 형성하며, 따라서 남아있는 산화막(12)은 트렌치산화막(12')이 된다.Next, as shown in FIG. 2B, the active layer sphere 100 is formed by selectively etching the oxide film 12 to a size corresponding to a width of a target active region for forming an active region of the device. Therefore, the remaining oxide film 12 becomes the trench oxide film 12 '.
이어서, 활성영역구(100)를 통해 노출된 실리콘웨이퍼(11) 상에 실리콘 에피택셜층(epitaxial layer)(13)을 성장시킨다. 이 때 실리콘 에피택셜층(13)은 트렌치산화막(12') 보다 700-1300Å 정도 낮은 높이가 되는 두께로 성장시킨다.Subsequently, a silicon epitaxial layer 13 is grown on the silicon wafer 11 exposed through the active region sphere 100. At this time, the silicon epitaxial layer 13 is grown to a thickness that is about 700-1300 mm lower than the trench oxide film 12 '.
다음, 도 2c에 도시된 바와 같이, 실리콘 에피택셜층(13) 상에 게이트산화막(14)을 형성하고, 게이트산화막(14) 상에 목적하는 게이트의 두께에 해당하는 두께로 다결정실리콘층을 형성한 후, 다결정실리콘층 및 게이트산화막을 목적하는 게이트의 폭으로 식각한다. 이로써 다결정실리콘으로 이루어진 게이트(15)를 형성한다.Next, as shown in FIG. 2C, a gate oxide film 14 is formed on the silicon epitaxial layer 13, and a polysilicon layer is formed on the gate oxide film 14 to a thickness corresponding to a desired gate thickness. After that, the polysilicon layer and the gate oxide film are etched to the width of the desired gate. As a result, a gate 15 made of polycrystalline silicon is formed.
이어서, 게이트(15)를 마스크로 하여 실리콘 에피택셜층(13) 내에 불순물을저농도로 주입하여 엘디디(LDD : lightly doped drain) 영역(16)을 형성한다.Subsequently, a lightly doped drain (LDD) region 16 is formed by implanting impurities into the silicon epitaxial layer 13 at low concentration using the gate 15 as a mask.
다음, 도 2d에 도시된 바와 같이, 실리콘웨이퍼(11)의 상부 전면에 질화막을 증착한 후 게이트(15) 및 트렌치산화막(12')의 양 측벽에만 질화막을 남기도록 식각하여 사이드월(17)을 형성한다.Next, as shown in FIG. 2D, after the nitride film is deposited on the upper surface of the silicon wafer 11, the sidewall 17 is etched to leave the nitride film only on both sidewalls of the gate 15 and the trench oxide film 12 ′. To form.
이 때 종래 모스 트랜지스터에서 게이트(15)의 측벽에만 사이드월을 형성한 것과는 달리, 트렌치산화막(12')의 양 측벽에도 질화막을 남겨 사이드월을 형성하는 특징이 있다.At this time, unlike sidewalls formed only on the sidewalls of the gate 15 in the conventional MOS transistor, the sidewalls of the trench oxide film 12 'are formed by leaving a nitride film on both sidewalls.
이와 같이 트렌치산화막(12')의 양 측벽에 형성된 사이드월은 컨택이 트렌치산화막(12')의 가장자리에 위치하도록 오정렬된 경우 발생하는 컨택 스파이킹을 방지해준다.As such, sidewalls formed on both sidewalls of the trench oxide layer 12 ′ prevent contact spiking that occurs when the contacts are misaligned at the edges of the trench oxide layer 12 ′.
이어서, 게이트(15) 및 사이드월(17)을 마스크로 하여 실리콘 에피택셜층(13) 내에 불순물을 고농도로 주입하여 소스 및 드레인 영역(18)을 형성한다.Subsequently, the source and drain regions 18 are formed by implanting impurities at a high concentration into the silicon epitaxial layer 13 using the gate 15 and the sidewalls 17 as masks.
상술한 바와 같이 본 발명에서는 트렌치 깊이에 해당하는 두께로 산화막을 증착한 후 선택적으로 식각함으로써 트렌치산화막을 형성하기 때문에, 종래 트렌치를 매립하는 방법으로 트렌치산화막을 형성하는 경우 발생하였던 문제점들, 즉, 디핑 현상, 덴트 현상, 시닝 현상 등을 방지하여 게이트산화막의 불량 발생을 방지하고, 스크래치 문제를 해결하여 결과적으로 수율을 향상시키는 효과가 있다.As described above, in the present invention, since a trench oxide film is formed by depositing an oxide film to a thickness corresponding to the depth of the trench and then selectively etching, the problems occurring when the trench oxide film is formed by filling a trench in the related art, that is, Dipping phenomenon, dent phenomenon, thinning phenomenon and the like to prevent the occurrence of defects in the gate oxide film, and to solve the scratch problem has the effect of improving the yield.
또한, 트렌치의 양 측벽에 사이드월을 형성하므로 컨택이 오정렬되어 트렌치의 가장자리인 사이드월 상에 위치하더라도 누설전류가 발생되지 않으며, 따라서 컨택 정렬시 공정마진이 확보되는 효과가 있다.In addition, since sidewalls are formed on both sidewalls of the trench, even if contacts are misaligned and positioned on sidewalls that are edges of the trench, no leakage current is generated, thereby ensuring a process margin when aligning contacts.
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