KR20040054835A - Hard Ware Watchdog Circuit and Method - Google Patents

Abstract

PURPOSE: A hardware watchdog circuit and a method thereof are provided to generate a watchdog signal to a CPU in an abnormal state by monitoring the state of the CPU and realize a watchdog timer to other device. CONSTITUTION: A watchdog controller(120) includes the watchdog timer(125) that is restarted whenever a monitoring signal is inputted from the CPU(110) in a preset period, and outputs a control signal and a reset signal if the watchdog timer is expired. A watchdog generator(130) generates the watchdog signal to a power-on reset port of the CPU by responding to the control signal and the reset signal. The watchdog generator includes a watchdog register(131) recording an enable/disable state, and the state that the CPU is reset by the watchdog signal.

Description

Hardware Watchdog Circuit and Method

The present invention relates to a watchdog circuit and method, and more particularly, to a watchdog circuit and method for resetting the central processing unit in the event of an abnormality using a hardware watchdog circuit.

In general, a watchdog function is provided to check whether the central processing unit performs a normal operation in a system equipped with a central processing unit. Such watchdog implementations typically include software watchdog technology and hardware watchdog technology.

The software watchdog technology drives the CPU when a certain value is written to the Software Service Register during a software watchdog timeout inside the CPU. Otherwise, a software watchdog is generated and the central processing unit is reset internally. However, since the software watchdog technology uses an internal reset, the CPU may not boot normally when the PLL (Phase Lock Loop) and the register value of the CPU are not initialized.

The hardware watchdog technology uses a central processing unit and a watchdog circuit, which receives a watchdog signal from a watchdog circuit implemented with an electric programmable logic device (EPLD) that executes a watchdog algorithm. .

1 is a block diagram illustrating a conventional hardware watchdog circuit, and as shown in FIG. 1, the CPU 1 includes a central processing unit 10 and a watchdog circuit 20. The watchdog generation circuit 10 includes a watchdog timer 21 and an 8-bit watchdog register 22 therein.

The central processing unit 10 has a write enable port / WE, an output enable port / OE, a data port Data, and a power on reset port / PORESET. The watchdog circuit 20 has a first output port IO 0, a first input port IO3, a second input port IO4, and a data port Data.

Referring to FIG. 1, the watchdog timer 21 of the watchdog circuit 20 is counted in a watchdog time period, and the watchdog circuit 20 receives a first input port from the central processing unit 10 during the watchdog time period. (IO 3) monitors whether a write enable signal has been received. At this time, if the central processing unit 10 outputs the write enable signal through the write enable port (/ WE) to perform the watchdog function, a "1" is displayed in the most significant bit (WDT_EN) of the watchdog register 22. This is recorded. The watchdog timer 22 is then cleared to start counting. The watchdog circuit 20 maintains the power-on reset port / PORESET of the CPU 10 at the high level through the first output port IO 0. In addition, the CPU 10 reads the value of the watchdog register 21 through the data port Data and then enables the output to the second input port IO 4 through the output enable port / OE. Output the signal.

On the other hand, when an abnormality occurs in the CPU 10, the watchdog register 22 may not read or write the watchdog register 121 through the write enable port / WE and the data port Data. As a result, when the watchdog circuit 20 does not receive the write enable signal and the output enable signal from the CPU 10 until the watchdog timeout occurs, the watchdog circuit 20 returns the first output port IO 0. Through the power-on reset port (/ PORESET) of the central processing unit 10 generates a low-level watchdog signal. The CPU 10 then receives a watchdog signal and resets it.

However, the hardware watchdog circuit described above has a problem that a lot of resources are used in the watchdog circuit because the watchdog timer is provided in the watchdog circuit. In addition, the board may not operate normally because only the central processing unit is booted and externally connected devices are not initialized.

Accordingly, it is an object of the present invention to provide a hardware watchdog circuit and method for monitoring a state of a central processing unit and generating a watchdog signal to the central processing unit in case of abnormality.

Another object of the present invention is to provide a hardware watchdog circuit and method for implementing the watchdog timer in a separate device.

The apparatus for achieving the object of the present invention is a watchdog circuit for monitoring the central processing unit in a system including a central processing unit, which is restarted whenever a monitoring signal is input within a predetermined period from the central processing unit. A watchdog timer including a watchdog timer and outputting a control signal and a reset signal when the watchdog timer expires, and sending a watchdog signal to a power-on reset port of the CPU in response to the control signal and the reset signal. It characterized in that it comprises a watchdog generating unit.

And a method for achieving the objects of the present invention in the system comprising a watchdog control unit for monitoring the central processing unit and the watchdog generating unit for generating a watchdog signal by the watchdog control unit, abnormal operation of the central processing unit A method for generating a watchdog signal to the central processing unit, the watchdog controller restarts a watchdog timer whenever a watch signal is input within a predetermined period from the central processing unit by the watchdog controller, and the watchdog timer expires. Outputting a control signal and a reset signal each time, and if the monitoring signal is not input until the watchdog timer expires, the watchdog generation unit checks whether the control signal and the reset signal are received from the watchdog control unit. And a reset scene received from the watchdog controller by the watchdog generator. And generating a watchdog signal for powering on and resetting the CPU according to the call.

1 is a block diagram showing a conventional watchdog circuit,

2 is a block diagram illustrating a watchdog circuit according to an exemplary embodiment of the present invention;

3 is a circuit diagram showing in detail the block diagram of FIG.

4 is a flowchart illustrating a watchdog signal generation operation for resetting a CPU using a watchdog circuit according to an exemplary embodiment of the present invention;

5A is a timing diagram illustrating outputs of respective ports when power is applied in a watchdog circuit according to an exemplary embodiment of the present invention;

5B is a timing diagram illustrating outputs of respective ports when enabled in a watchdog circuit according to an embodiment of the present invention;

FIG. 5C is a timing diagram illustrating outputs of respective ports in an abnormal state of the CPU in the watchdog circuit according to an exemplary embodiment of the present invention. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.

In addition, in the following description, many specific details such as specific signals and signal levels are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, the configuration of a watchdog circuit according to an embodiment of the present invention will be described with reference to the drawings.

2 is a block diagram illustrating a watchdog circuit according to an exemplary embodiment of the present invention, and FIG. 3 is a circuit diagram illustrating the block diagram of FIG. 2 in more detail.

As shown in FIGS. 2 and 3, the watchdog circuit 100 is connected to a central processing unit (CPU) 110 and monitors the central processing unit 110 to provide a watchdog timer function. The watchdog control unit 120 and the watchdog generation unit 130 which receive a control signal from the watchdog control unit 120 and generate a watchdog signal when an abnormality occurs in the central processing unit 110. In this case, the CPU 110 has hardware reset (H / W Reset), software reset (S / W Reset), and power on reset (Power on Reset) ports, and among these ports, in the embodiment of the present invention, This is explained using on reset. The central processing unit 110 uses the MPC860 of Motorola (Motorola), it is possible to use a central processing unit having similar ports in addition to the MPC860.

The watchdog generator 130 is an electric programmable logic device (EPLD) that implements a hardware watchdog algorithm as a logic, and receives a control signal from the watchdog controller 120 and meets a predetermined condition, thereby processing the central processing unit 110. The watchdog signal is output to the power-on reset port 112. The watchdog generator 130 includes an 8-bit watchdog register (WDTSR) 131 that stores certain signals for outputting the watchdog signal. The watchdog register 131 uses the highest bit (MSB) as the watchdog timer enable (WDT_EN) and the least significant bit (LSB) as the watchdog register set (WDRS). do. The watchdog timer enable (WDT_EN) bit may be read / written by the central processing unit 110 and has a value of “0” at power-on. The watchdog register set (WDRS) bit may be written only by the CPU 110 and has a value of "0" at power-on.

The watchdog control unit 120 includes a watchdog timer 125 therein, and if the watch signal is not input from the central processing unit 110 within at least 1 second or 1.6 seconds, which is the period of the watchdog timer 125, the watchdog Sends a control signal to the poison generator 130. The watchdog control unit 120 uses the MAX705 of MAXIM, and is used to monitor microcomputer systems and control systems as microprocessor management circuits.

The watchdog circuit of the reset device configured as described above will be described in more detail with reference to FIG. 3. The central processing unit 110 outputs a 500 ns pulse width and a 3.3 V level monitoring signal every predetermined period (for example, at least 800 ms). A port (PB20) 111 and a power-on reset port (/ PORREST) 112 for receiving a watchdog signal from the watchdog generation unit 130 are provided. The CPU 110 may include a write enable port (/ WE) 113, an output enable port (/ OE) 114, and 8 outputting an enable signal to the watchdog generator 130. It has a data port (Data) 115 for transmitting and receiving bit watchdog register values.

The watchdog control unit 120 may include a watchdog input port (WDI) 121 for receiving a monitoring signal output from the output port 111 and a watchdog output port for outputting a control signal to the watchdog generator 130 (/). WDO) 122, a manual reset port (/ MR) 123 connected to the watchdog output port (WDO) 122, and a reset port (/ RESET) 124 for outputting a reset signal to the watchdog generator 130 Has It has other power supply ports (VCC), ground ports (GND), input ports (PFI), and output ports (PFO).

The watchdog generator 130 is connected to the power-on reset port 112 of the central processing unit 110 and generates a watchdog signal according to a predetermined condition. And a first input port IO 1 connected to 122 and a second input port IO 2 connected to the reset port 124. The third input port IO 3 connected to the write enable port 113 of the central processing unit 110, the fourth input port IO 4 connected to the output enable port 114, and the central processing unit ( It has a data port (Data) for transmitting and receiving the data port 115 of the 110 and the watchdog register value.

The watchdog signal generation operation according to the hardware watchdog circuit configured as described above will be described with reference to the accompanying drawings.

4 is a flowchart illustrating an operation of a watchdog generator for resetting a CPU using a watchdog circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, when power is supplied to the watchdog circuit 100 in step 200, the watchdog generator 130 is initialized and the watchdog timer enable bit (WDT-EN) of the watchdog register 131 is performed. And watchdog register set (WDRS) bits are both set to " 0 ".

When the initialization process of the watchdog circuit 100 is completed, the watchdog timer enable (WDT_EN) bit of the watchdog generator 130 is set to “1” by the central processing unit 110 in step 210. Switch to Dock Enable. The watchdog generator 130 waits to receive a control signal output from the watchdog controller 120.

Then, in step 220, the watchdog generator 130 checks whether a control signal is input from the watchdog controller 120. In this case, since the control signal is input to the enable state when the control signal is input, the watchdog register set (WDRS) of the watchdog register is recorded as “1” by the CPU 110 in step 240. On the other hand, if not, the current state is maintained at step 230 and the process returns to step 220.

Then, in step 250, the watchdog generation unit 130 checks whether the reset signal is received from the watchdog control unit 120. If the control signal is received in step 260 watchdog generation unit 130 generates a watchdog signal to the central processing unit (110). Accordingly, the central processing unit 110 receives the watchdog signal through the power on reset port 112 and resets the watchdog signal. On the other hand, if no control signal is received, check whether the control signal is continuously received,

When the central processing unit 110 is reset, the watchdog generation unit 130 writes the watchdog timer enable (WDT_EN) bit of the watchdog register 131 to "0" in step 270 to the watchdog disable state. Switch. In addition, since a predetermined time passes after the reset of the central processing unit 110 in step 280, the least significant bit WDRS of the watchdog register 131 is recorded as “0” by the central processing unit 110. ) Becomes the initial power-on state. Then, the watchdog generation unit 130 returns to step 210 and waits until it is switched to the watchdog enable state and repeats the above-described processes.

The watchdog signal generation process will be described in more detail with reference to a timing chart showing output waveforms of respective ports.

FIG. 5A is a timing diagram illustrating states of respective ports when power is applied in the watchdog circuit according to an embodiment of the present invention, and FIG. 5B is a view illustrating ports of the enable port in the watchdog circuit according to an embodiment of the present invention. 5C is a timing diagram illustrating outputs, and FIG. 5C is a timing diagram illustrating outputs of respective ports when the central processing unit is abnormal in the watchdog circuit according to the exemplary embodiment of the present invention.

Referring to FIG. 5A, when each port maintains a low level state and power of 3.3 V is applied to the watchdog circuit 100 at a time t1, the watchdog input port of the watchdog control unit 120 ( 131 maintains a low level since the central processing unit 110 is before being reset. In addition, when the control signal output from the watchdog output port 122 is input to the manual reset port 123 at the time t1, the watchdog output port 122 of the watchdog control unit 120 goes low to the watchdog generator 130. It outputs a control signal of the level and then transitions to the high level after 70 ns (t2). The manual reset port 123 connected to the watchdog output port 122 is also switched to the high level. At this time, the watchdog timer 125 starts counting, and when the control signal of the watchdog output port 122 is outputted, the watchdog timer 125 is cleared and starts counting again.

When the watchdog output port 122 is switched to the high level, the reset port 124 outputs a low level reset signal to the second input port IO 2 of the watchdog generator 130 at time t, and after 200 ms ( At time t3), the level is switched to the high level. At this time, the watchdog register 131 of the watchdog generator 130 receives the watchdog timer enable (WDT_EN) bit and the watchdog register set (WDRS) bit of the watchdog register 131 when the watchdog register 131 receives the low level reset signal. Set to "0" to keep the low level.

When the low level reset signal is output, the power-on reset port 112 of the central processing unit 110 passes through the first output port IO 0 of the watchdog generator 130 at a time t2. After 200ms (t3 time), a high level power-on reset signal is received. This causes the CPU 110 to be powered on and reset.

When the watchdog timer expires after the central processing unit 110 is reset, the watchdog output port 123 transmits a 70 ns low level control signal to the first output port IO 1 of the watchdog generator 130. Output Accordingly, the reset port 112 also outputs a reset signal to the watchdog generator 130 for 200 ms (t5 to t6). At this time, unlike in the period t2 to t3, the reset signal from the watchdog generator 130 to the power-on reset port 112 so that the central processing unit 110 is not reset after the initial power-on reset in the watchdog disable state. Is not input and remains at the low level.

Referring to FIG. 5B, the central processing unit 110 is reset to the watchdog input port 121 of the watchdog control unit 120 through the output port 111 after a preset time, and then at a high level for 500 ns every 800 ms. Generates a surveillance signal. The central processing unit 110 generates a write enable signal to the third input port IO 3 at time t 3 to perform a watchdog function. Then, "1" is written by the central processing unit 110 in the most significant bit WDT_EN of the watchdog register 131 to become a watchdog enable state. In such an enable state, the watchdog control unit 120 monitors whether the monitoring signal is input to the watchdog input port within at least 1 second from the central processing unit 110.

The watchdog output port 122 and the manual reset port 123 maintain a high level when the watchdog signal is input to the watchdog input port 121 within the watchdog timeout 1s (t2 to t6). As a result, the reset port 124 also maintains a high level. The watchdog generator 130 also maintains a high level of the power-on reset port 112 output to the CPU 110 by the signal output from the reset port 124.

Referring to FIG. 5C, when a monitoring signal having a 500 ns pulse width is input to the watchdog input port 121 at a time t1, the watchdog timer 125 is cleared and starts counting again. At this time, the state of each port until the time t3 is the same as the state of each port of FIG.

Then, when an abnormality occurs in the central processing unit 110 and the monitoring signal is not input within the timeout (t1 to t3) at the time t3, the watchdog input port 121 maintains the low level. Accordingly, the watchdog output port 122 outputs a low level control signal to the first input port IO 1 of the watchdog generator 130 for 70 ns, and the manual reset port 123 is the watchdog output port 122. Receive the control signal output from). At this time, since the watchdog timer enable (WDT_EN) bit of the watchdog register 131 is in an enabled state set to "1", the watchdog generator 130 may set the watchdog register set (WDRS) according to the control signal. Write the bit to "1". In addition, the reset port 124 outputs a low level reset signal to the second input port IO 2 of the watchdog generation unit 130 for 200 ms (t4 to t5).

Then, the watchdog generation unit 130 receiving the reset signal is an enable state in which the watchdog timer enable (WDT_EN) bit of the watchdog register 131 is written as "1". The watchdog signal of a low level is output to the power on reset port 112 of the CPU 110 through the first output port IO 0 of 130. The CPU 110 is then reset by the watchdog signal. At this time, since the watchdog generation unit generates a watchdog signal to the CPU 110, the watchdog generator 131 records the watchdog timer enable (WDT_EN) bit of the watchdog register 131 as "0" to switch to the disabled state.

After a predetermined time has passed since the central processing unit 110 is reset, the watchdog register set (WDRS) bit of the watchdog register 131 is written as “0” by the central processing unit 110.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention can reduce the resources of the watchdog generator by providing a hardware watchdog timer in a separate watchdog controller, and since a watchdog signal is input from an external watchdog generator, a register inside the central processing unit. Can be initialized. When the hardware watchdog signal is generated, the watchdog register of the watchdog generator has an initial value, thereby making board operation more stable.

Claims (4)

A watchdog circuit for monitoring the central processing unit in a system comprising a central processing unit, A watchdog timer for restarting each time a monitoring signal is input within a predetermined period from the central processing unit, and outputting a control signal and a reset signal when the watchdog timer expires; And a watchdog generator configured to generate a watchdog signal to a power-on reset port of the CPU in response to the control signal and the reset signal. The method of claim 1, The watchdog generating unit includes a watchdog register for recording an enable and disable state by the CPU and a state of whether the CPU is reset by the watchdog signal. Hardware watchdog circuit. The method of claim 2, The watchdog register of the watchdog generator is set to an initial value when a watchdog signal is generated. In the system comprising a watchdog control unit for monitoring the central processing unit and the watchdog generating unit for generating a watchdog signal by the watchdog control unit, the watchdog signal is generated to the central processing unit when the central processing unit is abnormally operated. In the method for Restarting a watchdog timer each time a watchdog signal is input within a predetermined period from the CPU by the watchdog controller and outputting a control signal and a reset signal each time the watchdog timer expires; If the watchdog signal is not input until the watchdog timer expires, checking whether the watchdog generator receives a control signal and a reset signal from the watchdog controller; And generating a watchdog signal for powering on and resetting the central processing unit according to the reset signal received from the watchdog control unit by the watchdog generator.