JP2002532773A - Reset-out circuit with feedback - Google Patents

Abstract

(57) [Summary] A microcontroller integrated circuit according to the present invention includes a reset input. When a signal is received at the reset input, the microcontroller resets itself and outputs a reset signal to other devices in the system controlled by the microcontroller. A reset signal is provided to a reset input. To prevent the reset signal generated by the microcontroller from resetting the microcontroller again, the microcontroller inhibits the signal from the reset input under software control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a reset-out circuit, and more particularly to a microcontroller with a reset-out circuit that can feed back a reset-out signal of a microcontroller to its reset-in input without locking the microcontroller into a reset state. .

[0002]

[Prior art]

The microcontroller typically has a reset state in which various circuits of the microcontroller are initialized prior to commencing normal operation. For example, when the power is turned on for the first time, or when an internal or external state having a problem in keeping the microcontroller operating normally occurs, the reset state is entered. Upon entering this reset state, the microcontroller is initialized to a known state and can operate normally again.

A general microcontroller has a reset-in input pin, and receives, for example, an external reset signal instructing a reset of the microcontroller in the event of a power failure. The microcontroller is reset by an internal reset in addition to being reset by an external reset signal. The microcontroller outputs a reset-out signal from a reset-out output pin in response to an external reset signal received at the reset-in input pin or an internally generated reset signal. For example, the internal reset signal is generated by a central processing unit (CPU) of the microcontroller in response to execution of a reset command, timeout of a monitoring timer, or detection of some error condition.

Preferably, the microcontroller reset-out signal is supplied to all circuits of the device because the microcontroller reset-out signal is generated regardless of whether an external reset state or an internal reset state occurs. Used as a single global reset signal. When used as a global reset signal, the microcontroller reset-out signal is fed back from the reset-out output pin to the microcontroller reset-in input pin and is also provided to other devices in the system.

[0005]

[Problems to be solved by the invention]

When feeding back the microcontroller's reset out signal to the microcontroller's reset in input pin, a potential problem arises in that the microcontroller is permanently locked in the reset state. Another problem occurs when the duration of the global system reset signal supplied from the microcontroller, that is, the pulse width is too short. That is, if the global system reset signal is too short, all devices in the system may not be able to be correctly reset.

Accordingly, the microcontroller can be properly reset in response to both an external reset signal and an internally generated reset signal, and the global system reset output is output from the microcontroller reset out output pin. There is a need for a reset device that can provide feedback at the reset-in input pin of the microcontroller without the additional problem of permanently locking the microcontroller to the reset state.

[0007]

[Means for Solving the Problems]

One object of the present invention relates to providing a reset device in a microcontroller that can overcome the problems of conventional reset devices.

Another object of the present invention is to provide a reset device capable of distinguishing between an externally supplied reset signal and an internally generated reset signal.

It is another object of the present invention to provide a reset device capable of providing a reset out pulse having a sufficient duration whenever an internally generated reset signal is detected. .

Yet another object of the present invention is to provide feedback of a reset out pulse from a reset out output pin of a microcontroller to a reset in input pin of the microcontroller without permanently latching up the microcontroller. It is to provide a reset device that can be used.

It is yet another object of the present invention to provide a reset device that allows a user to disable all reset-out functions of a microcontroller under software control.

It is another object of the present invention to provide all of the above objects with any flip-chip involved.
It is to provide a reset device that can be achieved without resetting the flop at reset or after turning on the power.

The present invention achieves the above and other objects by, for example, providing a reset device in a microcontroller. The reset device includes, for example, a counter that outputs a count start signal after counting down a predetermined count number. The input circuit of the reset device supplies a start signal for instructing start of countdown to the counter in response to the input reset signal. The output device is
A reset-out signal is output in response to the start signal and the count start signal. The start signal is suppressed by a control signal provided when an external reset signal is received from the control device at an input pin of the microcontroller.

The input device has an AND gate. The AND gate includes, in addition to receiving the input reset signal, a delayed and inverted version of the input reset signal;
A control signal is also received. The reset device further includes a NOR gate. NO
The R gate receives the start signal and the count start signal, and outputs a reset out signal. The OR gate receives the output from the counter and provides a counter activation signal.

[0015] Further features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. The drawings illustrate a preferred embodiment of the present invention, wherein the same elements are designated by the same reference numerals.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a microcontroller 100 having a reset-in input pin 105 and a reset-out output pin 110. The global reset signal is received at reset-in input pin 105. The global reset signal is supplied from either an external reset signal generator 115 or a reset out output pin 110 of the microcontroller that is connected back to the reset in input pin 105. For simplicity, the signal received at the reset-in input pin 105 of the microcontroller is hereafter referred to as the external reset signal. The external reset signal is provided to the clock generation logic 120 of the microcontroller 100.

In addition to the global or external reset signal received at the reset input pin 105 of the microcontroller, the clock generation logic 120 also receives an internal reset request signal from the internal hardware logic 125 of the microcontroller 100. By way of example, internal hardware logic 125 includes the state of the hardware,
For example, monitoring the level of power or storage battery, for example, when the power is reduced,
If the oscillator fails, it generates an internal reset request signal.

In the embodiment shown in FIG. 1, the internal reset request signal
It is generated in response to a 30 timeout (expiration) or a reset command from the central processing unit (CPU) 135. The timeout and the central processing unit (CPU) command signal are provided to an OR gate 140, which outputs an internal reset request signal to the clock generation logic 120.

In response to an internal reset request signal from internal hardware logic 125 or an external reset signal received at the microcontroller's reset-in input pin 105, clock generation logic 120 outputs a RESET_N signal to reset circuit 145. . In addition to the RESET_N signal, the clock generation logic 120 outputs an inhibit signal CG_EXTRST_N to the reset circuit 145 when an external reset signal is received at the reset-in input pin 105 of the microcontroller. Thus, this inhibition signal CG_EX
TRST_N indicates that the reset signal received by clock generation logic 120 is not an internal reset request signal from internal hardware logic 125 but an external reset signal from reset in input pin 105 of the microcontroller. Disable operation.

The reset circuit 145 is also connected to a central processing unit (CPU) 135,
D (Software Write Data) signal is received.
The SWD signal is the reset circuit 145 disabled by the inhibit signal CG_EXTRST_N.
Activate the action. Clock generation logic 120 outputs both the RESET_N signal and the inhibit signal CG_EXTRST_N in response to an external reset signal, as described above, in contrast to RESET_N in response to an internal reset signal. Outputs only the signal.
In one embodiment, the inhibit signal CG_EXTRST_N has a high logic level when an external reset signal is received by the clock generation logic 120 and has a low logic level when an internal reset request signal is received. As described later, the microprocessor RESET_OUT output from the reset-out output pin 110
The OUT_N signal is output from the clock generation logic 120 to the reset circuit 145 by the inhibition signal CG_EX.
Suppressed if TRST_N is supplied.

In response to the RESET_N signal, the reset circuit 145 outputs a RESET_OUT_N signal from the reset output pin 110 of the microcontroller 100 when the inhibition signal CG_EXTRST_N is absent, for example, when it is at a low logic level. The RESET_OUT_N signal is
A global reset signal, which is controlled by the microcontroller 100 (including the microcontroller 100), such as consumer electronics, communications, computer and automation equipment, and medical and industrial equipment; Reset all circuits in any device that requires.

The RESET_OUT_N signal is the reset-in input pin 1 of the microcontroller 100
It is also fed back to 05. If no reset circuit 145 is present, the microcontroller is locked into the reset state. That is, when the RESET_OUT_N signal is supplied to the reset-in input pin 105 from the reset-out output pin 110 of the microcontroller, a second RESET_OUT_N signal is generated, which is again supplied to the reset-in input pin 105, and the third RESET_OUT_N signal is generated. Is done.
Thus, the generation of the RESET_OUT_N signal is repeated, and the microcontroller 100
Are permanently latched in the reset state. Reset circuit 145 prevents microcontroller 100 from being locked up in a reset state.

FIG. 2 shows the reset circuit 145 in more detail. As shown in FIG. 2, the reset circuit or device 145 includes a counter 150. This counter 15
For 0, in one embodiment, an n-bit down counter with n = 6 is used. The 6-bit down counter 150 has six inputs and six outputs. The six outputs are provided to an OR gate 155, which in this case has zero-n
It outputs a count start (COUNT_ENA) signal, also called a signal. The COUNT_ENA signal goes low whenever the counter 150 counts down to zero. COUN
The T_ENA signal is supplied to the activation input of the counter 150 and the NOR gate 160. The duration of the COUNT_ENA signal, which is also associated with the duration of the RESET_OUT_N signal from the reset out output pin 110 of the microcontroller 100, depends on the value preloaded in the counter 150. Thus, this duration can be easily changed by pre-loading a predetermined different value into the counter 150, so that the duration of the RESET_OUT_N signal is such that all devices in the system are correctly reset. Thus, it can be easily changed to a desired value.

In addition to the COUNT_ENA signal, NOR gate 160 also receives a START signal as a second input. The output of NOR gate 160 is a global reset signal, ie, RE
Represents the SET_OUT_N signal (this is shown as the signal from the reset out output pin 110 in FIG. 1). If desired, a driver or delay element, eg, flip-flop, can be connected to the output of NOR gate 160 to provide a delay or additional drive to the RESET_OUT_N signal.

The START signal is supplied from the input device to the NOR gate 160. More specifically, the input device includes an input flip-flop 170, eg, a D flip-flop, that receives the RESET_N signal from clock generator 120 shown in FIG. The input flip-flop 170 delays the input RESET_N signal and provides a delayed RES
Outputs ET_N signal. This signal is inverted by the inverter 175. The input and output signals of the input flip-flop 170, that is, the RESET_N signal and the delayed and inverted RESET_N_D signal are supplied to an AND gate 180, which provides a START signal to the counter 150 and the NOR gate 160. .

The AND gate 180 has another input and receives a control signal that activates or disables the AND gate 180 depending on the level of the control signal. This additional signal is called the reset out start signal RST_OUT_EN and is provided by a start / disable device, also called a control device. In one embodiment, the control device comprises a flip-flop 185, which comprises a D flip-flop with a clear input C. The D input of the control flip-flop 185 receives the SWD (software data write) signal from the central processing unit (CPU) 135 shown in FIG. 1, and the flip-flop clear input C inhibits the reception of an external reset signal. Receive the signal CG_EXTRST_N. The SWD signal activates the control flip-flop 185 and outputs a high logic level, ie, a high logic level RS.
The T_OUT_EN signal is supplied to the AND gate 180. On the other hand, the inhibit signal CG_EXTRST_N disables the control flip-flop 185 and provides a low logic level RST_OUT_EN signal.

The CG_EXTRST_N signal is a signal that mirrors (follows) the RESET_N signal supplied to the input flip-flop 170. Thus, the CG_EXTRST_N signal is
It has the same duration as the signal and occurs simultaneously. However, the RESET_N signal is generated by the clock generation logic 120 shown in FIG.
The CG_EXTRST_N signal, in contrast to a reset signal received from a source external to microprocessor 100, is provided whether received from an external source at 00 or from an internal source. High level only when an external reset signal is received at the reset-in input pin 105 of the microcontroller. That is, the CG_EXTRST_N signal is provided only when an external reset signal is received at pin 105 using circuitry well known in the art and provided to clock generator 120.

Next, the operation of the reset device 145 will be described with reference to FIGS. FIG. 3 illustrates a timing diagram of various signals of the reset device 145. A clock signal 210 is provided to the clock inputs of the two flip-flops 170, 185. The RESET_N signal 220 provided to the input flip-flop 170 is
Regardless of whether a reset signal generated internally by the internal hardware logic 125 of the microcontroller 100 (FIG. 1) or an external reset signal is received at the reset-in input pin 105 of the microcontroller 100, The RESET_N signal 220 is a pulse that goes low,
Reset all logic in 0.

FIG. 3 also shows the output of the input flip-flop 170, the delayed reset signal RESET_N_D signal 230. This signal is the input flip-flop 1
It is obtained by delaying the RESET_N signal 220 by 70. By inverting the delayed reset signal RESET_N_D signal 230 by the inverter 175, a delayed and inverted RESET_D signal 240 is obtained. Delayed and inverted RESET
By performing an AND operation on the _D signal 240 and the RESET_N signal 220, the START pulse 25
0 is formed. The START pulse has a one clock width pulse period between the rising edge of the RESET_N signal 220 and the falling edge of the delayed and inverted RESET_D signal 240. START pulse 250 is used to preload down counter 150 and to set output flip-flop 165.

In response to the START pulse 250, the counter 150 of the reset device 145 is loaded with a predetermined value. In one embodiment, the counter has a hexadecimal (
The value 3F in H) is loaded. The predetermined count value 3F _H 260, after one clock from the end of the reset pulse generated internally, i.e., after one clock of the RESET_N signal 220, i.e., is loaded immediately after the START signal 250. As explained below, if the reset input is external, the AND gate 180 is disabled, no START pulse is generated, and thus the count 150 is not loaded.

When loaded with a predetermined value, counter 150 counts down to zero,
Stop. This counting period determines the duration of the COUNT_ENA signal 270, ie, the pulse width, and thus the duration of the RESET_OUT_N signal 280 provided by the output flip-flop 165 (NOR gate 160). This is done by feeding the six outputs of counter 150 to OR gate 155, which outputs a zero-n, COUNT_ENA signal 270 when these six gate inputs are all low. Achieved.

The output flip-flop 165 is set when the counter 150 is first loaded, ie, when the START signal 250 goes high, and when the counter 150 reaches zero, ie, when the COUNT_ENA signal goes low. Cleared when the value is reached.
This is because the START signal 250 and the COUNT_ENA signal 270 in FIG. 2 and FIG.
When provided to OR gate 165 (160), a RESET_OUT_N pulse 280 is shown as being generated.

More specifically, the rising edge of the START pulse 250 causes the counter 1
The loading of 50 and this countdown are started. The COUNT_ENA signal 270 is
The value is high during the countdown period 260, and becomes low when the countdown reaches zero and ends. The output of the NOR gate 160, that is, RESET_OUT_
N signal 280 has two inputs (ie, START signal 250 and COUNT_ENA signal 270).
When either one of them becomes high, it becomes low. As shown in FIG. 3, RESET_OUT_N
Signal 280 goes low due to the rising edge of START pulse 250 and
It goes high by the falling edge of the NT_ENA signal 270.

The AND gate 180 that outputs the START pulse 250 is activated by an activation signal RST_OUT_EN from the control flip-flop 185. In one embodiment, the control flip-flop 185 is a software-writeable, special-function register.
flip-flop). The control flip-flop 185 provides a logic 0 output, i.e., "CGS_EXTRST_N" signal generated when an external reset signal is received.
Cleared to the "disabled" state.The CG_EXTRST_N signal thus inhibits generation of START signal 250.

This mechanism prevents the START pulse 250, and thus the RESET_OUT_N pulse 280, from being generated in response to an external reset signal (these external reset signals include a RESET_OUT_N pulse 280 that causes the microcontroller 100 to reset out of the microcontroller 100). An external reset signal generated when the output pin 110 is fed back to the reset input pin 105 (FIG. 1) is also included.) That is, the reset device 145 discriminates between an externally applied reset signal and an internally generated reset signal, and is disabled in the case of an external reset signal. Reset device 1
45 prevents the microcontroller 100 from being permanently latched up even when the RESET_OUT_N signal is fed back from the microcontroller's reset out output pin 110 to the microcontroller's reset in input pin 105.

After the control flip-flop 185 is disabled by the external reset signal and its output (ie, RST_OUT_EN signal) is cleared to zero, the software
By supplying a high value SWD (Software Data Write) signal from 135 (FIG. 1) to the D input of the control flip-flop 185, a dedicated function register flip-flop writable by software is set or activated. As a result of this activation, AND gate 180 generates a START pulse 250 and OR gate 1
60 generates a RESET_OUT_N signal. Of course, in applications where it is not required to generate the reset signal again after the generation of the external reset signal, the control flip-flop 185 can be left disabled. Thus, in this mechanism,
The user may disable all reset-out functions under software control, if not necessary, i.e. by not restarting the control flip-flop 185 disabled by the CG_EXTRST_N inhibit signal. Can also be disabled.

Next, an operation when an internal reset state occurs following a typical initial external reset signal will be described. When power is first applied, or when an initial external reset signal is received at the reset-in input pin 105 of the microcontroller 100, the control flip-flop 185 is disabled due to the presence of the CG_EXTRST_N signal and The / disable flip-flop output RST_OUT_EN is cleared to a low logic level. Therefore, the input flip-flop 170 and the inverter 175
, And the one-shot circuit constituted by the AND gate 180 does not generate a START pulse. Thus, without loading the counter 150 or counting down to zero, the COUNT_ENA signal 270 is not generated, and R
Thus, normal operation is started without the ESET_OUT_N signal 280 being generated.

Following the initial external reset signal, the SW from the central processing unit (CPU) 135
D (software data write) signal causes control flip-flop 185
Is started. Subsequently, when the CG_EXTRST_N signal is not present, that is, when the CG_EXTRST_N signal is low and an internal reset signal is generated, a START pulse 250 is generated, and the RESET_OUT_N signal is output from the reset out output pin 110 of the microcontroller 100.
The N signal 280 is output, and all circuits are reset, including the reset of the microcontroller 100 itself. That is, a global reset is performed. The microcontroller 100 is reset because the RESET_OUT_N signal 280 is fed back to the reset-in input pin 105 of the microcontroller 100. Upon receipt of the RESET_OUT_N signal 280 fed back to the microcontroller's reset-in input pin 105, a CG_EXTRST_N signal is generated, which causes another RESET_OUT_N signal 280 to be output from the microcontroller's reset-out output pin 110. Is suppressed.

Thus, when the reset-out output pin 110 of the microcontroller is connected to its reset-in input pin 105, the internal reset signal will reset the microcontroller 100 twice. The first time is when the internal reset signal itself is generated, and as a result, the RESET_OUT_N signal 280 is output. The second time is when the RESET_OUT_N signal 280 is fed back to the reset-in input pin 105 of the microcontroller. However, even if the microcontroller is reset twice, the circuit outside the microcontroller is reset only once when the RESET_OUT_N signal 280 is generated,
There is no particular problem.

It should also be noted that there is no particular problem if the counter 150 is started from a non-zero state when power is first applied. If, at power-up, the counter 150 is in a counting state, rather than a zero state, the generated COUNT_ENA signal 270 will have a shorter duration than the typical duration, i.e., a pulse width, and as a result Generated RESET_OUT_N signal 280
Is also shorter than the duration of the external reset signal generated when power is applied. This short RESET_OUT_N signal 280 terminates before the external reset signal generated when power is first applied is terminated. However, even if a short internal reset signal is generated when the power is turned on and the counter is not in the zero state, and thus a short RESET_OUT_N signal 280 is generated, this does not mean that the microcontroller is reset by turning on the power. This short RESET_OUT_N signal 280 does not prevent devices controlled by the microcontroller 100 from being properly reset because they are masked by the external reset signal received on the input pin 105.

Although the present invention has been described above with particular reference to preferred embodiments of the invention, those skilled in the art will recognize that the above-described embodiments do not depart from the spirit and scope of the invention.
Various changes may be made in form or detail, and the invention is limited only by the claims.

[Brief description of the drawings]

FIG. 1 shows a microcontroller according to the present invention.

FIG. 2 shows a reset device according to the invention.

FIG. 3 shows a timing chart of signals of a reset device according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 microcontroller 105 reset-in input pin 110 reset-out output pin 115 external reset signal generator 120 clock generation logic 125 internal hardware logic 130 monitoring timer 135 central processing unit (CPU) 140 OR gate 145 reset device (circuit) 150 counter 155 OR gate 160 NOR gate 175 Inverter 180 AND gate 210 Clock signal 220 RESET_N signal 230 Delayed reset signal RESET_N_D 240 Delayed and inverted RESET_D signal 250 START signal (pulse) 260 Predetermined count value 270 COUNT_ENA signal 280 RESET_OUT_N signal

──────────────────────────────────────────────────の Continued on the front page (71) Applicant Groenewoodseweg 1, 5621 BA Eindhoven, The Netherlands (72) Inventors William, J. Srikovkov 5656, Aaar, Eindhoven, Prof. Netherlands. Holstrahn, 6F term (reference) 5B054 AA11 BB01 BB05 CC01 5B062 HH08 5J055 AX00 BX41 CX27 EZ25 EZ28 EZ31 EZ34 EZ39 EZ50 FX01 FX18 GX01 GX02 GX04

Claims (10)

[Claims] A reset-in pin and a reset-out pin; a counter for outputting a start signal after counting a predetermined number of counts; a counter coupled to the reset-in pin, in response to a first input reset signal from the reset-in pin An input circuit that supplies a start signal for instructing the counting to the counter; and an output circuit that outputs an output reset signal to the reset out pin in response to the start signal and the start signal. A data processing integrated circuit, wherein the start signal is suppressed by a control signal. 2. The data processing integrated circuit according to claim 1, wherein the first input reset signal is generated inside the data processing integrated circuit. 3. A control circuit for supplying the control signal and activating the start signal when a second input reset signal received at an input pin of the data processing integrated circuit is absent. The data processing integrated circuit according to claim 1. 4. The input circuit of claim 1, wherein the input circuit includes an AND gate receiving the first input reset signal, a delayed and inverted output of the input circuit, and the control signal. A data processing integrated circuit as described. 5. The data processing integrated circuit according to claim 1, wherein the input circuit includes a delay circuit that delays the first input reset signal and supplies a delayed input reset signal. . 6. The data of claim 1, wherein said input circuit comprises an AND gate receiving said first input reset signal and an inverted version of said delayed input reset signal. Processing integrated circuit. 7. The input circuit includes a flip-flop for receiving the first input reset signal, the first input reset signal, a delayed and inverted output of the flip-flop, and the control signal. 2. The data processing integrated circuit according to claim 1, further comprising: an AND gate for receiving the data. 8. The reset device according to claim 1, further comprising a NOR gate receiving the start signal and the start signal and supplying the output reset signal. 9. The data processing integrated circuit according to claim 1, wherein the start signal is disabled when an external reset signal is received from a device external to the data processing integrated circuit. . 10. A counter for outputting a start signal after counting a predetermined count number, an input circuit for supplying a start signal for instructing the counter to the counter in response to an input reset signal, the start signal And an output circuit that outputs an output reset signal in response to the start signal, wherein the start signal is suppressed by a control signal.