KR20040054286A - Electromagnetic wave shielding structure of bga package - Google Patents
Electromagnetic wave shielding structure of bga package Download PDFInfo
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- KR20040054286A KR20040054286A KR1020020081307A KR20020081307A KR20040054286A KR 20040054286 A KR20040054286 A KR 20040054286A KR 1020020081307 A KR1020020081307 A KR 1020020081307A KR 20020081307 A KR20020081307 A KR 20020081307A KR 20040054286 A KR20040054286 A KR 20040054286A
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- circuit board
- semiconductor chip
- package
- metal plate
- shielding structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
본 발명은 비지에이 패키지 패키지의 전자파 차폐구조에 관한 것으로서, 보다 상세하게는 비지에이 패키지의 몰딩과 방열목적으로 설치된 금속판에 전자파 쉴드가 형성되도록 하여 전자파의 방사를 차단하는 비지에이 패키지 패키지의 전자파 차폐구조에 관한 것이다.The present invention relates to an electromagnetic shielding structure of a BG package package, and more particularly, to shield electromagnetic radiation by forming an electromagnetic shield on a metal plate installed for molding and heat dissipation of the BGP package. It's about structure.
최근 전자제품의 소형화, 고집적화에 됨에 따라 인쇄회로기판에 실장되는 전자부품들이 패키지(Package) 형태로 개발되고 있으며, 그 중 많이 사용되는 패키지 형태의 전자부품은 비지에이(BGA;Ball Grid Array) 패키지, 큐에프피(QFP;Quad Flat Package) 등이 사용되고 있다.With the recent miniaturization and high integration of electronic products, electronic components mounted on printed circuit boards are being developed in the form of packages. Among them, the electronic components in the form of packages are BGA (Ball Grid Array) packages. And QF (Quad Flat Package) are used.
도 1은 종래 기술에 의한 비지에이 패키지가 도시된 저면사시도이고, 도 2는 종래 기술에 의한 비지에이 패키지가 도시된 단면도이다.1 is a bottom perspective view of a BG package according to the prior art, and FIG. 2 is a cross-sectional view of a BG package according to the prior art.
종래 기술에 의한 비지에이 패키지는 도 1 및 도 2에 도시된 바와 같이, 내부배선이 형성된 회로기판(12)의 상측에는 상기 내부회로에서 발생된 열을 배출시킬 수 있도록 내부금속판(16)이 부착되고, 상기 내부배선의 일측에는 전극(11)이 형성되어 주회로기판(2)과 전기적으로 접속될 수 있도록 납볼(13)이 형성된다.As shown in FIG. 1 and FIG. 2, the BG package according to the related art has an inner metal plate 16 attached to an upper side of the circuit board 12 on which the inner wiring is formed so as to discharge heat generated in the inner circuit. The lead ball 13 is formed on one side of the internal wiring so that the electrode 11 is formed to be electrically connected to the main circuit board 2.
또한, 상기 회로기판(12)의 일측에는 소정공간의 함입부(12a)가 형성되어 반도체 칩(20)이 장착되도록 구성되는데, 상기 함입부(12a)의 주변부에는 전극패드(14)가 형성되어 상기 반도체 칩(20)과 전기적으로 연결되도록 상기 반도체 칩(20)과 연결된 와이어(22)가 본딩된다.In addition, a recess 12a of a predetermined space is formed at one side of the circuit board 12 so that the semiconductor chip 20 is mounted. An electrode pad 14 is formed at the periphery of the recess 12a. The wire 22 connected to the semiconductor chip 20 is bonded to be electrically connected to the semiconductor chip 20.
한편, 상기 비지에이 패키지(10)는 상기 회로기판(12) 및 상기 반도체 칩(20)과 연결된 와이어(22)의 본딩이 보호되도록 상기 반도체 칩(20) 및 와이어(22)를 감싸는 몰딩(25)이 형성된다.On the other hand, the BG package 10 is a molding 25 surrounding the semiconductor chip 20 and the wire 22 so that the bonding of the circuit board 12 and the wire 22 connected to the semiconductor chip 20 is protected. ) Is formed.
그리고, 상기 반도체 칩(20)의 상단에는 상기 반도체 칩(20)에서 발생된 열을 방출 시킬 수 있도록 외부금속판(18)이 부착된다. 이때, 상기 내부금속판(16)과 외부금속판(18) 사이에는 접착을 이루는 동시에 상기 내, 외부금속판(18)을 절연시키는 레진층(17)이 형성된다.In addition, an external metal plate 18 is attached to an upper end of the semiconductor chip 20 to release heat generated from the semiconductor chip 20. In this case, a resin layer 17 is formed between the inner metal plate 16 and the outer metal plate 18 to insulate the inner and outer metal plates 18.
상기와 같이 구성된 비지에이 패키지(10)는 주회로기판(2)에 실장된 후 상기 비지에이 패키지(10)에서 발생되는 열이 방열되도록 다수의 금속편(32)으로 이루어진 방열판(30)이 양면접착제(34)에 의해 상기 외부금속판(18)의 상측에 부착된다.In the BG package 10 configured as described above, the heat dissipation plate 30 made of a plurality of metal pieces 32 is formed on the main circuit board 2 so that heat generated from the BG package 10 is radiated. And attached to the upper side of the outer metal plate 18 by means of (34).
한편, 상기와 같이 구성된 비지에이 패키지(10)는 고밀도, 고집적화됨에 따라 고속동작을 위해 고클럭으로 작동되는데, 이로 말미암아 상기 비지에이 패키지(10)에는 고온으로 발열되고, 이때 발생된 열은 외측에 부착된 방열판(30)을통해 대기로 방사되며 냉각된다.On the other hand, the BG package 10 configured as described above is operated at a high clock for high-speed operation as it is high density and high density, whereby the BG package 10 is heated to a high temperature, and the generated heat is attached to the outside. It is radiated to the atmosphere through the heat sink 30 and cooled.
그러나, 종래 기술에 의한 비지에이 패키지(10)는 상기 회로기판(12) 또는 반도체 칩(20)이 고속의 클럭으로 동작함에 따라 고주파 노이즈가 발생되는데, 방열을 위해 부착된 상기 내, 외부금속판(16)(18)과 상기 방열판(30)이 전기적으로 접지되지 않아 안테나 역할을 하게되므로 상기 회로기판(12) 또는 반도체 칩(20)에서 발생된 고주파 노이즈가 상기 내, 외부금속판(16)(18)과 상기 방열판(30)에서 커플링되며 전자파를 발생시키는 원인이 되고 있다. 상기한 전자파는 다른 전자부품의 신호에 노이즈를 발생시켜 성능저하 및 오작동의 원인이 되고 있으며, 다른 전자제품에도 영향을 미처 오작동이 발생되는 문제점이 있으며, 상기 전자파는 전자제품은 물론 인체에 방사될 경우 심각한 문제를 야기하므로 전자파 장애(EMI ; ElectroMagnetic Interface) 규격을 개정하여 전자파 발생을 제한하는바, 상기 전자파 장애 규격을 만족하기 위해 전자파 쉴딩을 실시해야 하므로 비용상승의 원인이 되고 있다.However, the high-frequency noise is generated in the BG package 10 according to the prior art as the circuit board 12 or the semiconductor chip 20 operates at a high speed clock. 16) 18 and the heat sink 30 are not electrically grounded to act as antennas, so that high-frequency noise generated from the circuit board 12 or the semiconductor chip 20 is reduced by the inner and outer metal plates 16 and 18. ) Is coupled to the heat sink 30 and causes electromagnetic waves. The electromagnetic waves cause noise on signals of other electronic components, causing performance degradation and malfunctions, and affecting other electronic products, causing malfunctions. The electromagnetic waves may radiate to electronic products as well as the human body. In this case, since it causes a serious problem, the electromagnetic interference (EMI) standard is modified to limit the generation of electromagnetic waves. Therefore, electromagnetic shielding must be performed to satisfy the electromagnetic interference standards, thereby causing a cost increase.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위하여 안출된 것으로서, 전기적으로 절연된 내, 외부금속판을 회로기판에 접지시켜 자체 쉴딩효과를 얻는 동시에 방열판이 전기적으로 접지될 수 있도록 도전성 시트를 이용하여 부착시킴으로서 전자파의 방사가 차단되는 비지에이 패키지의 전자파 차폐구조를 제공하는데그 목적이 있다.The present invention has been made to solve the above problems of the prior art, by using a conductive sheet so that the heat sink is electrically grounded while at the same time to achieve the self-shielding effect by grounding the electrically insulated inner and outer metal plate on the circuit board. The purpose of the present invention is to provide an electromagnetic shielding structure of a package in which electromagnetic radiation is blocked by attaching.
도 1은 종래 기술에 의한 비지에이 패키지가 도시된 저면사시도,1 is a bottom perspective view showing a BG package according to the prior art,
도 2는 종래 기술에 의한 비지에이 패키지가 도시된 단면도,Figure 2 is a cross-sectional view showing a busy package according to the prior art,
도 3은 본 발명에 의한 비지에이 패키지가 분해되어 도시된 저면사시도,Figure 3 is a bottom perspective view showing an exploded package BG according to the present invention,
도 4는 본 발명에 의한 비지에이 패키지의 전자파 차폐구조가 도시된 단면도,4 is a cross-sectional view showing an electromagnetic shielding structure of a BG package according to the present invention;
도 5는 본 발명에 의한 방열판이 부착된 비지에이 패키지의 전자파 차폐구조가 도시된 단면도이다.5 is a cross-sectional view showing the electromagnetic shielding structure of the BGA package with a heat sink according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
42 : 주회로기판 50 : 비지에이 패키지42: main circuit board 50: Vijay package
52 : 전극 52 : 회로기판52: electrode 52: circuit board
52a : 함입부 52b : 홀52a: recess 52b: hole
53 : 납볼 56 : 내부금속판53: lead ball 56: inner metal plate
57 : 레진층 57a : 개구부57 resin layer 57a
58 : 외부금속판 60 : 반도체 칩58: outer metal plate 60: semiconductor chip
62 : 와이어 65 : 몰딩62: wire 65: molding
70 : 접지봉 72 : 납봉70: ground rod 72: lead rod
74 : 더미 납볼74: Dummy Lead Ball
상기한 과제를 실현하기 위한 본 발명에 의한 비지에이 패키지의 전자파 차폐구조는 반도체 칩과, 상기 반도체 칩이 실장되어 와이어로 연결되도록 내부배선이 형성된 회로기판과, 상기 회로기판 또는 상기 반도체 칩에서 발생된 열이 방열되도록 설치된 금속판과, 상기 회로기판의 하측에 배치되어 상기 회로기판이 실장되는 주회로기판과, 상기 회로기판 및 상기 내, 외부금속판과 연결되고 상기 주회로기판과 접지되어 상기 내부배선 또는 반도체 칩에서 발생된 전자파가 방출되지 않도록 전자파 쉴드를 형성시키는 접지봉을 포함하여 구성된다.The electromagnetic shielding structure of the BG package according to the present invention for realizing the above object is generated from a semiconductor chip, a circuit board having internal wiring formed so that the semiconductor chip is mounted and connected to a wire, and the circuit board or the semiconductor chip. A metal plate installed to dissipate the heat, and a main circuit board disposed below the circuit board, on which the circuit board is mounted, and connected to the circuit board and the inner and outer metal plates and grounded to the main circuit board. Or a ground rod for forming an electromagnetic shield so that electromagnetic waves generated from the semiconductor chip are not emitted.
이하, 본 발명의 실시 예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 의한 비지에이 패키지가 분해되어 도시된 저면사시도이고, 도 4는 본 발명에 의한 비지에이 패키지의 전자파 차폐구조가 도시된 단면도이다.Figure 3 is a bottom perspective view showing the decomposition of the BG package according to the present invention, Figure 4 is a cross-sectional view showing the electromagnetic shielding structure of the BG package according to the present invention.
본 발명에 의한 비지에이 패키지의 전자파 차폐구조는 도 3에 도시된 바와 같이, 미세패턴으로 이루어진 반도체 칩(60)과, 일측에 함입부(52a)가 형성되어 상기 반도체 칩(60)이 실장되고 상기 반도체 칩(60)의 미세패턴과 와이어(62)로 연결되도록 내부배선이 형성된 회로기판(52)과, 상기 회로기판(52)의 상측에 부착되어 상기 내부배선에서 발생된 열을 방열시키는 내부금속판(56)과, 상기 내부금속판(56)과 소정거리 이격되고 상기 반도체 칩(60)의 상단이 밀착되어 상기반도체 칩(60)에서 발생된 열을 방열시키는 외부금속판(58)과, 상기 내부금속판(56)과 외부금속판(58) 사이에 충진되어 상기 외부금속판(58)과 내부금속판(56)을 절연시키는 레진층(57)과, 상기 회로기판(52)의 하측에 배치되어 상기 내부배선과 연결되도록 상기 회로기판(52)의 전극(51)에 형성된 납볼(53)이 실장되는 주회로기판(42)과, 상기 회로기판(52) 및 상기 금속판과 연결되고 상기 주회로기판(42)과 접지되어 상기 내부배선 또는 반도체 칩(60)에서 발생된 전자파가 방출되지 않도록 전자파 쉴드를 형성시키는 접지봉(70)을 포함하여 구성된다.As shown in FIG. 3, the electromagnetic shielding structure of the BG package according to the present invention includes a semiconductor chip 60 having a fine pattern and an indentation 52a formed at one side thereof to mount the semiconductor chip 60. A circuit board 52 having an internal wiring formed therein so as to be connected to the fine pattern of the semiconductor chip 60 by a wire 62, and an inside which is attached to an upper side of the circuit board 52 to dissipate heat generated from the internal wiring. A metal plate 56 and an outer metal plate 58 spaced apart from the inner metal plate 56 by a predetermined distance and in close contact with an upper end of the semiconductor chip 60 to dissipate heat generated from the semiconductor chip 60; A resin layer 57 filled between the metal plate 56 and the outer metal plate 58 to insulate the outer metal plate 58 and the inner metal plate 56, and disposed below the circuit board 52, and disposed on the inner wiring line. Lead balls formed on the electrodes 51 of the circuit board 52 so as to be connected to the The main circuit board 42 on which the 53 is mounted, the circuit board 52 and the metal plate are connected and grounded with the main circuit board 42 to generate electromagnetic waves generated in the internal wiring or the semiconductor chip 60. It is configured to include a ground rod 70 to form an electromagnetic shield so as not to be emitted.
이를 위해, 상기 내부금속판(56) 및 회로기판(52)의 일측에는 관통형성된 홀(52b)이 형성되고, 상기 접지봉(70)은 상기 홀(52b)에 채워져 상기 내, 외부금속판(56)(58) 및 회로기판(52)을 전기적으로 연결시키는 납봉(72)과, 상기 납봉(72)의 단부에 형성되어 상기 주회로기판(42)과 접지되는 더미 납볼(74)을 포함하여 구성된다.To this end, through-holes 52b formed in one side of the inner metal plate 56 and the circuit board 52 are formed, and the ground rod 70 is filled in the hole 52b so that the inner and outer metal plates 56 ( 58 and a lead rod 72 electrically connecting the circuit board 52 and a dummy lead ball 74 formed at an end of the lead rod 72 and grounded with the main circuit board 42.
더불어, 상기 레진층(57)은 상기 납봉(72)이 관통되는 부위에 레진층(57)이 형성되지 않은 개구부(57a)가 형성되어 상기 납봉(72) 형성시 상기 내부금속판(56) 및 외부금속판(58) 사이에 납 페이스트가 침투되어 응고됨으로서 접촉면적이 증가되도록 이루어진다.In addition, the resin layer 57 has an opening 57a in which the resin layer 57 is not formed at a portion through which the lead rod 72 penetrates, so that the inner metal plate 56 and the outside when the lead rod 72 is formed. Lead paste penetrates and solidifies between the metal plates 58 so that the contact area is increased.
또한, 상기 비지에이 패키지(50)는 상기 회로기판(52) 및 상기 반도체 칩(60)과 연결된 와이어(62)의 본딩이 보호되도록 상기 반도체 칩(60) 및 와이어(62)를 감싸는 몰딩(65)이 형성된다.In addition, the busy package 50 may include a molding 65 surrounding the semiconductor chip 60 and the wire 62 so that bonding of the circuit board 52 and the wire 62 connected to the semiconductor chip 60 is protected. ) Is formed.
상기와 같이 구성된 비지에이 패키지(50)는 하측에 형성된 납볼(53)을 통해주회로기판(42)과 전기적으로 연결되어 작동되는데, 이때, 상기 반도체 칩(60) 또는 내부배선에 고주파 노이즈에 의한 전자파가 발생되나, 상기 내, 외부금속판(56)(58) 및 회로기판(52)이 상기 접지봉(70)에 의해 상기 주회로기판(42)에 접지되어 전자파 쉴드를 형성시킴으로 상기 전자파가 외부로 방출되지 않도록 차폐된다.The BG 50 configured as described above is electrically connected to the main circuit board 42 through a lead ball 53 formed at a lower side thereof. In this case, the semiconductor chip 60 or the internal wiring may be caused by high frequency noise. Electromagnetic waves are generated, but the inner and outer metal plates 56 and 58 and the circuit board 52 are grounded to the main circuit board 42 by the ground rod 70 to form an electromagnetic shield so that the electromagnetic waves are directed to the outside. It is shielded from release.
도 5는 본 발명에 의한 방열판이 부착된 비지에이 패키지의 전자파 차폐구조가 도시된 단면도이다. 여기서 앞서 도시된 도면에서와 동일한 참조부호는 동일한 부재를 가리킨다.5 is a cross-sectional view showing the electromagnetic shielding structure of the BGA package with a heat sink according to the present invention. Here, the same reference numerals as in the above-described drawings indicate the same members.
또한, 상기 비지에이 패키지(50)는 반도체 칩(60)이 처리속도가 증가됨에 따라 더욱 많은 열을 방출시켜야 되는데, 이를 위해 상기 비지에이 패키지(50)는 도 5에 도시된 바와 같이, 상기 외부금속판(58)의 외측에는 방열량이 증가되도록 다수의 금속편(82)으로 이루어진 방열판(80)이 더 배치되어 도전성 시트(84)에 의해 부착된다.In addition, the BI package 50 has to emit more heat as the semiconductor chip 60 increases in processing speed. For this purpose, the BI package 50 has an external structure as shown in FIG. 5. Outside the metal plate 58, a heat dissipation plate 80 made of a plurality of metal pieces 82 is further disposed so as to increase the amount of heat dissipation, and is attached by the conductive sheet 84.
즉, 상기 방열판(70)은 상기 외부금속판(58)과 밀착되어 상기 반도체 칩(60) 및 회로기판(52)에서 발생된 열을 외부로 방출시키는 동시에 도전성 시트(84)에 의해 상기 접지봉(70)과 전기적으로 연결되어 상기 주회로기판(42)에 접지됨으로서 전자파 쉴드가 형성되어 상기 반도체 칩(60) 또는 내부배선에서 발생된 전자파가 방출되지 못하고 상기 주회로기판(42)에 흡수된다.That is, the heat sink 70 is in close contact with the external metal plate 58 to release heat generated from the semiconductor chip 60 and the circuit board 52 to the outside and at the same time, the ground rod 70 by the conductive sheet 84. The electromagnetic shield is formed by being electrically connected to the main circuit board 42 and grounded to the main circuit board 42 so that electromagnetic waves generated from the semiconductor chip 60 or the internal wiring cannot be emitted and are absorbed by the main circuit board 42.
이상과 같이 본 발명에 의한 비지에이 패키지의 전자파 차폐구조를 예시된도면을 참조로 설명하였으나, 본 명세서에 개시된 실시예와 도면에 의해 본 발명은 한정되지 않으며 그 발명의 기술사상 범위내에서 당업자에 의해 재질을 포함한 다양한 변형이 이루어질 수 있음은 물론이다.As described above, the electromagnetic shielding structure of the BG package according to the present invention has been described with reference to the illustrated drawings. However, the present invention is not limited by the embodiments and drawings disclosed herein, and the skilled person within the technical scope of the present invention. Of course, various modifications can be made, including materials.
따라서, 상기와 같이 구성되는 본 발명에 의한 비지에이 패키지의 전자파 차폐구조는 상기 회로기판 및 상기 내, 외부금속판과 연결되고 상기 주회로기판과 접지되어 상기 내부배선 또는 반도체 칩에서 발생된 전자파가 방출되지 않도록 전자파 쉴드를 형성시키는 접지봉을 포함하여 구성되어, 전자파의 방출로 인한 전자부품의 오작동이 현저히 감소됨은 물론 다른 전자제품에 발생되는 오작동이 발생되지 않고, 인체가 전자파에 노출됨으로 인해 발생되는 이상증상이 미연에 방지되는 효과가 있다.Therefore, the electromagnetic wave shielding structure of the BG package according to the present invention configured as described above is connected to the circuit board and the inner and outer metal plates and grounded with the main circuit board to emit electromagnetic waves generated from the internal wiring or the semiconductor chip. It is composed of a grounding rod to form an electromagnetic shield so as to prevent the malfunction of the electronic components due to the emission of electromagnetic waves, as well as the malfunction caused by the exposure of electromagnetic waves to the human body is not generated abnormally It is effective in preventing symptoms.
또한, 별도의 전자파 쉴드가 필요치 않으므로 재료비 및 공정 절감을 통한 생산비를 저감시킬 수 있으며, EMI 규격을 만족하게되어 소비자 신뢰도가 향상됨은 물론 외국의 전자파 규격을 만족할 수 있게되어 수출경쟁력을 높일 수 있는 이점이 있다.In addition, since there is no need for a separate electromagnetic shield, it is possible to reduce the production cost by reducing the material cost and process, and to meet the EMI standards to improve consumer reliability and to meet foreign electromagnetic standards, thereby improving export competitiveness. There is this.
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2002-0081307A KR100505241B1 (en) | 2002-12-18 | 2002-12-18 | electromagnetic wave shielding structure of BGA package |
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| KR10-2002-0081307A KR100505241B1 (en) | 2002-12-18 | 2002-12-18 | electromagnetic wave shielding structure of BGA package |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100716846B1 (en) * | 2006-01-31 | 2007-05-09 | 삼성전기주식회사 | Structure of package using metal core flexible painted circuit board |
| KR100734816B1 (en) * | 2003-01-30 | 2007-07-06 | 인터내셔널 비지네스 머신즈 코포레이션 | Optimized lid mounting for electronic device carriers |
| US8791554B2 (en) | 2011-07-18 | 2014-07-29 | Samsung Electronics Co., Ltd. | Substrates for semiconductor devices including internal shielding structures and semiconductor devices including the substrates |
| CN112490219A (en) * | 2020-11-27 | 2021-03-12 | 海宁利伊电子科技有限公司 | Radiation leakage resistant conformal shielding SIP packaging structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220000538A (en) | 2020-06-26 | 2022-01-04 | 삼성전자주식회사 | Semiconductor module |
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2002
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100734816B1 (en) * | 2003-01-30 | 2007-07-06 | 인터내셔널 비지네스 머신즈 코포레이션 | Optimized lid mounting for electronic device carriers |
| KR100716846B1 (en) * | 2006-01-31 | 2007-05-09 | 삼성전기주식회사 | Structure of package using metal core flexible painted circuit board |
| US8791554B2 (en) | 2011-07-18 | 2014-07-29 | Samsung Electronics Co., Ltd. | Substrates for semiconductor devices including internal shielding structures and semiconductor devices including the substrates |
| CN112490219A (en) * | 2020-11-27 | 2021-03-12 | 海宁利伊电子科技有限公司 | Radiation leakage resistant conformal shielding SIP packaging structure |
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