KR20040051179A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to conserve the thickness of a dielectric layer for the capacitor and increase the capacitance of the capacitor by using a nitride layer as the dielectric layer. CONSTITUTION: A trench is formed in a semiconductor substrate(200). A nitride layer(203') is deposited on the resultant structure as a dielectric layer for a capacitor. The nitride layer is selectively patterned. The first gate oxide layer(205) is formed on the resultant structure. The first gate oxide layer is selectively patterned. The second gate oxide layer(207) is formed on the resultant structure. A doped polysilicon layer for a gate electrode is deposited on the second gate oxide layer. The first, the second gate and a capacitor are formed by selectively patterning the doped polysilicon layer and the second gate oxide layer.

Description

METHODS FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE

The present invention relates to a method for manufacturing a trench type capacitor, and more particularly, to form a dielectric film of a capacitor using an ONO film having a higher dielectric constant than an oxide film and excellent leakage current and breakdown voltage characteristics, thereby reducing cell area. It relates to a method of manufacturing a capacitor of a device.

At present, as a semiconductor memory device, a DRAM device having a high capacity while freely inputting and outputting information is widely used. DRAM devices generally comprise a memory cell region for storing information data in the form of charge and a peripheral circuit region for inputting and outputting data. The unit cell of a DRAM device typically includes one transistor and one storage capacitor.

Such capacitors should be further reduced in size in order to meet the semiconductor devices requiring increased density, and should be manufactured with high storage capacity to improve the characteristics of the semiconductor devices. It is developing.

The capacitor has a general stack structure and a trench structure. In this case, the capacitance of the capacitor is proportional to its surface area, the dielectric constant of the dielectric film, and inversely proportional to the thickness of the dielectric film.

In addition, as the memory devices are highly integrated, the area occupied by the capacitor is reduced in two dimensions, while the capacitance required per cell is hardly changed.

Therefore, after forming a storage node pattern in order to secure the same capacitance in the stack structure, an undercut using the lower portion of the storage node as an electrode by removing a portion of an oxide layer under the storage node by wet etching after forming the storage node pattern. ) May be used.

Another capacitor fabrication method is to use trench techniques to maximize the area efficiency of memory cells.

1A to 1F are process drawings showing a capacitor manufacturing method of a semiconductor device according to the prior art.

First, referring to FIG. 1A, after forming a device isolation layer 101 for inter-device insulation through a conventional trench process, a well (not shown) is formed inside the semiconductor substrate 100 by performing a photolithography process and an implant process. Form. The first photoresist pattern 102 is formed to form a trench in the region where the capacitor is to be formed, and then a dry etching process is performed using the mask to form the trench.

After removing the first photoresist pattern 102 of the resultant trench, the first oxide layer 103 is formed to a thickness of 40 占 퐉 through an oxidation process to form a first gate. Subsequently, a second photoresist pattern 104 for patterning the first gate oxide layer 103 is formed.

Then, as shown in FIG. 1C, the first oxide layer 103 ′ is left only in the region where the first gate is to be formed through wet etching using the second photoresist pattern 104, and all other portions are removed.

Subsequently, as shown in FIG. 1D, the second oxide film 105 is formed with a target of 40 占 퐉 in thickness to form the second gate. At this time, an oxide film having a thickness of about 24 kV is formed on the first gate oxide film 103 ', and an oxide film of about 44 kV is grown in the second gate oxide film 105. Therefore, the first gate oxide film has a thickness of 64 kV and the oxide film having a thickness of 44 kW is formed as the dielectric film of the second gate oxide film and the capacitor.

Subsequently, a doped polysilicon film 106 for the floating gate is deposited and a third photoresist pattern 107 for patterning the gate and the capacitor is formed.

Referring to FIG. 1E using the third photoresist pattern 107, a dry etching process is performed to pattern the first gate G1, the second gate G2, and the trench capacitor TC.

In this case, in order to increase the capacitance of the capacitor, the thickness of the dielectric film should be reduced. Since the capacitor dielectric film is formed at the same time when the second gate oxide film 105 is formed, the thickness of the gate oxide film can only be reduced in order to reduce the thickness of the dielectric film. There is a problem.

Meanwhile, as shown in FIG. 1F, an inter-poly-oxide (IPO) is deposited and insulated from the interlayer insulating film 109 on the resultant gate and capacitor formed thereon, followed by a planarization process, and a photo and dry etching process. After forming the metal contact through the bit line 109 and the metal wiring process 110 to manufacture an MPDL cell.

However, such a conventional method of manufacturing a capacitor must reduce the thickness of the dielectric film in order to increase the capacity of the MOS capacitor which occupies most of the cell area. However, since the dielectric film is formed at the time of forming the second gate oxide film, when the thickness of the dielectric film is reduced, the thickness of the second oxide film is also reduced, resulting in deterioration of TDDB (Time Dependent Dielectric Breakdown) characteristics and an increase in the number of processes.

That is, when the thickness of the second gate oxide film formed to be thin is reduced, the characteristics of the transistor are simultaneously changed, which causes a problem in that the characteristics of the device are changed.

In order to solve the above problems, the present invention forms a dielectric film of a capacitor in an ONO structure using a nitride film having a higher dielectric constant than that of an oxide film, thereby securing a higher capacitance at the same area without reducing the thickness of the dielectric film. It is to provide a method of manufacturing a capacitor of a semiconductor device that can be reduced.

1A to 1F are process drawings showing a capacitor manufacturing method of a semiconductor device according to the prior art.

2A to 2H are process drawings showing a capacitor manufacturing method of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

200 semiconductor substrate 201 device isolation film

203 ': capacitor dielectric film 205: first gate oxide film

207: second gate oxide film 208: doped polysilicon film

The present invention for achieving the above object is a process of forming a trench for forming a trench capacitor on a substrate having a predetermined substructure and a natural oxide film, and then performing an implant process, and the natural oxide film inside the trench Depositing and patterning a nitride film with a capacitor dielectric film after the formation thereof, forming a first gate oxide film on the resultant, patterning the oxide film to remain only in a region where the first gate is to be formed, and forming the first gate oxide film Forming a second gate oxide film on the patterned resultant to form an oxynitride film on the nitride film, depositing a gate electrode material on the second gate oxide film, and then patterning the first and second gates and capacitors Causing a capacitor dielectric film of an ONO structure to be formed It relates to a method for manufacturing a capacitor of a semiconductor device.

As described above, according to the present invention, since the capacitor dielectric film is formed in an ONO structure using a nitride film having a higher dielectric constant than the oxide film, a higher capacitance can be secured in the same area without reducing the thickness of the dielectric film as compared with the conventional capacitor. The cell area can be reduced.

The implant process in the trench is performed to adjust the threshold voltage of the capacitor, and it is preferable to proceed with a tilt of 30 ° using boron ions so that dopants are uniformly injected into the bottom and side of the trench. .

After the first gate oxide layer patterning, a cleaning process is further performed. In the cleaning process, the cleaning process is preferably performed with an ammonia-based cleaning solution to make the silicon surface uniform.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2A to 2G are process drawings showing a capacitor manufacturing method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a device isolation layer 201 is formed through a conventional trench process to separate devices, and then a well (not shown) is formed by performing a photo / etch process and an implant process on the semiconductor substrate 200. do. The first photoresist pattern 202 is formed to form trenches in the region where the capacitor is to be formed.

Then, as shown in FIG. 2B, after forming the trench in the capacitor region through dry etching using the first photoresist pattern 202, an implant process is performed to adjust the threshold voltage of the capacitor and the first photo is formed. The resist pattern 202 is removed.

At this time, the implant process for adjusting the threshold voltage of the capacitor is preferably inclined by about 30 ° using boron ions, which is to ensure that the dopant is uniformly injected into the bottom and side of the trench capacitor.

A nitride film 203 is deposited to a thickness of 36 to 44 으로 with a capacitor dielectric film on the resultant product from which the first photoresist pattern 202 is removed. At this time, since the natural oxide film is already formed on the surface of the semiconductor substrate 200 to a thickness of 2 to 3 Å, it is used as the dielectric film of the ONO structure of the nitride film to be subsequently deposited and the oxide film formed thereon. Do not remove.

As shown in FIG. 2C, the result of the formation of the natural oxide film and the oxynitride film having the nitride film structure formed on the capacitor, leaving only the nitride film 203 ′ in the region where the capacitor is to be formed through the photolithography process, and the nitride film 203 in the other region. Remove it.

Then, referring to FIG. 2D, after forming the first gate oxide film 205 with a thickness of 40 μs as a target, the second photoresist pattern 206 to leave the first gate oxide film 205 only in the region where the first gate is to be formed. ).

As shown in FIG. 2E, the first gate oxide layer 205 is left only in the region where the first gate is to be formed through the wet etching process using the second photoresist pattern 206, and the first gate in the other region. All of the oxide film 205 is removed.

At this time, an oxide film having a predetermined thickness is formed on the surface of the nitride film, which is the capacitor dielectric film 203 '. Accordingly, a capacitor dielectric film having an ONO structure of an oxide film formed by natural oxidation, a nitride film as a capacitor dielectric film, and an oxide film formed on the nitride film during the first gate oxidation process is formed on the semiconductor substrate.

Subsequently, the surface of the semiconductor substrate of the first gate oxide film 205 is cleaned with an ammonia-based cleaning solution to make the silicon surface uniform, thereby improving GOI (Gate Oxide Integrity) characteristics.

At this time, the cleaning process uses a UD cleaning solution, it is preferable to use a U [NH ₄ OH + H ₂ O ₂ + H ₂ O] + D cleaning solution.

As shown in Fig. 2F, the second gate oxide film 207 is formed by subjecting the capacitor dielectric film having the ONO structure to a thickness of 40 kV by subjecting it to an oxidation process. At this time, the second gate oxide film is formed on the first gate oxide film 205 to a thickness of about 24 kW, and the second gate oxide film is formed to a thickness of 44 kW by a chemical oxide film formed by several previous thicknesses by a previous cleaning process. An oxynitride film is formed on the nitride film 203 'of the capacitor.

Therefore, the first gate oxide film 205 is formed at a thickness of 64 kV and the second gate oxide film 207 is formed at a thickness of 44 kV because the chemical oxide film is formed several times by the cleaning process before the second gate oxide film forming process. .

In this case, the gate oxide film is formed by a wet oxidation process at a temperature of 800 ° C. using H ₂ + O ₂ .

Subsequently, the doped polysilicon 208 is deposited to form a gate electrode, and then a third photoresist pattern 209 for patterning the gate and the capacitor is formed.

2G, after forming the first gate G1, the second gate G2, and the capacitor C through an etching process using the third photoresist pattern, as shown in FIG. 2H, After depositing and planarizing the inter-poly-oxide (IPO) with the interlayer insulating film 2109, a metal contact is formed through a photo and dry etching process, and then a bit line 211 and a metal wiring process 212 are performed to form an MPDL cell. To prepare.

As described above, the present invention forms a dielectric film in an ONO structure by using a nitride film having a high dielectric constant of 7.2 instead of an oxide film having a dielectric constant of 3.9, thereby reducing capacitance of the capacitor dielectric film by 70 to 80% in the same area without reducing the thickness of the capacitor dielectric film. An increase can be achieved.

As described above, in the present invention, by using a nitride film having a higher dielectric constant than an oxide film, ONO having excellent electrical characteristics can be formed as a capacitor dielectric film, thereby ensuring high correction capacity in the same area, thereby reducing chip cell area to produce chip ends. This has the advantage of reducing costs.

In addition, by increasing the capacitance per unit area can be applied to products or SoC devices that require a high capacitance of the capacitor has the advantage of maximizing productivity.

Claims (4)

Performing an implant process after performing a trench forming process for forming a trench capacitor on a substrate having a predetermined substructure and a natural oxide film; Depositing and patterning a nitride film with a capacitor dielectric film after allowing a native oxide film to be formed in the trench; Forming a first gate oxide film on the resultant and performing patterning by performing a photo-etching process so that the oxide film remains only in a region where the first gate is to be formed; Forming a second gate oxide layer on the resultant of patterning the first gate oxide layer to form an oxynitride layer on the nitride layer; Depositing a gate electrode material on the second gate oxide layer and then performing a photo and etching process to pattern the first and second gates and the capacitor to form a capacitor dielectric layer having an ONO structure A method for manufacturing a capacitor of a semiconductor device, comprising. The method of claim 1, wherein the implant process is performed by giving a tilt of 30 ° using boron ions to uniformly inject dopants into the bottom and side surfaces of the trench. The method of manufacturing a capacitor of a semiconductor device according to claim 1, further comprising a cleaning process after said first gate oxide film patterning. The method of claim 1, wherein the cleaning process is performed by cleaning with an ammonia-based cleaning solution to make the silicon surface uniform.