KR20040049874A - Flash memory and fabrication method thereof - Google Patents
Flash memory and fabrication method thereof Download PDFInfo
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- KR20040049874A KR20040049874A KR1020020076828A KR20020076828A KR20040049874A KR 20040049874 A KR20040049874 A KR 20040049874A KR 1020020076828 A KR1020020076828 A KR 1020020076828A KR 20020076828 A KR20020076828 A KR 20020076828A KR 20040049874 A KR20040049874 A KR 20040049874A
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 23
- 239000002356 single layer Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 3
- 239000002784 hot electron Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Description
본 발명은 플래쉬 메모리 및 그 제조방법에 관한 것으로, 더욱 상세하게는 소거 효율을 향상시킨 플래쉬 메모리 및 그 제조방법에 관한 것이다.The present invention relates to a flash memory and a method of manufacturing the same, and more particularly, to a flash memory and a method of manufacturing the same with improved erase efficiency.
일반적으로 플래쉬 메모리는 종래 이피롬(EPROM : erasable programmable read only memory)과 이이피롬(EEPROM : electrically erasable PROM)의 장점을 동시에 구현하고자 하는데서 출발한 것으로, 전기적으로 데이터의 프로그래밍과 소거가 가능하면서도 간단한 제조공정 및 소형화된 칩 사이즈 등의 면에서 낮은 제조단가를 지향한다.In general, the flash memory is started to realize the advantages of the conventional erasable programmable read only memory (EPROM) and the electrically erasable PROM (EEPROM) simultaneously. It aims at low manufacturing cost in terms of process and miniaturized chip size.
또한, 플래쉬 메모리는 전원이 끊겨도 데이터가 소멸되지 않는 비휘발성 반도체 메모리이지만 정보의 프로그래밍과 소거가 시스템 내에서 전기적으로 용이하게 이루어진다는 점에서 램(RAM : random access memory)의 성격을 가지므로, 메모리 카드나 휴대용 사무자동화 기기의 하드 디스크를 대체하는 기억 장치 등에 이용되고 있다.In addition, the flash memory is a nonvolatile semiconductor memory in which data is not destroyed even when the power supply is cut off. However, since the flash memory is electrically easy to program and erase information in the system, it is a random access memory (RAM). It is used for a memory device or a storage device replacing a hard disk of a portable office automation device.
이러한 플래쉬 메모리에서 데이터의 프로그래밍은 핫 일렉트론(hot electron)의 주입에 의해 이루어진다. 즉, 소스와 드레인 간에 걸리는 포텐셜 차이에 의해 채널 내에서 핫 일렉트론이 발생되면 그 중 게이트를 이루는 다결정 실리콘과 산화막 사이의 포텐셜 장벽인 3.1 eV 이상의 에너지를 얻은 일부 일렉트론이 콘트롤 게이트에 걸리는 높은 전기장에 의해 플로팅 게이트로 이동하여 저장된다.The programming of data in such flash memory is by injection of hot electrons. That is, when hot electrons are generated in the channel due to the potential difference between the source and the drain, some of the electrons having energy of 3.1 eV or more, which is a potential barrier between the polycrystalline silicon forming the gate and the oxide layer, are caused by the high electric field applied to the control gate. It is moved to the floating gate and stored.
따라서, 일반적인 모스소자에서는 핫 일렉트론이 소자의 열화 원인이 되기 때문에 가능한 억제시키는 방향으로 소자 설계가 이루어지나, 플래쉬 메모리에서는 이러한 핫 일렉트론을 생성시키는 방향으로 소자 설계가 이루어진다.Therefore, in a general MOS device, the device design is made in the direction of suppressing as much as possible because hot electrons cause the deterioration of the device. In the flash memory, the device design is made in the direction of generating such hot electrons.
그러면, 도 1을 참조하여 종래 플래쉬 메모리를 개략적으로 설명한다. 도 1은 종래 플래쉬 메모리의 구조가 도시된 단면도이다. 도 1에 도시된 바와 같이, 플래쉬 메모리에서 데이터의 프로그래밍은 전자가 반도체 기판(1)으로부터 터널 옥사이드(2)를 터널링하여 플로팅 게이트(3)로 이동함으로써 이루어지고, 데이터의 소거는 플로팅 게이트(3)에 저장되어 있던 전자가 로코스(LOCOS : local oxidation of silicon) 산화막(4)을 관통하여 콘트롤 게이트(5)로 이동함으로써 이루어진다.Next, a conventional flash memory will be described with reference to FIG. 1. 1 is a cross-sectional view showing the structure of a conventional flash memory. As shown in FIG. 1, programming of data in the flash memory is performed by electrons tunneling tunnel oxide 2 from the semiconductor substrate 1 to the floating gate 3, and erasing of data is performed by the floating gate 3. Is stored by passing through the LOCOS (local oxidation of silicon) oxide film 4 to the control gate 5.
이와 같이 종래 플래쉬 메모리에서는 소거 효율을 높이기 위해 플로팅 게이트(3) 위에 실리콘을 열산화하여 로코스 산화막(4)을 성장시켜 플로팅 게이트(3)의 가장자리를 뾰족하게 만들었다.As described above, in the conventional flash memory, silicon is thermally oxidized on the floating gate 3 to grow the LOCOS film 4 so as to sharpen the edge of the floating gate 3 in order to increase the erase efficiency.
그러나, 로코스 산화막(4)은 두께가 두꺼워 전자의 이동이 어렵기 때문에 소거 효율이 낮은 문제점이 있었다.However, the LOCOS oxide film 4 has a problem that the erase efficiency is low because the thickness of the LOCOS oxide film 4 is difficult to move the electrons.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 플래쉬 메모리의 소거 효율을 향상시키는 것이다.The present invention has been made to solve the above problems, and an object thereof is to improve the erase efficiency of the flash memory.
도 1은 종래 플래쉬 메모리의 구조가 도시된 단면도이고,1 is a cross-sectional view showing the structure of a conventional flash memory;
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 플래쉬 메모리의 제조방법이 도시된 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a flash memory according to an embodiment of the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 희생 산화막을 증착 및 선택적 식각하여 플로팅 게이트구를 형성하고 여기에 질화막을 증착 및 식각하여 사이드월을 형성한 후 다결정 실리콘층을 매립함으로써 가장자리가 뾰족한 형상의 플로팅 게이트를 형성하며, 플로팅 게이트 상에 원하는 얇은 두께의 절연막을 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, the sacrificial oxide film is deposited and selectively etched to form a floating gate sphere, and the nitride film is deposited and etched thereon to form a sidewall, and then the polycrystalline silicon layer is buried to have a sharp edge. A floating gate having a shape is formed, and an insulating film having a desired thin thickness is formed on the floating gate.
즉, 본 발명에 따른 플래쉬 메모리 제조 방법은, 반도체 기판 상에 산화막을 플로팅 게이트의 높이에 해당하는 두께로 형성한 후, 산화막을 선택적으로 식각하여 플로팅 게이트구를 형성하는 단계; 플로팅 게이트구를 통해 노출되는 반도체 기판에서 플로팅 게이트구의 양 측벽에 인접한 반도체 기판 및 양 측벽 상에 각각 사이드월을 형성하는 단계; 양 사이드월의 사이에서 플로팅 게이트구를 통해 노출되는 반도체 기판 상에 플로팅 게이트 산화막을 형성하는 단계; 플로팅 게이트 산화막 및 사이드월 상에 제1다결정 실리콘층을 형성하여 플로팅 게이트구를 매립하는 플로팅 게이트를 형성하는 단계; 산화막 및 사이드월을 제거하는 단계; 플로팅 게이트 및 반도체 기판 상에 플로팅 게이트를 감싸도록 100-1000Å의 두께로 절연막을 형성하고, 절연막 상에 제2다결정 실리콘층을 증착하여 콘트롤 게이트를 형성하는 단계; 콘트롤 게이트 및 절연막을 선택적으로 식각하는 단계를 포함하여 이루어진다.That is, the flash memory manufacturing method according to the present invention comprises the steps of forming an oxide film on the semiconductor substrate to a thickness corresponding to the height of the floating gate, and then selectively etching the oxide film to form a floating gate sphere; Forming sidewalls on the semiconductor substrate and both sidewalls adjacent to both sidewalls of the floating gate sphere in the semiconductor substrate exposed through the floating gate sphere; Forming a floating gate oxide film on the semiconductor substrate exposed through the floating gate sphere between both sidewalls; Forming a floating gate to fill the floating gate sphere by forming a first polycrystalline silicon layer on the floating gate oxide layer and the sidewall; Removing the oxide film and the sidewall; Forming an insulating film having a thickness of 100-1000 Å on the floating gate and the semiconductor substrate so as to surround the floating gate, and forming a control gate by depositing a second polycrystalline silicon layer on the insulating film; And selectively etching the control gate and the insulating film.
이하, 본 발명에 따른 플래쉬 메모리 및 그 제조방법에 대해 상세히 설명한다.Hereinafter, a flash memory and a method of manufacturing the same according to the present invention will be described in detail.
도 2d는 본 발명의 일실시예에 따른 플래쉬 메모리가 도시된 단면도로서, 이에 도시된 바와 같이, 본 발명의 일실시예에 따른 플래쉬 메모리는 반도체 기판의 소정영역에 형성된 플로팅 게이트 산화막(14)과, 플로팅 게이트 산화막(14)의 상부에 형성되고, 상부의 가장자리가 뾰족한 형상을 가지는 플로팅 게이트(15'), 반도체 기판 및 플로팅 게이트 상에 형성되고, 균일한 두께를 가지는 절연막(16), 및 절연막 상에 형성된 콘트롤 게이트(17')로 이루어진 구성이다.2D is a cross-sectional view showing a flash memory according to an embodiment of the present invention. As shown in the drawing, a flash memory according to an embodiment of the present invention may include a floating gate oxide film 14 formed in a predetermined region of a semiconductor substrate. , An insulating film 16 formed on the floating gate oxide film 14 and having a pointed upper edge, formed on the semiconductor substrate and the floating gate, and having an uniform thickness, and an insulating film. The control gate 17 'is formed on the structure.
이 때, 절연막(16)은 산화막-질화막-산화막의 3층 구조 또는 산화막의 단일 구조로 이루어질 수 있으며, 플로팅 게이트(15')의 일부분을 감싸도록 형성되고, 1000Å 이하의 두께를 가지는 것이 바람직하다.At this time, the insulating film 16 may have a three-layer structure of an oxide film-nitride film-oxide film or a single structure of an oxide film, and is formed to surround a portion of the floating gate 15 ', and preferably has a thickness of 1000 占 퐉 or less. .
그러면, 이러한 구조의 플래쉬 메모리를 제조하는 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Next, a method of manufacturing a flash memory having such a structure will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 플래쉬 메모리의 제조방법이 도시된 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a flash memory according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11) 상에 희생산화막(12)을 플로팅 게이트의 높이 해당하는 두께로 형성한 후, 이를 선택적으로 식각하여 플로팅 게이트구(100)를 형성한다.First, as shown in FIG. 2A, the sacrificial oxide film 12 is formed on the semiconductor substrate 11 to a thickness corresponding to the height of the floating gate, and then selectively etched to form the floating gate sphere 100.
이 때 희생산화막(12)의 두께는 3000-4000Å 정도가 되도록 형성한다.At this time, the sacrificial oxide film 12 is formed to have a thickness of about 3000-4000 kPa.
이어서, 플로팅 게이트구(100)를 통해 노출된 반도체 기판(11)을 포함하여 희생산화막(12) 상에 질화막을 증착한 후, 희생산화막(12)이 노출될 때까지 질화막을 식각하여 플로팅 게이트구(100)의 양 측벽에 잔존시킴으로써 잔존 질화막으로 이루어진 사이드월(13)을 형성한다.Subsequently, after the nitride film is deposited on the sacrificial oxide film 12 including the semiconductor substrate 11 exposed through the floating gate hole 100, the nitride film is etched until the sacrificial oxide film 12 is exposed. By remaining on both sidewalls of the (100), sidewalls 13 made of the remaining nitride film are formed.
그 후에, 양 사이드월(13)의 사이에서 플로팅 게이트구(100)를 통해 노출된 반도체 기판(11) 상에 플로팅 게이트 산화막(14)을 형성한다.Thereafter, the floating gate oxide film 14 is formed on the semiconductor substrate 11 exposed through the floating gate port 100 between both sidewalls 13.
이어서, 사이드월(13) 및 플로팅 게이트 산화막(14)을 포함하여 희생산화막(12)의 상부 전면에 플로팅 게이트구(100)를 충분히 매립하도록 제1다결정 실리콘층(15)을 형성한다.Subsequently, the first polycrystalline silicon layer 15 is formed to include the sidewall 13 and the floating gate oxide film 14 so as to sufficiently fill the floating gate sphere 100 in the entire upper surface of the sacrificial oxide film 12.
다음, 도 2b에 도시된 바와 같이, 희생산화막(12)이 노출될 때까지 제1다결정 실리콘층(15)을 화학기계적 연마하여 플로팅 게이트구(100)의 내부에 남김으로써, 다결정 실리콘으로 이루어지고 플로팅 게이트구의 내부에 매립된 형태의 플로팅 게이트(15')를 형성한다.Next, as shown in FIG. 2B, the first polycrystalline silicon layer 15 is chemically mechanically polished until the sacrificial oxide film 12 is exposed to the inside of the floating gate sphere 100, thereby being made of polycrystalline silicon. A floating gate 15 'having a shape embedded in the floating gate sphere is formed.
이어서, 희생산화막(12) 및 사이드월(13)을 각각 습식식각하여 제거한다.Subsequently, the sacrificial oxide film 12 and the sidewall 13 are respectively wet-etched and removed.
그 결과 제조된 플로팅 게이트(15')는 가장자리가 뾰족한 형상을 가지므로 이 곳에 응력이 집중되어 전자의 이동이 쉬워지며 따라서 소거 효율을 높일 수 있다.As a result, the manufactured floating gate 15 ′ has a sharp edge, and thus stress is concentrated therein, which facilitates the movement of electrons, thereby increasing the erase efficiency.
다음, 도 2c에 도시된 바와 같이, 플로팅 게이트(15')를 포함하여 반도체 기판(11)의 상부 전면에 절연막(16)을 형성하고, 절연막(16) 위에 제2다결정 실리콘층(17)을 형성한다.Next, as shown in FIG. 2C, an insulating film 16 is formed on the entire upper surface of the semiconductor substrate 11 including the floating gate 15 ′, and the second polycrystalline silicon layer 17 is formed on the insulating film 16. Form.
이 때 절연막(16)은 제1산화막, 질화막, 및 제2산화막을 순차적으로 적층하여 3층 구조로 형성할 수도 있고, 또는 산화막의 단일층 구조로 형성할 수도 있다.At this time, the insulating film 16 may be formed by stacking the first oxide film, the nitride film, and the second oxide film sequentially to have a three-layer structure, or may have a single layer structure of the oxide film.
또한, 절연막(16)은 소거효율을 높이기 위해 원하는 두께로 형성할 수 있으며, 바람직하게는 1000Å 이하의 두께로 형성할 수 있다.In addition, the insulating film 16 may be formed to a desired thickness in order to increase the erasing efficiency, and preferably may be formed to a thickness of 1000 GPa or less.
다음, 프로그래밍 효율을 높이기 위해 제2다결정 실리콘층(17) 및 그 하부의 절연막(16)을 선택적으로 식각하여 원하는 콘트롤 게이트 구조를 만듦으로써 다결정 실리콘으로 이루어진 콘트롤 게이트(17')를 완성한다.Next, in order to increase the programming efficiency, the second polycrystalline silicon layer 17 and the insulating layer 16 underneath are selectively etched to form a desired control gate structure, thereby completing the control gate 17 'made of polycrystalline silicon.
이로써, 본 발명의 일실시예에 따른 플래쉬 메모리의 제조가 완료된다.Thus, the manufacture of the flash memory according to the embodiment of the present invention is completed.
상기한 바와 같이, 본 발명에서는 희생 산화막을 증착 및 선택적 식각하여 플로팅 게이트구를 형성하고 여기에 질화막을 증착 및 식각하여 사이드월을 형성한 후 다결정 실리콘층을 매립함으로써 가장자리가 뾰족한 형상의 플로팅 게이트를 형성하며, 플로팅 게이트 상에 원하는 얇은 두께의 절연막을 형성하기 때문에, 종래 두꺼운 LOCOS 산화막으로 인해 저하되었던 소거 효율을 향상시키는 효과가 있다.As described above, in the present invention, a floating gate sphere is formed by depositing and selectively etching a sacrificial oxide film, and a sidewall is formed by depositing and etching a nitride film therein, and then filling the polycrystalline silicon layer to form a floating gate having a sharp edge shape. In addition, since the insulating film having a desired thin thickness is formed on the floating gate, there is an effect of improving the erase efficiency which has been degraded due to the conventional thick LOCOS oxide film.
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| US6165845A (en) * | 1999-04-26 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Method to fabricate poly tip in split-gate flash |
| US6358797B1 (en) * | 2001-02-12 | 2002-03-19 | Vanguard International Semiconductor Corporation | Method of forming a non-volatile memory cell |
| US20020110985A1 (en) * | 2001-02-12 | 2002-08-15 | Horng-Huei Tseng | Methid of making a single transistor non-volatile memory device |
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| JPH1065026A (en) * | 1996-08-19 | 1998-03-06 | Sanyo Electric Co Ltd | Manufacturing method of nonvolatile semiconductor memory device |
| US6165845A (en) * | 1999-04-26 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Method to fabricate poly tip in split-gate flash |
| US6358797B1 (en) * | 2001-02-12 | 2002-03-19 | Vanguard International Semiconductor Corporation | Method of forming a non-volatile memory cell |
| US20020110985A1 (en) * | 2001-02-12 | 2002-08-15 | Horng-Huei Tseng | Methid of making a single transistor non-volatile memory device |
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| KR100696374B1 (en) * | 2004-10-08 | 2007-03-19 | 삼성전자주식회사 | Non-volatile memory devices and methods of forming the same |
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