KR20040049544A - Method for cleaning polymer residue from wafer and method for fabricating semiconductor device using the same - Google Patents

Abstract

PURPOSE: A wafer cleaning method is provided to prevent a storage node from being attached to another storage node by completely eliminating polymer remnants on the surface of a wafer when the storage node is formed. CONSTITUTION: The surface of the wafer is firstly cleaned by using HB(1). The surface of the wafer is secondly cleaned by using a SC1 solution including NH4OH, H2O2 and H2O(3). The surface of the wafer is thirdly cleaned by using HF diluent(5). H2SO4 and H2O2 are mixed in a ratio of 6:1 at a temperature of 120 plus or minus 3 deg.C and for an interval of 30 seconds to form the HB.

Description

Method for cleaning polymer residue from wafer and method for fabricating semiconductor device using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a wet cleaning method for removing foreign matter on a wafer, and a semiconductor device manufacturing method in which a wet cleaning step is included in the middle of a process.

As the integration of semiconductor devices increases, in particular, in the case of semiconductor devices such as DRAM (Dynamic Random Access Memory), much effort is required to ensure sufficient cell capacitance in a limited area. Among them, the method of increasing the effective area of the storage node (the lower electrode of the capacitor) is most promising to be applied to the real process because it is relatively easy to implement the process. In particular, a method of three-dimensionally storing a storage node into a cylindrical shape is widely used to increase the effective area of the storage node.

Conventionally, in order to form a cylindrical storage node, a plurality of storage node holes are formed by etching an oxide-based sacrificial layer, and then a conductive layer is formed along an upper surface of the sacrificial layer and an inner wall of the storage node hole. By removing portions of the conductive layer formed on the top surface of the sacrificial layer, separate cylindrical storage nodes are formed. This is known as node separation. Then, remove the sacrificial layer.

In this process, an anti-reflection film made of Plasma Enhanced CVD SiON (PE-SiON) and a double layer of Plasma Enhanced CVD OXide (PE-OX) are used as an etch mask for etching the sacrificial layer to form the storage node holes. In order to keep the node hole depth constant, an etch stop film is used, which can serve as an etch end point, while a large amount of polymer residue is generated during the formation of the storage node hole by etching the anti-reflection film / PE-OX and the etch stop film. If not removed, this will have an undesirable effect on subsequent processes. Therefore, the wafer is cleaned under process conditions using SC1 (standard chemical) and HF to remove the conductive layer before forming the conductive layer. Such cleaning is commonly known as "precleaning." In addition, SC1 is well known here as a solution which mixed ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and deionized water (H ₂ O) in a mixing ratio of 1: 4: 20.

However, there is a problem in that the pretreatment conditions using SC1 and HF cannot completely remove the polymer residues. Polymer debris that remains on the wafer creates defects that stick together and clump together after storage. For example, 256M double data rate (DDR) products have a 20 percent defect rate. Such defects adversely affect the stability and reliability of the product.

Accordingly, the technical problem to be achieved by the present invention is to provide a wafer cleaning method capable of completely removing polymeric debris.

Another object of the present invention is to provide a method of manufacturing a semiconductor device without defects between storage nodes by using the wafer cleaning method as described above.

1 is a flowchart of a wafer cleaning method according to an embodiment of the present invention.

FIG. 2 is a system configuration of a wet station capable of performing wafer cleaning according to the method of FIG. 1.

3 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device including a cylindrical capacitor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

105 Insulation 110, 110 'Etch stop

125 ... Sacrifice 125a ... Sacrifice Pattern

130 ... Hard mask layer H ... Storage nodehole

140 ... Conductor Floor 140a ... Storage Nodes

145 capping film 150 dielectric film

155 ... upper electrode 160 ... cylindrical capacitor

Wafer cleaning method according to the present invention for achieving the above technical problem, is to remove the polymer residue completely by adding the sulphate to the existing SC1 + HF process conditions. The quality improvement can be aimed at by effectively removing unwanted polymeric debris.

In the method of manufacturing a semiconductor device according to the present invention for achieving the above technical problem, a sacrificial layer pattern defining a storage node hole is formed on a wafer, and then sulfuric acid is performed to first clean the surface of the sacrificial layer pattern. . Then, the sacrificial layer pattern surface is secondarily cleaned using the SC1 solution. The natural oxide film generated on the wafer surface due to the secondary cleaning is removed by tertiary cleaning using an HF diluent. Subsequently, a conductive layer is formed to a thickness that does not completely fill the storage node hole, and a capping film for completely filling the storage node hole is formed on the entire surface of the resultant layer on which the conductive layer is formed, and then the top surface of the sacrificial layer pattern is exposed. Until the capping film is formed, the upper surface of the resultant is flattened. The sacrificial layer pattern and the capping layer remaining in the storage node hole are removed to form separate cylindrical storage nodes, and the dielectric layer and the upper electrode are sequentially formed on the storage node to complete the process.

According to the present invention, even when an anti-reflection film made of PE-SiON film is used to etch the sacrificial layer to form a storage node hole, the polymer residues generated when the anti-reflection film is etched can be effectively cleaned by a unique cleaning method. Can be removed. As a result, the occurrence of defects between the capacitor storage nodes can be suppressed, and the quality of semiconductor devices such as 256M DDR products can be improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or wafer, a layer may exist in direct contact with the other layer or wafer, or a third layer may be intervened therebetween. have.

1 is a flowchart of a wafer cleaning method according to an embodiment of the present invention. Referring to Figure 1, it will be described in detail with respect to the wafer cleaning method of the present invention. For reference, the wafer cleaning method herein includes not only a bare silicon wafer cleaning method before the semiconductor device manufacturing process is performed, but also a wafer cleaning method having various films and patterns formed thereon. Consider.

First, a sulphate of sulfuric acid is performed to first clean the wafer surface (1). Boil sulfate is mixed with sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) to about 6: 1 to apply at a temperature of 120 ± 3 ℃. Such sulfuric acid boilers are very effective for removing organic matter. Therefore, it is excellent for removing the polymeric debris generated in the etching step. It is preferable to make a sulfuric acid boiling time about 300 second.

After completion of the primary cleaning, the wafer surface is secondary cleaned using SC1 solution (3). The SC1 solution is a mixed solution of ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and deionized water (H ₂ O), as is well known, and is an alkaline and corrosive solution. The mixing ratio of ammonia, hydrogen peroxide, and deionized water is 1: 4: 20. The operating temperature can be maintained at 80 ± 3 ℃ or 50 ± 3 ℃, it is preferable that 70 ± 3 ℃. The application time is about 300 seconds. The SC1 solution is excellent in particle removal and organic matter removal. Therefore, after the second cleaning according to the present invention, no polymeric residue remains on the wafer.

When the secondary cleaning is performed, a natural oxide film is generated on the surface of the wafer due to the characteristics of the SC1 solution. The third wash using HF dilution to remove it (5). For example, the mixing ratio of hydrofluoric acid (HF) and deionized water (H ₂ O) is 1: 5-1000, and the operating temperature is 25 ± 3 ° C. It is preferable to use 1: 100-200 mainly, and preferably 1: 200 is used in this invention. At this stage, the film quality of 20-40 kPa is etched and cleaned. Cleaning with HF diluent can cause hydrophobic water spots on the wafer surface, so the cleaning time should be determined appropriately, for example, within 90 seconds and the robot up time will be accelerated to prevent hydrophobization of the wafer surface. do.

On the other hand, between the first to third washing, and after the third washing is finished, washing with deionized water may be further included. For example, washing the wafer surface with a hot water shower, N ₂ bubbles and up-flow between the first and second cleanings 1 and 3 may be included. And washing the wafer surface with a deionized water shower, N ₂ bubbles and upflow between the secondary rinse 3 and the tertiary rinse 5. In addition, after completing the tertiary cleaning (5), the method may include washing the wafer surface by upflowing deionized water.

The system configuration of the wet station that can easily perform the wafer cleaning method of the present invention can be as shown in FIG.

Referring to FIG. 2, from the loader 10 to the unloader 55, the sulfuric acid boiler bath 15, the high temperature QDR (HQDR) 20, and the SC1 bath 25 are sequentially. Equipment of QDR (30), HF bath (35), overflow bath (OF), final rinse bath (FR) (45) and IPA (IsoPropyl Alcohol) dryer (50) Has a configuration. The robot 60 is then provided to move the wafer between the bath and the bath in the wet station.

When the wafer is loaded into the loader unit 10, the wafer is transferred to the sulphate sulphate bath 15, and the sulphate sulphate is performed as in step 1 of FIG. 1. It is then transferred to HQDR (20), where QDR (quick + dump + rinse) is performed with hot water. That is, the wafer surface is washed with water by performing a hot shower, N ₂ bubble, upflow, or the like on the wafer surface. The wafer is then transferred to the SC1 bath 25 and cleaned in accordance with step 3 of FIG. 1 and washed with QDR 30. Next, after removing from the HF bath 35 to the natural oxide film in accordance with step 5 of FIG. 1, the deionized water is upflowed for a predetermined time in the overflow bath 40 and washed with water. In the final flush bath 45, the cleaning state of the wafer surface is checked by a rinse step immediately before drying the wafer. The deionized water on the wafer surface is then dried in an IPA dryer 50. Here, the IPA in the chamber is vaporized using a heater under the chamber, and then adsorbed onto the wafer to replace the remaining moisture. The wafer is slowly lifted upwards, and the IPA adsorbed on the wafer is dried by nitrogen purge or air drying. The wafer surface is carried out through the unloader unit 55 in a state where the deionized water is thus dried. The robot 60 moves the wafer between the bath and the bath within the wet station.

Pre-cleaning by using the wafer cleaning method of the present invention as described in detail above can effectively remove polymeric debris, and can manufacture a semiconductor device while suppressing adhesion between capacitor storage nodes. This will be described with reference to FIGS. 3 to 8.

First, referring to FIG. 3, an insulating film 105 and an etch stop film 110 are sequentially formed on a wafer 100 on which a substructure (not shown), such as a transistor, is formed, and then an etch stop film 110 and an insulating film. The contact plug 120 penetrates the 105 to contact the impurity region of the wafer 100. The etch stop layer 110 is formed to have a thickness of about 100 to 2000Å, and is formed of a film that can act as an etching end point when etching the sacrificial layer formed in a subsequent process. For example, when an oxide film is formed as a sacrificial layer, the etch stop film 110 is formed of a silicon nitride film.

Plasma Enhanced CVD Tetra Ethyl Ortho Silicate (PE-TEOS), Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), High Density Plasma (HDP) on the contact plug 120 and the etch stop layer 110 A sacrificial layer 125 is formed by stacking an oxide film, such as a) film or a USG (Undoped Silicate Glass) film, and then forming a hard mask film 130 on the sacrificial layer 125. The hard mask layer 130 may be formed to a thickness of about 500 to 5000 Å, and may be formed as a double layer of an anti-reflection film 129 such as PE-OX film 128 and PE-SiON. A photoresist pattern 132 having an opening A is formed on a region of the hard mask layer 130 corresponding to the top surface of the contact plug 120 and the etch stop layer 110 around the hard plug layer 130.

As shown in FIG. 4, the hard mask layer 130 and the sacrificial layer 125 are etched using the photoresist pattern 132 as an etching mask to form the hard mask pattern 130a and the sacrificial layer pattern 125a. . The hard mask pattern 130a and the sacrificial layer pattern 125a define the storage node hole H exposing the top surface of the contact plug 120 and the etch stop layer 110 around the contact plug 120.

Subsequently, the photoresist pattern 132 is removed by ashing, and then the front surface of the resultant in which the storage node holes H are formed is subjected to wafer cleaning according to the method described with reference to FIG. 1 to remove polymeric debris. At this time, a wet station as shown in Fig. 2 can be used.

Meanwhile, the stacking order of the etch stop layer 110 may be changed. That is, as shown in FIG. 5, the contact plug 120 may be formed through the insulating layer 105 to contact the impurity region of the wafer, and then the etch stop layer 110 ′ may be stacked. In this case, after the sacrificial layer pattern 125a is formed, the sacrificial layer pattern 125a is used as an etch mask to expose the contact plug 120 buried under the etch stop layer 110 '. 110 '). When the etch stop layer 110 ′ is stacked on the contact plug 120 as described above, the etch stop layer 110 ′ supports the high-capacity capacitor storage node from the side, and thus the storage node has a superior mechanical strength in terms of mechanical strength. Can be obtained.

Next, as shown in FIG. 6, after the conductive layer 140 is formed to a thickness that does not completely fill the storage node hole H, the storage node hole H is completely formed on the entire surface of the resultant layer on which the conductive layer 140 is formed. A capping film 145 to be embedded is formed. The conductive layer 140 is formed of, for example, a doped polysilicon film to form a storage node. The capping layer 145 is formed to prevent foreign matter from filling in the storage node hole H in a subsequent process. Therefore, the capping layer 145 is preferably formed of a film having a high level coating property to completely fill the storage node hole H. For example, an SOG (Spin On Glass) film, a BPSG film, a PSG film, a USG film, a FOX (Flowable Oxide) film, or a photoresist film is formed as the capping film 145. When the sacrificial layer 125 and the capping film 145 are formed as the same film, a subsequent process of removing the sacrificial layer pattern 125a and the capping film 145 is facilitated.

Referring to FIG. 7, the upper surface of the resultant product in which the capping layer 145 is formed until the sacrificial layer patterns 125a are exposed is subjected to etch-back or chemical mechanical polishing (hereinafter referred to as “CMP”). By flattening. In the CMP slurry it may be used, including such as _{CeO 2, SiO 2, Mn 2} O 3 as an abrasive. The portions formed on the sacrificial layer pattern 125a of the conductive layer 140 are completely removed and the nodes are separated to form separate cylindrical storage nodes 140a.

Referring to FIG. 8, the sacrificial layer pattern 125a and the capping layer 145 remaining in the storage node hole H are removed from the result in which the storage node 140a is formed. When the sacrificial layer pattern 125a and the capping layer 145 are formed of the same oxide layer, the sacrificial layer pattern 125a and the capping layer 145 may be easily removed by a wet etching method. When the photoresist film is formed as the capping film 145, it is ashed by removing it. Next, the dielectric layer 150 and the upper electrode 155 are sequentially formed on the storage node 140a to complete the cylindrical capacitor 160. The capacitor 160 is in electrical contact with the impurity region of the wafer 100 by the contact plug 120.

As a result of the experiment of the present inventors, when the storage node of the 256M DDR product was formed by applying the wafer cleaning method of the present invention, it was confirmed that the defects did not occur between the storage nodes. After completing the capacitor manufacturing, the BIN4 failure index was not found, and there was no loss due to the defect between the storage nodes. In addition, it was confirmed that the cell capacitance was improved in the electrical property check result.

As mentioned above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical idea of the present invention. It is obvious.

According to the present invention described above, the polymeric debris present on the wafer surface is completely removed. As a result, when the capacitor storage node is formed by applying the wafer cleaning method of the present invention, defects between the storage nodes do not occur. Therefore, the manufacturing yield and quality of a semiconductor element can be improved, and the stability and reliability of a product are improved.

Claims (10)

Performing a boil sulfate to first clean the wafer surface; After completing the first cleaning, second cleaning the wafer surface using an SC1 solution including ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and deionized water (H ₂ O); And After the secondary cleaning is completed, terminating the surface of the wafer using an HF dilution solution in a third manner. The method of claim 1, wherein the sulphate sulfate is mixed with H ₂ SO ₄ and H ₂ O ₂ in a ratio of 6: 1 to 120 ± 3 ° C. for 300 seconds. The method of claim 1, wherein in the second cleaning, an SC1 solution of 70 ± 3 ° C. is applied for 300 seconds. The method of claim 1, wherein the sulfuric acid voile is mixed with H ₂ SO ₄ and H ₂ O ₂ 6: 1 and apply 120 ± 3 ℃, 300 seconds, and in the second wash the SC1 solution of 70 ± 3 ℃ 300 seconds, and the third cleaning, the wafer cleaning method characterized in that the HF dilution mixture of HF and H ₂ O 1: 1: 200 applied for 25 ± 3 ℃, 90 seconds. The method of claim 1, further comprising: washing the wafer surface with a hot water shower, N ₂ bubbles and up-flow between the first and second washes; Washing the wafer surface with a deionized water shower, N ₂ bubbles and upflow between the second and third washes; And After the tertiary cleaning is completed, upflowing deionized water to wash the wafer surface. Forming a sacrificial layer pattern defining holes on the wafer; Performing a sulphate sulfate to first clean the sacrificial layer pattern surface; After the first cleaning is completed, the sacrificial layer pattern surface is secondly cleaned using an SC1 solution including ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and deionized water (H ₂ O). step; After the second cleaning is completed, performing a third cleaning of the sacrificial layer pattern surface using an HF diluent; After the tertiary cleaning is completed, forming a conductive layer to a thickness that does not completely fill the hole; Forming a capping film completely filling the hole on the entire surface of the resultant material on which the conductive layer is formed; Planarizing an upper surface of a resultant product in which the capping layer is formed until the upper surface of the sacrificial layer pattern is exposed; Removing the sacrificial layer pattern and the capping layer remaining in the hole to form separate capacitor storage nodes; And And sequentially forming a dielectric film and an upper electrode on the storage node. The method of claim 6, wherein forming the sacrificial layer pattern comprises: Sequentially forming a sacrificial layer and a hard mask film on the wafer; Forming a photoresist pattern on the hard mask layer to define holes; Forming a hole by etching the hard mask layer and the sacrificial layer by using the photoresist pattern as an etching mask; And Removing the photoresist pattern; The first cleaning step is performed after removing the photoresist pattern. The method of claim 6, wherein the sulphate sulfate is mixed with H ₂ SO ₄ and H ₂ O ₂ in a ratio of 6: 1 to 120 ± 3 ° C. for 300 seconds. The method of claim 6, wherein in the secondary cleaning, an SC1 solution of 70 ± 3 ° C. is applied for 300 seconds. The method of claim 6, wherein the sulfuric acid voile is mixed with H ₂ SO ₄ and H ₂ O ₂ 6: 1 and apply 120 ± 3 ℃, 300 seconds, in the second wash the SC1 solution of 70 ± 3 ℃ And applying 300 seconds, and applying the HF dilution mixture of HF and H ₂ O at 1: 200 for 25 seconds at 3 ± 3 ° C. for 90 seconds.