KR20040047540A - A Ferroelectric memory device and a method of forming the same - Google Patents

Abstract

PURPOSE: A ferroelectric memory device is provided to solve a problem caused by conventional misalignment by continuously patterning a protecting glue layer and an interlayer dielectric, and to prevent a void and a lifting phenomenon caused by a conventional interface reaction by completely isolating a lower electrode and a ferroelectric layer from an interlayer dielectric thereunder by the protecting glue layer. CONSTITUTION: A semiconductor substrate(100) is prepared. An interlayer dielectric(110) and a protecting glue layer(120) are sequentially formed, including a contact hole(125) for exposing the semiconductor substrate. A buried contact(130) electrically contacts the semiconductor substrate through the contact hole. A part of the protecting glue layer near the buried contact is covered with a lower electrode(140) that overlaps the buried contact. The lower electrode and the protecting glue layer are covered with a ferroelectric layer(150). The ferroelectric layer is covered with an upper electrode(160) that overlaps the lower electrode.

Description

A ferroelectric memory device and a method of forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device and a method of forming the same, and more particularly, to a ferroelectric memory device without a pichlor phase and a method of forming the same.

The ferroelectric memory device uses a polarization phenomenon of the ferroelectric film. One type of ferroelectric memory devices is composed of one access transistor and one cell capacitor using a ferroelectric film as a dielectric film.

1 is a schematic cross-sectional view of a ferroelectric memory device according to the prior art.

A method of forming the ferroelectric memory device of FIG. 1 is as follows. First, gate electrodes (not shown) are formed on the semiconductor substrate 1, and source / drain regions (not shown) are formed in the semiconductor substrate 1 between the gate electrodes. An interlayer insulating film 3 is stacked to cover the source / drain regions and the gate electrodes. The interlayer insulating film is mainly formed of a silicon oxide film-based material. The interlayer insulating layer 3 is patterned to form a contact hole exposing the drain region of the semiconductor substrate 1, and the buried contact 5 is formed by filling the contact hole with a conductive layer. The lower electrode 7 is formed by stacking and patterning a lower electrode layer on the entire surface of the semiconductor substrate 1 on which the investment contact 5 is formed. A ferroelectric film 9 covering the lower electrode 7 is stacked. In order to crystallize the ferroelectric film 9, an annealing process is performed. An upper electrode 11 is formed by stacking and patterning an upper electrode layer on the ferroelectric layer 9.

In the above process, when the lower electrode 7 is stacked, the interface between the interlayer insulating film 3 and the lower electrode 7 becomes uneven as shown in FIG. 1 because the lamination is not performed well on the interlayer insulating film 3. The problem (E) which floats arises. In addition, when the annealing process is performed to crystallize the ferroelectric film 9 to have a perovskite structure, the interlayer insulating film 3 and the bare layer exposed by the lower electrode 7 are exposed. A reaction between the two films 3 and 9 occurs at the interface between the ferroelectric films 9 so that the ferroelectric film 9 becomes pyrochlore and volume expansion may occur. This may subsequently form voids V and cause a malfunction of the memory device.

In order to prevent this, the ferroelectric memory device disclosed in Korean Patent Publication No. 10-0195262 and a method of forming the same will be described with reference to FIG. 2.

Referring to FIG. 2, the buried contact 5 is exposed by stacking and patterning a protective adhesive film 6, such as a titanium oxide film, on an entire surface of the semiconductor substrate 1 on which the buried contact 5 of FIG. 1 is formed. . Subsequently, the lower electrode 7 is formed to cover a portion of the protective adhesive film 6 and the exposed investment contact 5, and then a ferroelectric layer 9 and an upper electrode 11 are formed. However, the structure and formation method thereof of FIG. 2 are vulnerable to mis-alignment since the protective adhesive film 6 is patterned after the formation of the buried contact 5, and thus, the lower electrode 7 and the interlayer insulating film. (3) may come into contact, and problem E may occur at the interface as shown in FIG.

Accordingly, the technical problem of the present invention is to solve the above problems and to provide a reliable ferroelectric memory device and a method of forming the same.

1 is a schematic cross-sectional view of a ferroelectric memory device according to the prior art.

2 is a schematic cross-sectional view of another ferroelectric memory device according to the prior art.

3 is a schematic cross-sectional view of a ferroelectric memory device according to an embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of sequentially forming the ferroelectric memory device of FIG. 3.

FIG. 5 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing one subsequent process in the state of FIG. 3.

FIG. 6 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing another subsequent process in the state of FIG. 3.

7 is a schematic cross-sectional view of a ferroelectric memory device according to another embodiment of the present invention.

8A through 8D are process cross-sectional views illustrating a method of sequentially forming the ferroelectric memory device of FIG. 7.

FIG. 9 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing one subsequent process in the state of FIG. 7.

FIG. 10 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing another subsequent process in the state of FIG. 7.

Accordingly, a ferroelectric memory device according to the present invention for achieving the above technical problem is a semiconductor substrate, an interlayer insulating film and a protective adhesive film sequentially stacked with a contact hole for exposing the semiconductor substrate, and the semiconductor substrate through the contact hole; An investment contact which is electrically in contact with the electrode, a lower electrode covering a portion of the protective adhesive layer surrounding the investment contact, a ferroelectric layer covering the lower electrode and the protective adhesive layer, and the ferroelectric layer and overlap the lower electrode. It is provided with an upper electrode. In the ferroelectric memory device, the protective adhesive film is preferably made of a titanium oxide film (TiO ₂ ).

The ferroelectric memory device may further include a barrier layer pattern interposed between the buried contact and the lower electrode in the contact hole. In this case, the barrier layer pattern may be formed of at least one material selected from the group consisting of TiN, TiAlN, TiSi _X , TiSiN, TaSiN, and TaAlN.

In the ferroelectric memory device, the upper electrode preferably overlaps at least two of the lower electrodes at the same time. The ferroelectric memory device may further include an upper interlayer insulating layer covering the ferroelectric layer and the upper electrode, and a plate line electrically connected to the upper electrode through the upper interlayer insulating layer. Furthermore, the ferroelectric memory device may further include a strip line on the upper interlayer insulating layer and an upper interlayer insulating layer covering the strip line, wherein the plate line includes the upper interlayer insulating layer and the upper layer. The interlayer insulating film may be sequentially penetrated to be electrically connected to the upper electrode.

The ferroelectric memory device may be formed using the following method. According to the above method, first, an interlayer insulating film and a protective adhesive film are sequentially stacked on a semiconductor substrate. The protective adhesive layer and the interlayer insulating layer are patterned to form contact holes exposing the semiconductor substrate. A buried contact electrically connected to the semiconductor substrate is formed in the contact hole. A lower electrode is formed to overlap a portion of the buried contact to cover a portion of the protective adhesive layer around the buried contact. A ferroelectric film is formed to cover the lower electrode and the protective adhesive film. An upper electrode is formed to cover the ferroelectric layer and overlap the lower electrode.

In the method, before forming the lower electrode, the upper portion of the investment contact is recessed, the barrier layer is stacked to fill the recessed area in the contact hole, and the planarization process is performed on the barrier layer. The barrier layer pattern may be formed on the recessed buried contact in the contact hole while exposing the protective adhesive layer.

In the above method, the upper electrode may be formed to overlap with the at least two lower electrodes at the same time. In a subsequent process, an upper interlayer insulating film may be formed to cover the ferroelectric layer and the upper electrode, and a plate line may be formed through the upper interlayer insulating film to be electrically connected to the upper electrode. Prior to forming the plate line, a strip line may be formed on the upper interlayer insulating film and an upper metal interlayer insulating film may be formed to cover the strip line, wherein the plate line may include the upper metal interlayer insulating film and the upper interlayer insulating film. It can be penetrated in turn and electrically connected to the upper electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. If it is mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

<Example 1>

3 is a schematic cross-sectional view of a ferroelectric memory device according to an embodiment of the present invention.

Referring to FIG. 3, a plurality of gate electrodes (not shown) are disposed on the semiconductor substrate 100, and source / drain regions (not shown) are positioned on the semiconductor substrate 100 between the gate electrodes. Bit lines (not shown) in contact with the source region are positioned. An interlayer insulating layer 110 and a protective adhesive layer 120 that are sequentially stacked to cover the plurality of gate electrodes and source / drain regions are disposed on the semiconductor substrate 100. The protective adhesive film 120 is made of a titanium oxide film (TiO ₂ ).

A contact hole 125 is formed through the protective adhesive layer 120 and the interlayer insulating layer 110 to expose a drain region (not shown) of the semiconductor substrate 100. An investment contact 130 is formed to fill the contact hole 125 and to be in electrical contact with the drain region (not shown). The lower electrode 140 is formed to overlap the buried contact 130 and partially cover the protective adhesive layer 120 positioned in the periphery of the buried contact 130. A ferroelectric film 140 is disposed to cover the protective adhesive film 120 exposed without being covered by the lower electrode 14 and the lower electrode 14, and partially covers the ferroelectric film 150 thereon. The upper electrode 160 is disposed to overlap the lower electrode 140 to form a capacitor. The upper electrode 160 overlaps the two lower electrodes 140 at the same time.

The ferroelectric film 150 includes PZT [Pb (Zr, Ti) O ₃ ], PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , PbLaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , BST [(Ba, Sr ) TiO ₃ ], Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ And Bi ₄ Ti ₃ O _{12 It} can be made of one material selected from the group comprising. The lower electrode 140 and the upper electrode 160 are ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ) , Iridium oxide (IrO _X ), and at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Can be.

In the above structure, the protective adhesive film 120 made of a titanium oxide film has a good adhesive strength with the lower electrode 140 and does not cause a pyrochlore phase in the ferroelectric film 150. That is, the protective adhesive film 120 serves as a glue layer at the interface between the lower electrode 140 and the interlayer insulating film 110, and the ferroelectric film 150 is the interlayer insulating film 110. It serves as a protective layer to suppress the reaction occurring at the interface with the (). Therefore, since the lower electrode 140 and the ferroelectric film 150 are completely separated from the interlayer insulating film 110 by the protective adhesive film 120, a void caused by a reaction generated at an interface with the interlayer insulating film ( V) and lifting (E) phenomenon can be prevented.

In addition, in the above structure, the upper electrode 160 overlaps with the two lower electrodes 140 at the same time, thereby sufficiently securing the process margin when the plate line is subsequently formed.

4A through 4D are cross-sectional views illustrating a method of sequentially forming the ferroelectric memory device of FIG. 3.

Referring to FIG. 4A, a plurality of gate electrodes (not shown) are formed on the semiconductor substrate 100, and source / drain regions (not shown) are formed in the semiconductor substrate 100 between the gate electrodes. A bit line (not shown) is formed to contact the source region (not shown). An interlayer insulating layer 110 is formed on an entire surface of the semiconductor substrate 100 including the gate electrodes and the source / drain regions. The interlayer insulating layer 110 is at least one selected from the group consisting of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), and spin on glass (SOG). Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glss (BPSG), High density plasma (HDP) oxide, Plasma enhanced tetraethyl orthosilicate (PETOS), Undoped Silicate Glass (USG), Phosphorus Silicate Glss (PSG), It may be formed of at least one material selected from the group comprising PE-SiH ₄ and Al ₂ O ₃ . A protective adhesive film 120 is laminated on the interlayer insulating film 110. The protective adhesive film 120 may be formed of a titanium oxide film (TiO ₂ ) using a method such as CVD.

Referring to FIG. 4B, the protective adhesive layer 120 and the interlayer insulating layer 110 are successively patterned to form a contact hole 125 exposing a drain region (not shown) of the semiconductor substrate 100. The protective adhesive film 120 formed of a titanium oxide film may be etched using a mixed gas of a fluorine carbide gas such as CHF ₃ and CF ₄ and a chlorine gas such as Cl _2, and the interlayer insulating film 110 may be CHF _3. And a fluorocarbon gas such as CF ₄ .

Referring to FIG. 4C, a conductive film 129 is stacked on the entire surface of the semiconductor substrate 100 on which the contact hole 125 is formed to fill the contact hole 125. The conductive layer 129 may be at least one material selected from the group including tungsten, aluminum, copper, and a polysilicon layer doped or not doped with impurities.

Referring to FIG. 4D, a planarization process such as chemical mechanical polishing (CMP) is performed on the conductive layer 129 to expose the protective adhesive layer 120 and at the same time, the conductive layer 129 in the contact hole 125. A buried contact 130 is formed. A lower electrode layer (not shown) is stacked and patterned on the entire surface of the semiconductor substrate 100 on which the investment contact 130 is formed to overlap the investment contact 130 and partially cover the protective adhesive film 120. The electrode 140 is formed. The lower electrode 140 includes ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ), and iridium oxide (IrO _X ) And at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Can be. The lower electrode film is well deposited on the protective adhesive film 120 without the lifting phenomenon (E in FIGS. 1 and 2) as in the prior art.

Subsequently, referring to FIG. 3, the ferroelectric layer 150 is stacked to cover the protective adhesive film 120 that is not covered by the lower electrode 140 and the lower electrode 140. The ferroelectric film 150 includes PZT [Pb (Zr, Ti) O ₃ ], PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , PbLaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , BST [(Ba, Sr TiO ₃ ], Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O _9, and Bi ₄ Ti ₃ O ₁₂ . The ferroelectric film 150 uses one method selected from the group consisting of sputtering, chemical vapor deposition, sol-gel, and atomic layer deposition. Can be formed. An annealing process is performed such that the ferroelectric film 150 has a perovskite structure. Since the ferroelectric film 150 does not contact the interlayer insulating film 110, no pyrochlore phase is formed, and voids (V in FIG. 1) due to volume expansion are not formed as in the prior art.

An upper electrode layer (not shown) is stacked and patterned on the ferroelectric layer 150 to form an upper electrode 160 to overlap the lower electrode 140 and partially cover the ferroelectric layer 150. The upper electrode 160 includes ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ), and iridium oxide (IrO _X ) And at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Can be. The upper electrode 160 is preferably formed to overlap with at least two lower electrodes 140 as shown in FIG. This makes it possible to increase the process margin in forming grooves for subsequent plate lines to be formed.

FIG. 5 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing one subsequent process in the state of FIG. 3.

Referring to FIG. 5, the upper interlayer insulating layer 170 is stacked in the state of FIG. 3. The upper interlayer insulating film 170 may be formed of the same material in the same manner as the interlayer insulating film 110. The upper interlayer insulating layer 170 is patterned to form a groove 175 exposing the upper electrode 160. In this case, the upper electrode 160 serves as an etch stop layer. The conductive material is stacked and patterned conformally along the profile of the groove 175 to form a plate line 180 as shown in FIG. 5. Since the upper electrode 160 overlaps at least two of the lower electrodes 140 at the same time, a large area can secure sufficient process margin when forming the groove 175.

FIG. 6 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing another subsequent process in the state of FIG. 3.

Referring to FIG. 6, the upper interlayer insulating layer 170 is stacked in the state of FIG. 3. After the wiring process of forming the strip line 172 or the like on the upper interlayer insulating layer 170 is performed, an upper metal interlayer insulating layer 174 covering the strip line 172 is formed. The upper interlayer insulating layer 174 and the upper interlayer insulating layer 170 are sequentially patterned to form a groove 175 that exposes the upper electrode 160. The groove 175 may be formed with the upper electrode 160 through the groove 175. The plate line 180 to be electrically connected is formed. The strip line 172 and the plate line 180 are aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium At least one selected from the group consisting of (Os), palladium (Pd), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride film (TiN) and tantalum nitride film (TaN) It can be formed of a material.

<Example 2>

7 is a schematic cross-sectional view of a ferroelectric memory device according to another embodiment of the present invention.

Referring to FIG. 7, the barrier layer pattern 135 is interposed between the lower electrode 140 and the buried contact 125 in the contact hole 125. The barrier layer pattern 135 is formed of a single layer or multiple layers of at least one material selected from the group consisting of TiN, TiAlN, TiSi _X , TiSiN, TaSiN, and TaAlN. Although not shown, a titanium silicide (TiSi _X ) film may be interposed between the barrier film pattern 135 and the investment contact 125 as an ohmic layer. Other structures, kinds of materials, and the like are the same as those in FIG.

In the structure, the barrier film pattern 135 serves to prevent the oxidation of the investment contact 130 by blocking the transmission of oxygen and hydrogen. In addition, the barrier layer pattern 135 has good adhesive strength with the lower electrode 140.

8A through 8D are process cross-sectional views illustrating a method of sequentially forming the ferroelectric memory device of FIG. 7.

Referring to FIG. 8A, a planarization process such as chemical mechanical polishing (CMP) is performed on the conductive layer 129 in the state of FIG. An investment contact (130 in FIG. 4D) formed of a film 129 is formed. The top of the investment contact (130 of FIG. 4D) is recessed using a front etch back process to form an investment contact 130 that fills a substantial portion of the contact hole 125 as shown in FIG. 8A. The etch back process is performed using an etching selectivity between the protective adhesive layer 120 and the investment contact 130, and the protective adhesive layer 120 is formed while the upper portion of the investment contact 130 is recessed. Almost no etching

Referring to FIG. 8B, a barrier layer 134 is stacked on the entire surface of the semiconductor substrate 100 on which the investment contact 130 filling the substantial portion of the contact hole 125 is formed, and then buried in the investment contact 130. Fill the upper portion of the contact hole 125 that is not filled by. In this case, the barrier layer 134 is at least one selected from the group consisting of sputtering, chemical vapor deposition, sol-gel, and atomic layer deposition. It may be formed of at least one material selected from the group containing TiN, TiAlN, TiSi _X , TiSiN, TaSiN, and TaAlN.

Referring to FIG. 8C, the barrier layer pattern 135 filling the upper portion of the contact hole 125 while exposing the protective adhesive layer 120 by performing a planarization process such as CMP on the barrier layer 134. To form.

Referring to FIG. 8D, a lower electrode layer (not shown) is stacked and patterned on the barrier layer pattern 135 and the protective adhesive layer 120 to form a lower electrode 140. The lower electrode layer (not shown) is well deposited on the barrier layer pattern 135 and the protective adhesive layer 120 without the lifting phenomenon (E of FIGS. 1 and 2) as in the prior art.

Subsequently, a ferroelectric film 150 is conformally stacked on the semiconductor substrate 100 on which the lower electrode 140 is formed, as shown in FIG. 7. An annealing process is performed such that the ferroelectric film 150 has a perovskite structure. At this time, since the ferroelectric layer 150 does not contact the interlayer insulating layer 110 and the barrier layer 135, a pyrochlore phase is not formed, and voids (V in FIG. 1) due to volume expansion are not formed as in the prior art. . In addition, since the barrier layer 135 is not exposed during the formation of the ferroelectric layer 150 or the annealing process using oxygen, the lower electrode may be minimized by minimizing stress in the barrier layer 135 that may occur in the process. 140 can be prevented from floating.

An upper electrode layer (not shown) is stacked and patterned on the ferroelectric layer 150 to form an upper electrode 160 to overlap the lower electrode 140 and partially cover the ferroelectric layer 150. The upper electrode 160 is preferably formed to overlap with at least two lower electrodes 140 as shown in FIG. This makes it possible to increase the process margin when forming grooves for subsequent platelines.

Process conditions not mentioned in this embodiment, the kind of material constituting the film and the method of forming the film are the same as in Example 1.

FIG. 9 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing one subsequent process in the state of FIG. 7.

Referring to FIG. 9, the upper interlayer insulating layer 170 is stacked in the state of FIG. 7. The upper interlayer insulating film 170 may be formed of the same material in the same manner as the interlayer insulating film 110. The upper interlayer insulating layer 170 is patterned to form a groove 175 exposing the upper electrode 160. In this case, the upper electrode 160 serves as an etch stop layer. The conductive material is stacked and patterned conformally along the profile of the groove 175 to form a plate line 180 as shown in FIG. 5. Since the upper electrode 160 overlaps at least two of the lower electrodes 140 at the same time, a large area can secure sufficient process margin when forming the groove 175.

FIG. 10 is a schematic cross-sectional view of a ferroelectric memory device formed by further performing another subsequent process in the state of FIG. 7.

Referring to FIG. 10, the upper interlayer insulating layer 170 is stacked in the state of FIG. 7. After the wiring process of forming the strip line 172 or the like on the upper interlayer insulating layer 170 is performed, an upper metal interlayer insulating layer 174 covering the strip line 172 is formed. The upper interlayer insulating layer 174 and the upper interlayer insulating layer 170 are sequentially patterned to form a groove 175 that exposes the upper electrode 160. The groove 175 may be formed with the upper electrode 160 through the groove 175. The plate line 180 to be electrically connected is formed.

Therefore, according to the ferroelectric memory device and the method of forming the same, the protective adhesive film and the interlayer insulating film are successively patterned to solve the problems caused by the conventional misalignment. The protective adhesive film completely separates the lower electrode and the ferroelectric film from the interlayer insulating film thereunder, thereby preventing void formation and lifting due to the conventional interfacial reaction. The barrier film can prevent oxidation of the investment contact. Since the barrier film is not exposed when the ferroelectric film is formed, the stress inside the barrier film can be minimized to prevent the lifting of the lower electrode. Since the ferroelectric film is not in contact with the interlayer insulating film and the barrier film, the ferroelectric structure of the perovskite structure can be exhibited without forming a pyrochlore phase, thereby increasing the reliability of the ferroelectric memory device. In addition, the upper electrode overlaps with the at least two lower electrodes at the same time to secure a sufficient process margin when forming a groove for forming a plate line.

Claims (26)

Semiconductor substrates; An interlayer insulating film and a protective adhesive film that are sequentially stacked with contact holes exposing the semiconductor substrate; An investment contact in electrical contact with the semiconductor substrate through the contact hole; A lower electrode overlapping the buried contact and covering a portion of the protective adhesive layer around the buried contact; A ferroelectric film covering the lower electrode and the protective adhesive film; And And an upper electrode covering the ferroelectric layer and overlapping the lower electrode. The method of claim 1, The protective adhesive film is a ferroelectric memory device, characterized in that consisting of a titanium oxide film (TiO ₂ ). The method of claim 1, And a barrier film pattern interposed between the buried contact and the lower electrode in the contact hole. The method of claim 3, wherein The barrier film pattern is made of at least one material selected from the group consisting of TiN, TiAlN, TiSi _X , TiSiN, TaSiN, and TaAlN. The method of claim 1, The ferroelectric film is PZT [Pb (Zr, Ti) O 3], PbTiO 3, SrTiO 3, BaTiO 3, PbLaTiO 3, (Pb, La) (Zr, Ti) O 3, BST [(Ba, Sr) TiO 3] And Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O _9, and Bi ₄ Ti ₃ O ₁₂ . The method of claim 1, The lower electrode and the upper electrode are ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ), and iridium oxide (IrO _X ) And at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). device. The method of claim 1, And the buried contact is made of at least one material selected from the group consisting of tungsten, aluminum, copper, and polysilicon doped or not doped with impurities. The method according to claim 1 or 2, And the upper electrode overlaps at least two of the lower electrodes at the same time. The method of claim 8, An upper interlayer insulating film covering the ferroelectric film and the upper electrode; And And a plate line penetrating the upper interlayer insulating film to electrically connect with the upper electrode. The method of claim 9, A strip line on the upper interlayer insulating film; And Further provided with an upper interlayer insulating film covering the strip line, And the plate line sequentially passes through the upper metal interlayer insulating film and the upper interlayer insulating film to electrically connect with the upper electrode. The method of claim 9, And the plate line is made of a conductive material. Sequentially stacking an interlayer insulating film and a protective adhesive film on the semiconductor substrate; Patterning the protective adhesive layer and the interlayer insulating layer to form a contact hole exposing the semiconductor substrate; Forming a buried contact in the contact hole to electrically connect with the semiconductor substrate; Forming a lower electrode to overlap a portion of the buried contact to cover a portion of the protective adhesive layer around the buried contact; Forming a ferroelectric film to cover the lower electrode and the protective adhesive film; And And forming an upper electrode to cover the ferroelectric layer and overlap the lower electrode. The method of claim 12, The protective adhesive film is a method of forming a ferroelectric memory device, characterized in that formed of a titanium oxide film. The method of claim 12, Forming the buried contact, Filling the contact hole by stacking a conductive film on an entire surface of the semiconductor substrate on which the contact hole is formed; And And forming a buried contact made of the conductive film in the contact hole while exposing the protective adhesive film by performing a planarization process on the conductive film. The method of claim 12, Before forming the lower electrode, Recessing an upper portion of the investment contact; Stacking a barrier film to fill a region in which the buried contact is recessed in the contact hole; And And forming a barrier layer pattern on the recessed buried contact in the contact hole while exposing the protective adhesive layer by performing a planarization process on the barrier layer. . The method of claim 15, And the barrier film is formed of at least one material selected from the group consisting of TiN, TiAlN, TiSi _X , TiSiN, TaSiN, and TaAlN. The method of claim 15, The barrier layer is formed using at least one method selected from the group consisting of sputtering, chemical vapor deposition, sol-gel, and atomic layer deposition. A method of forming a ferroelectric memory device, characterized in that. The method of claim 12, The ferroelectric film is PZT [Pb (Zr, Ti) O 3], PbTiO 3, SrTiO 3, BaTiO 3, PbLaTiO 3, (Pb, La) (Zr, Ti) O 3, BST [(Ba, Sr) TiO 3] , Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and Bi ₄ Ti ₃ O _{12 A} method of forming a ferroelectric memory device, characterized in that formed of one material selected from the group The method of claim 12, The lower electrode and the upper electrode are ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ), and iridium oxide (IrO _X ), And a ferroelectric, characterized in that it is formed of at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Method of forming a memory device. The method according to claim 12 or 15, And the upper electrode is formed to overlap at least two of the lower electrodes at the same time. The method of claim 20, Forming an upper interlayer insulating film covering the ferroelectric film and the upper electrode; And And forming a plate line penetrating the upper interlayer insulating film to electrically connect with the upper electrode. The method of claim 21, Before forming the plate line, Forming a strip line on the upper interlayer insulating film; And The method may further include forming an upper interlayer dielectric layer covering the strip line. And the plate line sequentially penetrates through the upper metal interlayer insulating film and the upper interlayer insulating film to electrically connect with the upper electrode. The method of claim 21, The plate line is formed of a conductive material, characterized in that the ferroelectric memory device. The method of claim 22, The interlayer insulating film, the upper interlayer insulating film, and the upper metal interlayer insulating film may include plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), and spin on glass (SOG). The method of forming a ferroelectric memory device, characterized in that formed using at least one method selected from the group comprising. The method of claim 12, The ferroelectric film is formed using at least one method selected from the group consisting of sputtering, chemical vapor deposition, sol-gel, and atomic layer deposition. Method for forming a ferroelectric memory device, characterized in that. The method of claim 12, The buried contact is formed of at least one material selected from the group consisting of tungsten, aluminum, copper, and polysilicon doped or undoped impurities.