KR100605101B1 - Ferroelectric memory device and method of forming the same - Google Patents

Abstract

A ferroelectric memory device and a method of forming the same are disclosed. The apparatus includes an interlayer insulating film laminated on a semiconductor substrate having an alignment key region; A protective film on the interlayer insulating film; A recessed region sequentially passing through the passivation layer and the interlayer insulating layer in the alignment key region; A residual conductive film covering sidewalls and bottoms of the recessed regions; A residual insulating film covering a portion of the bottom and sidewalls of the residual conductive film; And a lower electrode film and a ferroelectric film sequentially stacked on the residual insulating film and the residual conductive film, wherein the protective film is interposed between the lower electrode film and the residual insulating film, and the interposed protective film is the ferroelectric film. The diffusion of lead and the like in the interior is prevented and the reaction between the residual insulating film and the lead and the like is prevented, thereby preventing the floating phenomenon.

Ferroelectric film, titanium oxide film

Description

Ferroelectric memory device and method of manufacturing the same

1 is a cross-sectional view of a ferroelectric memory device having an alignment key region according to the prior art.

2 is a cross-sectional view of a ferroelectric memory device having an alignment key region according to an embodiment of the present invention.

3 through 7 are cross-sectional views sequentially illustrating a method of forming the ferroelectric memory device of FIG. 2.

* Explanation of symbols for the main parts of the drawings

1, 100: semiconductor substrate 3, 102: gate pattern

5, 104: first interlayer insulating film 7, 106: contact pad

9, 108: second interlayer insulating film 11, 116: protective film

13 and 110: spacer 15 and 112: contact conductive film

17, 114: insulating film 19, 118: barrier film

21 and 120: lower electrode films 23 and 122: ferroelectric films

25, 124: upper electrode film

The present invention relates to a nonvolatile memory device and a method of forming the same, and more particularly, to a ferroelectric memory device having an alignment key region and a method of forming the same.

As devices of semiconductor devices are highly integrated, it is an important task to form capacitors having a large capacity in a small area in a memory device using capacitors. As one of methods for realizing a small area large capacity capacitor, a method of forming a capacitor employing a dielectric film having a high dielectric constant has been studied. In particular, recently, many methods have been studied to form a nonvolatile memory device having a high operating characteristic without using refresh by using a ferroelectric in a capacitor. Representative ferroelectric film materials include metal titanate compounds such as PZT and BST. In order for these compounds to have ferroelectricity, they must be crystallized in a pre-stage material state of an amorphous structure, which is easy to form and process on a substrate, or crystallization having a ferroelectric array. In order to crystallize these materials, a step of processing for a predetermined time in a high temperature, oxygen atmosphere is usually required. However, when these materials are processed in a high temperature oxygen atmosphere, there may arise a problem that the components of the semiconductor device already formed are affected.

1 is a cross-sectional view of a ferroelectric memory device having an alignment key region according to the prior art.

Referring to FIG. 1, gate patterns 3 are formed on a semiconductor substrate 1 including a cell array region and an alignment key region, and a first interlayer insulating layer 5 is stacked. The first interlayer insulating layer 5 is planarized to expose top surfaces of the gate patterns 3. The contact pad 7 is formed between the gate patterns 3 by a self-aligned contact process. A second interlayer insulating film 9 is laminated on the entire surface of the semiconductor substrate 1. The protective film 11 is laminated on the second interlayer insulating film 9. The passivation layer 11 and the second interlayer insulating layer 9 are sequentially patterned to form contact holes in the cell array region and to form recessed regions for forming alignment key grooves in the alignment key region. A spacer 13 is formed to cover the inner wall of the contact hole, and the contact conductive layer 15 is stacked to fill the contact hole, and at the same time, to cover the inner wall and the bottom of the recessed region.

The insulating layer 17 is stacked on the contact conductive layer 15, and a planarization process is performed on the insulating layer 17 and the contact conductive layer 15 to expose the protective layer 11. The insulating film 17 and the contact conductive film 15 on the top are removed. Thus, a remaining conductive film made of the contact conductive film 15 and a remaining insulating film made of the insulating film 17 remain in the recessed area of the alignment key region. The barrier layer 19 and the lower electrode layer 21 are conformally stacked and patterned to form a lower electrode in the cell array region. The barrier layer 19 and the lower electrode layer 21 may remain in the alignment key region as shown in FIG. 1.

The ferroelectric film 23 and the upper electrode film 25 are sequentially stacked, and the upper electrode film 25 is patterned to form an upper electrode in the cell array region. And the ferroelectric film 23 is subjected to a heat treatment process to have a ferroelectric. At this time, a lead (Pb) component or the like in the ferroelectric film 23 diffuses through the lower electrode film 21 and the barrier film 19 to react with the insulating film 17 to form an undesirable compound. . As a result, the barrier layer 19, the lower electrode layer 21, the ferroelectric layer 23, etc. on the insulating layer 17 are lifted up, which makes it difficult to properly serve as an alignment key in a subsequent photolithography process.

In addition, due to the thickness of the passivation layer 11, the step difference between the cell array region and the peripheral circuit region is further increased. Therefore, in the patterning process for forming the metal contact in the peripheral circuit region, a metal contact open may occur because the lower conductive film is not completely penetrated, and a depth of focus (DOF) may be performed in a subsequent photolithography process. You may run out of margin.

Accordingly, in order to solve the above problems, the present invention provides a ferroelectric memory device and a method of forming the same, which can prevent the floating phenomenon by preventing the diffusion of lead components in the ferroelectric film and can alleviate the step. have.

In order to achieve the above technical problem, the ferroelectric memory device of the present invention comprises an interlayer insulating film stacked on a semiconductor substrate having an alignment key region; A protective film on the interlayer insulating film; A recessed region sequentially passing through the passivation layer and the interlayer insulating layer in the alignment key region; A residual conductive film covering sidewalls and bottoms of the recessed regions; A residual insulating film covering a portion of the bottom and sidewalls of the residual conductive film; And a lower electrode film and a ferroelectric film sequentially stacked on the residual insulating film and the residual conductive film, wherein the passivation film is interposed between the lower electrode film and the remaining insulating film.

In the ferroelectric memory device, the protective film is preferably made of a single film of titanium oxide (TiO ₂ ) or a double film of a titanium oxide film and a silicon nitride film.

A barrier layer may be interposed between the lower electrode layer and the passivation layer. In this case, the barrier film is at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), iridium (Ir), ruthenium (Ru), and tungsten (W) or the at least one It may be made of a silicide of a metal or a nitride of the at least one metal. The residual insulating film and the interlayer insulating film are preferably made of the same material. The ferroelectric film is PZT [Pb (Zr, Ti) O 3], PbTiO 3, SrTiO 3, BaTiO 3, PbLaTiO 3, (Pb, La) (Zr, Ti) O 3, BST [(Ba, Sr) TiO 3] , Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and It may be made of one material selected from the group having Bi ₄ Ti ₃ O ₁₂ .

The semiconductor substrate further includes a cell array region, the contact plug electrically passing through the passivation layer and the interlayer insulating layer and electrically connected to the semiconductor substrate in the cell array region; And a lower electrode layer, a ferroelectric layer, and an upper electrode layer overlapping the contact plug and sequentially stacked on the contact plug and the passivation layer.

A method of forming the ferroelectric memory device is as follows. First, an interlayer insulating film is formed on a semiconductor substrate having a cell array region and an alignment key region. The interlayer insulating layer is patterned to form a region recessed in the interlayer insulating layer in the alignment key region. A conductive film and an insulating film are sequentially stacked on the semiconductor substrate on which the recessed region is formed. A planarization process is performed to expose the interlayer insulating film, and to form a residual conductive film covering the bottom and sidewalls of the recessed region and a residual insulating film covering the bottom and sidewalls of the residual conductive film. A surface anisotropic etching process is performed to etch a part of the interlayer insulating film and a part of the remaining insulating film at the same time. A passivation layer is formed on the etched interlayer insulating layer, sidewalls of the remaining conductive layer, and the remaining insulating layer. A lower electrode layer is formed on the passivation layer. And a ferroelectric film is formed.

In the above method, the passivation layer may be formed by sputtering, low pressure chemical vapor deposition, or chemical vapor deposition.

A barrier film may be formed before forming the lower electrode film. The barrier film may be formed by sputtering or chemical vapor deposition. The ferroelectric film may be formed by metal organic chemical vapor deposition, sol-gel, or sputtering.

In the method, when the recessed region is formed, a contact hole penetrating the interlayer insulating layer may be formed in the cell array region. When the conductive layers are stacked, the contact hole may be filled with the conductive layer, and a contact plug including the conductive layer may be formed in the contact hole by the planarization process. In addition, the passivation layer may be formed to further cover the sidewall of the contact plug. An upper electrode is formed on the ferroelectric film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

2 is a cross-sectional view of a ferroelectric memory device having an alignment key region according to an embodiment of the present invention.

Referring to FIG. 2, gate patterns 102 are disposed on an active region defined by an isolation layer (not shown) on a semiconductor substrate 100 having a cell array region and an alignment key region. The gate pattern 102 may include a gate insulating layer, a gate electrode, a capping layer pattern, and a spacer covering sidewalls, which are sequentially stacked. Source / drain regions may be disposed in the active region between the gate patterns 102. A first interlayer insulating layer 108 is positioned on the same line as the gate patterns 102 and covers sidewalls of the gate patterns 102. Contact pads 106 are disposed between the gate patterns 102.

A second interlayer insulating layer 108 is positioned on the first interlayer insulating layer 104. The first and second interlayer insulating films 104 and 108 may be formed of Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glss (BPSG), High Density Plasma (HDP) oxide, Plasma Enhanced Tetraethyl Orthosilicate (PETOS), and Undoped Silicate Glass (USG). ), PSG (Phosphorus Silicate Glss), PE-SiH ₄ And Al ₂ O _{3 It} may be made of at least one material selected from the group containing. The second interlayer insulating film 108 has a thickness thinner than that of the conventional one (reference numeral 9 of FIG. 1).

The passivation layer 116 is positioned on the second interlayer insulating layer 108. The protective film 116 is made of a single film of titanium oxide (TiO ₂ ) or a double film of a titanium oxide film and a silicon nitride film. A contact hole 109a through the passivation layer 116 and the second interlayer insulating layer 109 to expose the contact pad 106 in the cell array region and the first interlayer insulating layer 104 in the alignment key region. A recessed area 109b is disposed that exposes. A bottom of the recessed region 109b may pass through the first interlayer insulating layer 104 to expose a pad oxide layer (not shown) on the semiconductor substrate 100. Alternatively, the bottom of the recessed region 109b may not reach the first interlayer insulating film 104 and may expose a predetermined depth of the second interlayer insulating film 108.

The spacer 110 is positioned on the inner wall of the contact hole 109a. Although not shown, spacers may also be located on the inner wall of the recessed region 109b. There is a contact plug 112a which fills the contact hole 109a and electrically connects with the contact pad 106, and a residual conductive layer 114b covering the sidewalls and the bottom of the recessed region 109b. The residual insulating layer 114b is positioned on the residual conductive layer 114b. In addition, the passivation layer 116 is positioned on the residual insulating layer 114b. The residual insulating film 114b is made of a material having the same etching selectivity as the second interlayer insulating film 108, and preferably made of the same material.

The lower electrode 120a overlapping the contact plug 120a is positioned in the cell array region, and the ferroelectric film 122 and the upper electrode 124a are positioned on the lower electrode 120a. The lower electrode 120a and the upper electrode 124a are ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ) , Iridium oxide (IrO _X ), and at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Can be. The ferroelectric film 122 may include PZT [Pb (Zr, Ti) O ₃ ], PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , PbLaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , BST [(Ba, Sr TiO ₃ ], Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and It may be made of one material selected from the group having Bi ₄ Ti ₃ O ₁₂ .

The upper electrode 124a may be formed to overlap at least two lower electrodes 120a at the same time. This increases the process margin upon subsequent top electrode contact formation. The barrier layer 118 may be located under the lower electrode 120a. In the alignment key region, the barrier layer 118, the lower electrode layer 120, and the ferroelectric layer 122 may exist, and the upper electrode layer 124 may also exist. An alignment key groove 126 is positioned in the alignment key region, and may serve as an alignment key in the photolithography process.

In the ferroelectric memory device having the above structure, a protective film 116 is interposed between the barrier film 118 and the residual insulating film 114b in the alignment key region, and thus, in the ferroelectric film 122 in a heat treatment process for subsequent ferroelectricity. Diffusion of lead components and the like can be prevented. Therefore, the conventional lifting phenomenon can be prevented. In addition, since the second interlayer insulating layer 108 has a thickness thinner than that of the related art, a step with the peripheral circuit region may be alleviated.

3 through 7 are cross-sectional views sequentially illustrating a method of forming the ferroelectric memory device of FIG. 2.

Referring to FIG. 3, an isolation layer (not shown) is formed on a semiconductor substrate 100 including a cell array region and an alignment key region to define an active region. A gate pattern 102 is formed on the active region. The gate pattern 102 may be formed by a conventional method. Source / drain regions (not shown) are formed in the active region between the gate patterns 102 by an ion implantation process. The first interlayer insulating layer 104 is stacked and planarized to expose the upper portion of the gate pattern 102. Contact pads 106 are formed between the gate patterns 102 by a self align contact (SAC) process. Although not illustrated, an etch stop layer may be formed to cover the upper portions of the gate patterns 102 and the upper portion of the contact pads 106.

A second interlayer insulating film 108 is stacked and selectively patterned to form a contact hole 109a exposing the contact pad 106 in the cell array region, and at the same time the first interlayer insulating film 108 in the alignment key region. May form a recessed region 109b exposing). In this case, the recessed region 109b may expose the pad oxide layer (not shown) on the semiconductor substrate 100 through the first interlayer insulating layer. The spacer layer is stacked and anisotropically etched to form a spacer covering the inner wall of the contact hole 109a. In this case, although not shown, a spacer may be formed to cover the inner wall of the recessed region 109b.

The first and second interlayer insulating films 104 and 108 may be formed of Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glss (BPSG), High Density Plasma (HDP) oxide, Plasma Enhanced Tetraethyl Orthosilicate (PETOS), and Undoped Silicate Glass (USG). ), PSG (Phosphorus Silicate Glss), PE-SiH ₄ and Al ₂ O ₃ It may be formed of at least one material selected from the group containing. The spacer layer may be formed of a silicon nitride layer. The first and second interlayer insulating films 104 and 108 include plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), and spin on glass (SOG). It may be formed using at least one method selected from the group.

The contact conductive layer 112 is stacked to fill the contact hole 109a and to cover the sidewalls and the bottom of the recessed region 109b. The contact conductive layer 112 may be formed of at least one material selected from the group consisting of aluminum, copper, tungsten, titanium, and tantalum. An insulating film 114 is formed on the contact conductive film 112. In this case, since the recessed region 109b has a wide width, the insulating layer 114 may not fill the recessed region 109b. The insulating layer 114 is formed of a material having the same etching selectivity as the second interlayer insulating layer 108 and is preferably formed of the same material.

Referring to FIG. 4, a planarization process is performed to remove the insulating layer 114 and the contact conductive layer 112 on the second interlayer insulating layer 108. Accordingly, the second interlayer insulating film 108 and the contact plug 112a may be exposed, and the remaining conductive film 112b and the remaining insulating film 114b covering the inner wall and the bottom of the recessed region 109b may be formed. You can remain.

Referring to FIG. 5, an anisotropic etching process is performed by using an etching selectivity between the contact conductive layer 112 and the insulating layers 108 and 114. At this time, since the interlayer insulating film 108 and the remaining insulating film 114b have the same etching selectivity, they are etched at the same etching rate. On the other hand, the contact plug 112a, the remaining conductive layer 112b, and the spacer 110 are not etched. The degree of etching of the insulating layers 108 and 114b is controlled by adjusting the progress time of the front side anisotropic etching process. The thickness of the second interlayer insulating layer 108 may be reduced by the front anisotropic etching process, so that the step with the peripheral circuit region may be reduced even when the subsequent protective layer 116 is stacked.

Referring to FIG. 6, a protective film 116 is conformally stacked on the entire surface of the resultant product. In this case, the passivation layer 116 may be formed by sputtering, low pressure chemical vapor deposition, or chemical vapor deposition. The protective layer 116 may be formed as a single layer of a titanium oxide layer or a double layer of a titanium oxide layer and a silicon nitride layer. In this case, the silicon nitride film may be formed by a low pressure chemical vapor deposition method. The passivation layer 116 may be formed to have a thickness that is about the thickness of the second interlayer insulating layer 108 or more in the front anisotropic etching process of FIG. 5.

Referring to FIG. 7, the passivation layer 116 may be planarized to expose the contact plug 112a and the remaining conductive layer 112b. The planarization process may be performed by stacking a sacrificial layer (not shown) on the passivation layer 116. The sacrificial layer may be removed after the planarization process is completed.

Subsequently, the barrier layer 118, the lower electrode 120, the ferroelectric layer 122, and the upper electrode 124a are formed as shown in FIG. 2. The barrier layer 118 may be formed by sputtering or chemical vapor deposition. The lower electrode 120a and the upper electrode 124a are ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ) , Iridium oxide (IrO _X ), and at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ) Can be. The ferroelectric film 122 may include PZT [Pb (Zr, Ti) O ₃ ], PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , PbLaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , BST [(Ba, Sr TiO ₃ ], Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and It may be formed of one material selected from the group having Bi ₄ Ti ₃ O ₁₂ .

In this case, the ferroelectric film 122 is not patterned, thereby preventing damage to the ferroelectric film due to etching. After the upper electrode 124a is formed, a heat treatment process for ferroelectricity of the ferroelectric film 122 is performed. At this time, the protective film 116 prevents diffusion of lead components and the like of the ferroelectric film 122 to suppress the conventional lifting phenomenon.

Therefore, according to the ferroelectric memory device and the method of forming the same, a protective film is interposed between the ferroelectric film and the remaining insulating film in the alignment key region, thereby preventing diffusion of lead components and the like in the ferroelectric film in a subsequent heat treatment process for ferroelectricity. Thus, the lifting phenomenon due to the reaction with the conventional lead component and the residual insulating film can be prevented. In addition, since the interlayer insulating layer is etched anisotropically and the thickness is thin, even if the protective film is present, it is possible to mitigate the step with the peripheral circuit region to prevent subsequent metal contact opening and to secure the dope margin.

Claims (21)

An interlayer insulating film stacked on the semiconductor substrate having an alignment key region; A recessed region formed in the interlayer insulating layer in the alignment key region; A residual conductive film covering sidewalls and bottoms of the recessed regions; A residual insulating film covering a portion of a bottom surface and an inner sidewall of the residual conductive film; A protective film covering an upper surface, an inner wall and a bottom surface of the residual insulating film and contacting an upper wall of the residual conductive film; And And a lower electrode layer and a ferroelectric layer sequentially stacked on the passivation layer. The method of claim 1, The protective film is a ferroelectric memory device, characterized in that the titanium oxide film (TiO ₂ ). The method of claim 1, The protective film is a ferroelectric memory device, characterized in that consisting of a double layer of titanium oxide film and silicon nitride film. The method of claim 1, And a barrier film interposed between the lower electrode film and the passivation film. The method of claim 4, wherein The barrier layer may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), iridium (Ir), ruthenium (Ru), and tungsten (W), or at least one metal of the at least one metal. A ferroelectric memory device comprising a silicide or a nitride of the at least one metal. The method of claim 1, And the residual insulating film and the interlayer insulating film are made of the same material. The method of claim 1, The ferroelectric film is PZT [Pb (Zr, Ti) O 3], PbTiO 3, SrTiO 3, BaTiO 3, PbLaTiO 3, (Pb, La) (Zr, Ti) O 3, BST [(Ba, Sr) TiO 3] , Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and A ferroelectric memory device, comprising: one material selected from the group having Bi ₄ Ti ₃ O ₁₂ . The method of claim 1, The semiconductor substrate further includes a cell array region, In the cell array region, the passivation layer is positioned on the interlayer insulating layer. The ferroelectric memory device, A contact plug electrically passing through the passivation layer and the interlayer insulating layer to electrically connect the semiconductor substrate; A lower electrode in contact with the contact plug on the passivation layer; A ferroelectric film on the lower electrode; And And an upper electrode on the ferroelectric layer. Forming an interlayer insulating film on a semiconductor substrate having a cell array region and an alignment key region; Patterning the interlayer insulating film to form a region recessed in the interlayer insulating film in the alignment key region; Sequentially stacking a conductive film and an insulating film on the semiconductor substrate on which the recessed region is formed; Performing a planarization process on the insulating film and the conductive film to expose the interlayer insulating film and to form a residual conductive film covering the bottom and sidewalls of the recessed region and a remaining insulating film covering the bottom and sidewalls of the residual conductive film. ; Performing an entire anisotropic etching process to simultaneously etch a portion of the interlayer insulating film and a portion of the residual insulating film to partially expose the top surface and sidewalls of the residual conductive film; Conformally stacking and planarizing a protective film to expose the top surface of the residual conductive film while leaving a protective film covering the top surface, the inner wall and the bottom surface of the residual insulating film on the interlayer insulating film and in the recessed region. ; Forming a lower electrode layer on the passivation layer; And Forming a ferroelectric film. The method of claim 9, The protective film is formed by sputtering, low pressure chemical vapor deposition, or chemical vapor deposition. The method of claim 9, The protective film is a method of forming a ferroelectric memory device, characterized in that formed of a titanium oxide (TiO ₂ ). The method of claim 9, The protective film is a method of forming a ferroelectric memory device, characterized in that formed of a double layer of titanium oxide film and silicon nitride film. The method of claim 12, The silicon nitride film is formed by a low pressure chemical vapor deposition (Low pressure chemical vapor deposition) method of forming a ferroelectric memory device. The method of claim 9, And forming a barrier film before forming the lower electrode film. The method of claim 14, The barrier layer may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), iridium (Ir), ruthenium (Ru), and tungsten (W), or at least one metal of the at least one metal. A method of forming a ferroelectric memory device, characterized in that formed of silicide or nitride of the at least one metal. The method of claim 14, And the barrier film is formed by sputtering or chemical vapor deposition. The method of claim 9, And the insulating film and the interlayer insulating film are formed of the same material. The method of claim 9, The ferroelectric film is PZT [Pb (Zr, Ti) O 3], PbTiO 3, SrTiO 3, BaTiO 3, PbLaTiO 3, (Pb, La) (Zr, Ti) O 3, BST [(Ba, Sr) TiO 3] , Ba ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ and A method of forming a ferroelectric memory device, characterized in that formed of one material selected from the group having Bi ₄ Ti ₃ O ₁₂ . The method of claim 9, The ferroelectric film is formed by a metal organic chemical vapor deposition (Metal organic chemical vapor deposition), sol-gel (sol-gel) or sputtering (Sputtering) method of forming a ferroelectric memory device. The method of claim 9, When the recessed region is formed, a contact hole penetrating the interlayer insulating layer is formed in the cell array region. When the conductive films are stacked, the contact holes are filled with the conductive films, When the planarization process is performed on the insulating layer, a contact plug formed of the conductive layer is formed in the contact hole. The passivation layer is formed to contact the side wall of the contact plug, And forming an upper electrode on the ferroelectric film. The method of claim 20, The lower electrode layer and the upper electrode include ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), osmium (Os), palladium (Pd), ruthenium oxide (RuO _X ), and iridium oxide (IrO). _X ), and at least one material selected from the group consisting of platinum oxide (PtO _X ), rhodium oxide (RhO _X ), osmium oxide (OsO _X ), and palladium oxide (PdO _X ). Method of forming ferroelectric memory device.

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