KR20040043245A - Structure of electrode for GaN-based semiconductor - Google Patents

Structure of electrode for GaN-based semiconductor Download PDF

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KR20040043245A
KR20040043245A KR1020020071433A KR20020071433A KR20040043245A KR 20040043245 A KR20040043245 A KR 20040043245A KR 1020020071433 A KR1020020071433 A KR 1020020071433A KR 20020071433 A KR20020071433 A KR 20020071433A KR 20040043245 A KR20040043245 A KR 20040043245A
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gan
layer
compound semiconductor
gallium nitride
diffusion barrier
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KR1020020071433A
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Korean (ko)
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추성호
장자순
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엘지이노텍 주식회사
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Abstract

PURPOSE: A structure of GaN compound semiconductor electrode is provided to restrain the surface reaction between a GaN compound semiconductor layer and a metal layer and prevent the mutual reaction between metal layers used as electrodes by additionally forming an inter-diffusion barrier between a contact layer and an electrode layer. CONSTITUTION: A structure of GaN compound semiconductor electrode is provided with a GaN compound semiconductor layer(11), a contact layer(12) formed on the GaN compound semiconductor layer, and an inter-diffusion barrier(13) formed on the contact layer. The GaN compound semiconductor electrode structure further includes an electrode layer(14) formed on the inter-diffusion barrier. Preferably, the inter-diffusion barrier is formed on a P type GaN compound semiconductor layer. Preferably, the inter-diffusion barrier is a multilayer metal. At this time, the multilayer metal is completed by sequentially depositing a Mo/W/Mo layer.

Description

질화갈륨(GaN)화합물 반도체의 전극구조{Structure of electrode for GaN-based semiconductor}Structure of electrode for GaN-based semiconductor

본 발명은 질화갈륨(GaN)화합물 반도체의 전극의 구성에 관한 것으로서, 특히, 반도체 접촉층과 전극층 사이에 중간 확산 장벽을 더 형성하여 열적, 전기적으로 안정된 오믹 전극이 구현되는 질화갈륨(GaN)화합물 반도체의 전극 구성에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of electrodes of gallium nitride (GaN) compound semiconductors. In particular, gallium nitride (GaN) compounds in which an intermediate diffusion barrier is formed between the semiconductor contact layer and the electrode layer to realize a thermally and electrically stable ohmic electrode It relates to the electrode configuration of a semiconductor.

질화갈륨(GaN)화합물 반도체는 청색 광을 구현할 수 있는 발광 다이오드(LED)로서, 최근들어 그 사용이 급증하고 있는 실정이다. 보다 고휘도의 광 및 안정적인 광을 구현하기 위하여 그 전극의 구성에 대한 연구가 많이 수행되고 있다.A gallium nitride (GaN) compound semiconductor is a light emitting diode (LED) capable of realizing blue light, and its use is increasing rapidly in recent years. In order to realize more high-brightness light and stable light, many researches have been conducted on the configuration of the electrode.

도 1은 종래 질화갈륨(GaN)화합물 반도체의 적층 구조를 설명하는 도면이다.1 is a diagram illustrating a laminated structure of a conventional gallium nitride (GaN) compound semiconductor.

도 1을 참조하면, 질화갈륨(GaN)화합물 반도체(GaN)층(1)과, 상기 질화갈륨(GaN)화합물 반도체 층의 상면에 형성되는 접촉층(2)과, 상기 접촉층(2)의 상면에 더 형성되는 전극층(3)이 포함된다. 나아가, 접촉층(2)은 금(Au)을 주된 성분으로 하고, 전극층(3)은 니켈(Ni)를 주된 성분으로 한다.Referring to FIG. 1, a gallium nitride (GaN) compound semiconductor (GaN) layer 1, a contact layer 2 formed on an upper surface of the gallium nitride (GaN) compound semiconductor layer, and the contact layer 2 The electrode layer 3 is further formed on the upper surface. Furthermore, the contact layer 2 is made of gold (Au) as the main component, and the electrode layer 3 is made of nickel (Ni) as the main component.

또한, 종래 질화갈륨(GaN)화합물 반도체는 다층의 구조가 적층된 뒤에, 전극의 적정한 오믹 조건을 찾기 위하여 열처리가 행하여지는 것이 일반적이다. 그러나, 이러한 열처리 공정시에, 전극으로 사용되는 금속과 질화갈륨(GaN)화합물 반도체의 계면에는 원하지 않는 성분 간의 상호 확산에 의해서 전극의 퇴화가 발생된다. 그리고, 이러한 전극의 퇴화는 장시간 소자 동작 시에 누설 전류를 증가시키는 원인으로 작용함으로써 반도체 소자의 신뢰성에 많은 영향을 주게된다.In addition, in the conventional gallium nitride (GaN) compound semiconductor, after the multilayer structure is laminated, heat treatment is generally performed to find an appropriate ohmic condition of the electrode. However, in this heat treatment step, deterioration of the electrode occurs due to mutual diffusion between unwanted components at the interface between the metal used as the electrode and the gallium nitride (GaN) compound semiconductor. In addition, such degeneration of the electrode acts as a cause of increasing the leakage current during the operation of the device for a long time has a large impact on the reliability of the semiconductor device.

이와 같은 금속-반도체 계면의 반응에 대해서 그 반응 기전을 중심으로 다시 설명한다. 열처리 시에는 질화갈륨(GaN)화합물 반도체와 금속에는 고열이 가해지고, 이 열에 의해서 상호 간에 일정한 반응이 일어나게 된다. 특히 이러한 반응은계면 에너지의 에너지를 줄이는 방향으로 일어나게 되고, 이 때의 에너지는 음성 활성화 에너지를 갖는다. 또한, 이러한 음성 에너지는 금속과 반도체의 상이한 이온화 에너지의 차이에 기인한다.Such a reaction of the metal-semiconductor interface will be described again with reference to the reaction mechanism. During the heat treatment, high heat is applied to the gallium nitride (GaN) compound semiconductor and the metal, and the heat causes a constant reaction to each other. In particular, this reaction occurs in the direction of reducing the energy of the interface energy, at which time the energy has a negative activation energy. This negative energy is also due to the difference in the different ionization energies of the metal and the semiconductor.

결국, 이러한 음성 에너지를 흡수하기 위하여 양자 간의 이온화 에너지의 차이를 줄임으로써, 금속과 반도체의 계면에서 안정되는 질화갈륨(GaN)화합물 반도체의 전극 구조를 형성할 수 있게된다.As a result, by reducing the difference in ionization energy between the two to absorb such negative energy, it is possible to form the electrode structure of the gallium nitride (GaN) compound semiconductor that is stable at the interface between the metal and the semiconductor.

본 발명은 질화갈륨(GaN)화합물 반도체와 상기 반도체에 접하는 금속층과의 계면 반응을 억제하고, 전극으로 사용되는 금속층 간의 상호 반응을 억제할 수 있는 질화갈륨(GaN)화합물 반도체의 전극 구조를 제안하는 것을 목적으로 한다.The present invention proposes an electrode structure of a gallium nitride (GaN) compound semiconductor capable of suppressing an interfacial reaction between a gallium nitride (GaN) compound semiconductor and a metal layer in contact with the semiconductor and suppressing mutual reaction between metal layers used as electrodes. For the purpose of

특히, 질화갈륨(GaN)화합물 반도체가 열적, 전기적으로 안정되게 작동될 수있는 오믹 전극의 구성을 제안하는 것을 목적으로 한다.In particular, an object of the present invention is to propose a configuration of an ohmic electrode in which a gallium nitride (GaN) compound semiconductor can be thermally and electrically operated stably.

도 1은 종래 질화갈륨화합물 반도체의 적층 구조를 설명하는 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining the laminated structure of the conventional gallium nitride compound semiconductor.

도 2는 본 발명에 따른 질화갈륨(GaN)화합물 반도체의 적층 구조를 설명하는 도면.2 is a view for explaining a laminated structure of a gallium nitride (GaN) compound semiconductor according to the present invention.

도 3은 본 발명 실시예와 비교례를 C-TLM방법에 의해서 열처리 시간의 경과에 따른 비접촉 저항을 측정하여 표시한 선도.Figure 3 is a diagram showing the measurement of the specific contact resistance according to the passage of the heat treatment time by the C-TLM method and the comparative example of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1, 11 : 질화갈륨(GaN)화합물 반도체1, 11: gallium nitride (GaN) compound semiconductor

2, 12 : 접촉층2, 12: contact layer

3, 14 : 전극층3, 14 electrode layer

13 : 중간 확산 장벽층13: intermediate diffusion barrier layer

상기된 바와 같은 목적을 달성하기 위한 본 발명에 따른 질화갈륨(GaN)화합물 반도체의 전극 구조는 질화갈륨(GaN)화합물 반도체의 상측에 형성되는 접촉층과, 상기 접촉층 상면에 형성되는 중간확산장벽층과, 상기 중간확산장벽층의 상면에 형성되는 전극층이 포함되는 것을 특징으로 한다.The electrode structure of the gallium nitride (GaN) compound semiconductor according to the present invention for achieving the above object is a contact layer formed on the upper side of the gallium nitride (GaN) compound semiconductor, and the intermediate diffusion barrier formed on the upper surface of the contact layer And an electrode layer formed on the upper surface of the intermediate diffusion barrier layer.

또 다른 측면에 따른 본 발명은 질화갈륨(GaN) 화합물 반도체층 상면의 접촉층과, 상단 전극의 사이에, 금속 과 질화갈륨 반도체 사이의 계면 반응 및 이온화 에너지를 조절하기 위하여, W(텅스텐), Mo(몰리브덴), Metal-Si(실리콘), Metal-N(질소), Cr(크롬), Pt(백금), Ti(티탄), Ru(루세늄)의 단일층, 또는 이층 이상의 조합으로 구성되어 열처리된 중간확산장벽층이 더 형성되는 것을 특징으로 한다.According to another aspect of the present invention, a tungsten (W) tungsten layer is used to control an interfacial reaction and ionization energy between a metal and gallium nitride semiconductor between a contact layer on an upper surface of a gallium nitride (GaN) compound semiconductor layer and an upper electrode. It consists of a single layer of Mo (molybdenum), Metal-Si (silicon), Metal-N (nitrogen), Cr (chromium), Pt (platinum), Ti (titanium), Ru (rucenium), or a combination of two or more layers. Heat-treated intermediate diffusion barrier layer is characterized in that it is further formed.

상기된 전극의 구성으로서 금속층 간의 상호 반응, 금속층과 반도체 층 간의 원치않는 상호 반응을 억제할 수 있어, 결국, 질화갈륨(GaN)화합물 반도체의 안정된 오믹 전극을 구현할 수 있다.As described above, the interaction between the metal layers and the unwanted interaction between the metal layer and the semiconductor layer can be suppressed, and thus, a stable ohmic electrode of a gallium nitride (GaN) compound semiconductor can be realized.

본 발명에서는 질화갈륨(GaN)화합물 반도체층과 상기 질화갈륨게 반도체층에 접하는 금속층과의 계면 반응을 선택적으로 조정할 수 있는 중간 확산 장벽을 제안한다. 상세히는, 질화갈륨(GaN)화합물 반도체층과 금속층의 계면에서는 Metal-Ga와, Metal-N의 반응이 일어나게 되는데, 이러한 반응을 선택적으로 조정하는데 기여할 수 있는 중간 확산 장벽을 제공하는 것이다.The present invention proposes an intermediate diffusion barrier capable of selectively adjusting the interfacial reaction between a gallium nitride (GaN) compound semiconductor layer and a metal layer in contact with the gallium nitride semiconductor layer. Specifically, the reaction between the metal-Ga and the metal-N occurs at the interface between the gallium nitride (GaN) compound semiconductor layer and the metal layer, which provides an intermediate diffusion barrier that may contribute to the selective adjustment of the reaction.

예를 들면, p형 전극의 경우에는, Metal-Ga의 반응은 안정적으로 일어나고 Metal-N의 반응은 억제시킬 수 있어야 하기 때문에, 이를 위하여 접촉층 위에, Metal-N의 활성화 에너지와, Metal-Ga의 활성화 에너지의 중단 단계의 양성 활성화 에너지를 갖는 중간 확산 장벽을 더 형성하는 것이다.For example, in the case of the p-type electrode, the reaction of Metal-Ga should occur stably and the reaction of Metal-N should be suppressed. It is to further form an intermediate diffusion barrier having a positive activation energy of the step of stopping the activation energy of.

한편, 상기 중간 확산 장벽과 상부 전극 금속층과의 반응이 거의 없도록 하여, 금속층과 질화갈륨(GaN)화합물 반도체층과의 계면에서 형성되는 음성 활성화 에너지를 전극층으로 충분히 발산할 수 있도록 설계되어야 한다.On the other hand, there should be little reaction between the intermediate diffusion barrier and the upper electrode metal layer, so that the negative activation energy formed at the interface between the metal layer and the gallium nitride (GaN) compound semiconductor layer to be sufficiently emitted to the electrode layer.

이하에서는 p형 전극의 경우를 예로 들어 본 발명의 오믹 전극 구조를 상세히 설명하도록 한다.Hereinafter, the ohmic electrode structure of the present invention will be described in detail with an example of a p-type electrode.

도 2는 본 발명에 따른 질화갈륨(GaN)화합물 반도체의 적층 구조를 설명하는도면이다2 is a view for explaining a laminated structure of a gallium nitride (GaN) compound semiconductor according to the present invention.

도 2를 참조하면, 질화갈륨(GaN)화합물 반도체층(11)과, 접촉층(12)과, 전극층(14)이 포함되고, 특히, 접촉층(12)과, 전극층(14)의 사이면에는 중간 확산 장벽층(13)이 더 형성되는 것을 알 수 있다. 상기 중간 확산 장벽층(13)은 열처리 시에 금속층과 질화갈륨(GaN)화합물 반도체층의 계면 반응을 억제할 수 있고, 또한, 금속층과 질화갈륨(GaN)화합물 반도체층의 계면에 형성되는 음성 활성화 에너지를 상부의 전극층으로 발산할 수 있는 특정의 물질이 단일 적층 또는 다중 적층되어 사용된다.Referring to FIG. 2, a gallium nitride (GaN) compound semiconductor layer 11, a contact layer 12, and an electrode layer 14 are included. In particular, an interfacial surface between the contact layer 12 and the electrode layer 14 is included. It can be seen that the intermediate diffusion barrier layer 13 is further formed on the substrate. The intermediate diffusion barrier layer 13 may suppress the interfacial reaction between the metal layer and the gallium nitride (GaN) compound semiconductor layer during heat treatment, and may also be negatively activated at the interface between the metal layer and the gallium nitride (GaN) compound semiconductor layer. Certain materials capable of dissipating energy to the upper electrode layer are used in single or multiple stacks.

예를 들면, 접촉층(12)이 금(Au), 전극층(14)이 니켓(Ni)인 경우에, 상기 중간 확산 장벽층(13)은 몰리브덴/텅스텐/몰리브덴(Mo/W/Mo)이 적층된 구조일 수 있다. 또한, 동일한 특성을 나타낼 수 있는 또 다른 금속은 Metal-Si, Metal-N, Cr, Pt, Ti, Ru등이 사용될 수도 있다. 한편, 상기 중간 확산 장벽층(13)의 두께는 각각의 층이 1~5,000nm으로 형성될 수 있다.For example, when the contact layer 12 is gold (Au) and the electrode layer 14 is nickel (Ni), the intermediate diffusion barrier layer 13 is formed of molybdenum / tungsten / molybdenum (Mo / W / Mo). It may be a stacked structure. In addition, as another metal that may exhibit the same properties, Metal-Si, Metal-N, Cr, Pt, Ti, Ru, or the like may be used. Meanwhile, the thickness of the intermediate diffusion barrier layer 13 may be formed in each layer of 1 ~ 5,000nm.

이하에서는 본 발명의 구체적인 실시예 및 비교례를 설명한다.Hereinafter, specific examples and comparative examples of the present invention will be described.

질화갈륨(GaN)화합물을 트리클로로에틸렌(TCE), 아세톤, 메탄올, 증류수로 각각 5분씩 세척한다. C-TLM(Circular-Transmission Line model) pattern을 사진식각술로 형성한다. 그리고, 금속 증착기 챔버에 상기 패턴을 장착한다.The gallium nitride (GaN) compound is washed with trichloroethylene (TCE), acetone, methanol and distilled water for 5 minutes each. C-TLM (Circular-Transmission Line model) pattern is formed by photolithography. The pattern is then mounted in a metal vapor deposition chamber.

상기 금속 증착기는 전자빔 증착기, 스퍼터, 이온빔 클러스터 증착기, CVD(Chemical Vapor Deposition), MBE(Molecular Beam Epitaxy), 자석을 이용한 증착기, 레이저를 이용한 증착기등 다양한 구성 및 양상의 증착기가 사용될 수 있다.The metal evaporator may be an evaporator, a sputter, an ion beam cluster evaporator, a chemical vapor deposition (CVD), a molecular beam epitaxy (MBE), an evaporator using a magnet, or an evaporator using a laser.

증착기에 상기 패턴이 놓인 뒤에는, 비교례로서, 질화갈륨(GaN)화합물의 상측에 금과, 니켈을 10-6Torr에서 각각 10nm증착한다.After the pattern is placed on the evaporator, as a comparative example, 10 nm of gold and nickel are deposited on the upper side of the gallium nitride (GaN) compound at 10 −6 Torr.

그리고, 본 발명의 실시예로서, 질화갈륨(GaN)화합물 반도체층(11)의 상측에 접촉층(12)으로서 금, 전극층(14)으로서 니켈을 각각 증착한다. 특히, 중간 확산 장벽층(13)으로는, 몰리브덴/텅스텐/몰리브덴(Mo/W/Mo)을 각각 10nm씩 증착한다.As an embodiment of the present invention, gold is deposited as the contact layer 12 and nickel as the electrode layer 14 on the gallium nitride (GaN) compound semiconductor layer 11, respectively. In particular, as the intermediate diffusion barrier layer 13, molybdenum / tungsten / molybdenum (Mo / W / Mo) is deposited by 10 nm each.

증착된 뒤에는 열처리를 행하여 질화갈륨(GaN) 반도체의 오믹 접촉이 달성되도록 한다.After deposition, heat treatment is performed to ensure that ohmic contact of the gallium nitride (GaN) semiconductor is achieved.

한편, C-TLM방법에 의해서 열처리 시간의 경과에 따른 비접촉 저항을 측정하여 도 3에 선도로 표시하였다. 이때 열처리를 수행하는 온도는 오믹 접촉을 달성하기 위한 온도로서 600℃의 환경이다.On the other hand, by the C-TLM method, the specific contact resistance with the passage of the heat treatment time was measured and shown as a diagram in FIG. At this time, the temperature to perform the heat treatment is an environment of 600 ℃ as a temperature for achieving ohmic contact.

도 3을 참조하면, 중간 확산 장벽층(도 2의 13참조)이 형성되지 않은 경우에는, 열처리 시간이 경과함에 따라 비접촉 저항값이 커지는 경향을 보이는 등 열적으로 불안정한 특성을 보인다(선도 32참조). 그러나, 본 발명에서와 같은 중간 확산 장벽층이 더 형성되는 경우에는 열처리 시간에 따른 비접촉저항값이 일정하게 측정되는 등, 열적 안정성이 매우 우수함을 알 수 있다(선도 31참조).Referring to FIG. 3, when the intermediate diffusion barrier layer (see 13 in FIG. 2) is not formed, thermally unstable characteristics such as the non-contact resistance value tend to increase as the heat treatment time passes (see FIG. 32). . However, when the intermediate diffusion barrier layer as in the present invention is further formed, it can be seen that the thermal stability is very excellent, such as the specific contact resistance value according to the heat treatment time is constantly measured (see FIG. 31).

나아가서, 상기 실시예 및 비교예에 있어서, 600℃의 온도에서 60분 동안 열처리를 계속해서 수행하여 전극의 표면상의 변화를 AFM(Atomic Force Microscope)을 이용하여 관찰하면, 비교예의 경우에는 전극의 표면이 거칠어져 추후의 공정에 영향을 미치게 되지만, 본 발명 실시예의 경우에는 표면이 매우 부드럽게 형성되어매우 우수한 표면 특성(Smooth Surface)을 가지는 것을 관찰할 수 있다. 상기된 양호한 표면 특성에 의해서 반도체 장치의 생산 수율을 향상시킬 수 있다.Further, in the above Examples and Comparative Examples, the heat treatment was continuously performed at a temperature of 600 ° C. for 60 minutes to observe the change on the surface of the electrode using AFM (Atomic Force Microscope). This roughness affects later processes, but in the case of the present invention, it can be observed that the surface is formed very smoothly and has very good smooth surface. The above-described good surface characteristics can improve the production yield of the semiconductor device.

이상에서 살펴본 바와 같이 반도체의 접촉층과, 전극층의 사이에 중간 확산 장벽층을 개재함으로써, 반도체의 우수한 열적, 전기적 안정성을 구현할 수 있다.As described above, by providing an intermediate diffusion barrier layer between the contact layer of the semiconductor and the electrode layer, excellent thermal and electrical stability of the semiconductor can be realized.

본 발명의 전극에 의해서, 질화갈륨(GaN)화합물 반도체의 접촉층과 전극층의 사이에 중간 확산 장벽을 더 형성함으로써, 금속과 반도체의 계면에서 일어나는 부적합한 계면 반응을 억제함으로써, 전극의 열적, 전기적은 특성을 향상시키고, 전극의 오믹 특성을 향상시킬 수 있는 효과가 있다.By the electrode of the present invention, an intermediate diffusion barrier is further formed between the contact layer of the gallium nitride (GaN) compound semiconductor and the electrode layer, thereby suppressing the unsuitable interfacial reaction occurring at the interface between the metal and the semiconductor, thereby providing thermal and electrical There is an effect that can improve the characteristics, and improve the ohmic characteristics of the electrode.

Claims (6)

질화갈륨(GaN)화합물 반도체의 상측에 형성되는 접촉층과,A contact layer formed on the upper side of the gallium nitride (GaN) compound semiconductor, 상기 접촉층 상면에 형성되는 중간확산장벽층과,An intermediate diffusion barrier layer formed on an upper surface of the contact layer; 상기 중간확산장벽층의 상면에 형성되는 전극층이 포함되는 것을 특징으로 하는 질화갈륨(GaN)화합물 반도체의 전극구조.An electrode structure of a gallium nitride (GaN) compound semiconductor, characterized in that it comprises an electrode layer formed on the upper surface of the intermediate diffusion barrier layer. 제 1 항에 있어서,The method of claim 1, 상기 중간확산장벽층은 P형 질화갈륨(GaN)화합물 반도체 상에 형성되는 것을 특징으로 하는 질화갈륨(GaN) 화합물 반도체의 전극구조.The intermediate diffusion barrier layer is formed on the P-type gallium nitride (GaN) compound semiconductor electrode structure of the gallium nitride (GaN) compound semiconductor. 제 1 항에 있어서,The method of claim 1, 상기 중간 확산 장벽은 Mo(몰리브덴)/W(텅스텐)/Mo(볼리브덴)의 순서로 적층되는 다중금속층인 것을 특징으로 하는 질화갈륨(GaN) 화합물 반도체의 전극 구조.The intermediate diffusion barrier is an electrode structure of a gallium nitride (GaN) compound semiconductor, characterized in that the multi-metal layer laminated in the order of Mo (molybdenum) / W (tungsten) / Mo (bolide). 제 1 항에 있어서,The method of claim 1, 상기 중간확산장벽층은 W(텅스텐) 및/또는 Mo(몰리브덴)이 증착되는 것을 특징으로 하는 질화갈륨(GaN) 화합물 반도체의 전극 구조.The intermediate diffusion barrier layer is an electrode structure of a gallium nitride (GaN) compound semiconductor, characterized in that W (tungsten) and / or Mo (molybdenum) is deposited. 질화갈륨(GaN) 화합물 반도체층 상면의 접촉층과, 상단 전극의 사이에, 금속과 질화갈륨 반도체 사이의 계면 반응 및 이온화 에너지를 조절하기 위하여, W(텅스텐), Mo(몰리브덴), Metal-Si(실리콘), Metal-N(질소), Cr(크롬), Pt(백금), Ti(티탄), Ru(루세늄)의 단일층, 또는 이층 이상의 조합으로 구성되어 열처리된 중간확산장벽층이 더 형성되는 것을 특징으로 하는 질화갈륨(GaN) 화합물 반도체의 전극 구조.W (tungsten), Mo (molybdenum), Metal-Si to control the interfacial reaction and ionization energy between the metal and gallium nitride semiconductor between the contact layer on the upper surface of the gallium nitride (GaN) compound semiconductor layer and the upper electrode The intermediate diffusion barrier layer, which is composed of a single layer of (silicon), metal-N (nitrogen), Cr (chromium), Pt (platinum), Ti (titanium), Ru (rucenium), or a combination of two or more layers, is further heat treated. An electrode structure of a gallium nitride (GaN) compound semiconductor, characterized in that formed. 제 5 항에 있어서,The method of claim 5, wherein 상기 중간 확산 장벽층은 전자빔 증착기, 스퍼터, 이온빔 클러스터 증착기, CVD(Chemical Vapor Deposition), MBE(Molecular Beam Epitaxy), 자석을 이용한 증착기, 레이저를 이용한 증착기중 하나에 의해서 형성되는 것을 특징으로 하는 질화갈륨(GaN) 화합물 반도체의 전극 구조.The intermediate diffusion barrier layer is formed of one of an electron beam evaporator, a sputter, an ion beam cluster evaporator, a chemical vapor deposition (CVD), a molecular beam epitaxy (MBE), an evaporator using a magnet, and an evaporator using a laser. Electrode structure of (GaN) compound semiconductor.
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