KR20040042430A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR20040042430A KR20040042430A KR1020020070729A KR20020070729A KR20040042430A KR 20040042430 A KR20040042430 A KR 20040042430A KR 1020020070729 A KR1020020070729 A KR 1020020070729A KR 20020070729 A KR20020070729 A KR 20020070729A KR 20040042430 A KR20040042430 A KR 20040042430A
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- film
- oxide film
- device isolation
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- 238000002955 isolation Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000005498 polishing Methods 0.000 claims abstract description 25
- 239000002002 slurry Substances 0.000 claims abstract description 16
- 239000004094 surface-active agent Substances 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 125000002915 carbonyl group Chemical group [*:2]C([*:1])=O 0.000 claims description 7
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는, 소자분리막 형성시 발생되는 기판과 소자분리막에 발생하는 데미지 및 디싱을 방지할 수 있는 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film capable of preventing damage and dishing occurring on a substrate and a device separation film generated when the device isolation film is formed.
반도체 소자의 고속화 및 고집적화가 급속하게 진행됨에 따라 패턴의 미세화 및 패턴 칫수의 고정밀화에 대한 요구가 점점 높아지고 있다. 이러한 요구는 소자 영역에 형성되는 패턴은 물론 상대적으로 넓은 영역을 차지하는 소자분리막에도 적용된다. 이것은 소자 영역의 폭이 감소되고 있는 추세에서 상대적으로 소자 영역의 폭을 증가시키기 위해서는 소자분리 영역의 폭을 감소시켜야만 하기 때문이다.As the speed and the high integration of semiconductor devices are rapidly progressing, there is an increasing demand for miniaturization of patterns and high precision of pattern dimensions. This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area. This is because the width of the device isolation region must be reduced in order to increase the width of the device region relatively in the trend that the width of the device region is decreasing.
여기서, 상기 소자분리막은 로코스(LOCOS) 공정에 의해 형성되어져 왔는데, 상기 로코스 공정에 의한 소자분리막은 그 가장자리 부분에서 새부리 형상의 버즈-빅(bird's-beak)이 발생되기 때문에 소자분리막의 면적을 증대시키면서 누설전류를 발생시키는 단점이 있다.Here, the device isolation film has been formed by a LOCOS process, and the device isolation film by the LOCOS process has an area of the device isolation film because bird's-beak having a beak shape is generated at an edge portion thereof. There is a disadvantage in that leakage current is generated while increasing.
따라서, 상기 로코스 공정 대신에 얕은 접합 소자분리(Shallow Trench Isolation : 이하, STI) 공정을 이용한 소자분리막 형성방법이 제안되었고, 현재 대부분의 반도체 소자는 상기 STI 공정을 적용해서 소자분리막을 형성하고 있으며, 이러한 STI 공정을 이용한 소자분리막 형성방법은 다음과 같이 진행된다.Accordingly, a method of forming a device isolation layer using a shallow trench isolation (STI) process has been proposed in place of the LOCOS process. Currently, most semiconductor devices form a device isolation layer by applying the STI process. The device isolation film forming method using the STI process proceeds as follows.
먼저, 기판 상에 패드산화막과 패드질화막을 차례로 증착하고, 이어서, 상기 막들을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시킨다.First, a pad oxide film and a pad nitride film are sequentially deposited on a substrate, and then the films are patterned to expose a substrate portion corresponding to an isolation region.
그런다음, 상기 노출된 기판 영역을 식각하여 소정 깊이의 트렌치들을 형성하고, 이어서, 상기 트렌치들을 매립하도록 기판의 전 영역 상에 트렌치 매립 산화막(이하, HDP 산화막)을 증착한다.Then, the exposed substrate region is etched to form trenches of a predetermined depth, and then a trench buried oxide film (hereinafter referred to as HDP oxide film) is deposited over the entire region of the substrate to fill the trenches.
다음으로, 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정에 따라 상기 패드질화막의 표면이 노출되도록 HDP 산화막을 연마하고, 이를 통해, 기판의 소자분리 영역에 트렌치형의 소자분리막들을 형성한다. 이후, 상기 패드질화막 및 패드 산화막을 제거한다.Next, the HDP oxide film is polished to expose the surface of the pad nitride film according to a chemical mechanical polishing (CMP) process, thereby forming trench isolation device isolation layers in the device isolation region of the substrate. Thereafter, the pad nitride film and the pad oxide film are removed.
그러나, 상기와 같은 소자분리막 형성방법은 상기 패드질화막과 HDP 산화막간의 연마선택비가 4:1이므로 소자분리막 형성시 패드질화막 상의 HDP 산화막을 완전히 제거하기 위하여 과도 연마를 하여야 한다.However, in the method of forming a device isolation film as described above, the polishing selectivity between the pad nitride film and the HDP oxide film is 4: 1, so that the polishing of the device isolation film requires excessive polishing to completely remove the HDP oxide film on the pad nitride film.
여기서, 상기 패드 질화막 상의 HDP 산화막을 완전히 제거하기 위한 과도 연마는, 도 1a에 도시된 바와 같이, 트렌치보다 큰 면적을 가진 액티브 영역에서는 양호한 형태의 소자분리막을 형성하지만, 도 1b 내지 1c에 도시된 바와 같이, 액티브 영역과 같은 면적을 가진 소자분리막 영역 및 액티브 영역보다 큰 면적을 가진 소자분리막 영역에서는 상기 소자분리막이 낮아지거나 기판 및 소자분리막에 데미지 (Damage)를 야기시켜 반도체 소자의 신뢰성을 감소시키게 된다.Here, the overpolishing for completely removing the HDP oxide film on the pad nitride film forms a device isolation film having a good shape in the active region having an area larger than the trench as shown in FIG. 1A, but is shown in FIGS. 1B to 1C. As described above, in the device isolation layer region having the same area as the active region and the device isolation region having a larger area than the active region, the device isolation layer may be lowered or damage may be caused to the substrate and the device isolation layer, thereby reducing the reliability of the semiconductor device. do.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 소자분리막 형성시 기판 및 소자분리막에 발생하는 데미지 및 디싱을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method of forming a device isolation film of a semiconductor device that can prevent damage and dishing occurring on the substrate and the device isolation film when forming the device isolation film, the object is have.
도 1a 내지 도 1c는 종래 기술에 따른 STI 공정에서의 소자분리막 형성방법을 설명하기 위한 사진.1A to 1C are photographs illustrating a method of forming an isolation layer in an STI process according to the prior art.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 STI 공정에서의 소자분리막 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming an isolation layer in an STI process according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 소자분리막을 도시한 사진.3 is a photo showing a device isolation film according to an embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
1 : 반도체 기판 3 : 패드질화막1 semiconductor substrate 3 pad nitride film
5 : 트렌치 7 : HDP 산화막5: trench 7: HDP oxide film
9 : 블로킹층(Blocking layer) 10 : 소자분리막9: blocking layer 10: device isolation layer
상기와 같은 목적을 달성하기 위한 본 발명의 방법은 반도체 기판 상에 질화막을 증착하는 단계와, 상기 질화막의 소정 부분을 식각하여 기판을 노출시키는 단계와, 상기 노출된 기판 부분을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 매립하도록 기판 결과물 상에 산화막을 증착하는 단계와, 상기 질화막이 노출되도록 상기 산화막을 화학적기계연마하여 소자분리막을 형성하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법에 있어서, 상기 산화막을 화학적기계연마하는 단계는 상기 질화막과 산화막간의 연마선택비를 증가시켜 상기 산화막 표면에서의 디싱 발생이 억제되도록 계면 활성제(surfactant)를 첨가한 슬러리를 사용하여 수행하는 것을 특징으로 한다.A method of the present invention for achieving the above object comprises the steps of depositing a nitride film on a semiconductor substrate, etching a predetermined portion of the nitride film to expose the substrate, and etching the exposed substrate portion to form a trench And depositing an oxide film on a substrate product to fill the trench, and chemically polishing the oxide film to expose the nitride film to form an isolation layer. The chemical mechanical polishing of the oxide film may be performed by using a slurry to which a surfactant is added to increase the polishing selectivity between the nitride film and the oxide film so that dishing on the surface of the oxide film is suppressed.
여기서, 상기 계면 활성제는 pH가 중성인 카르복실기 또는 카르보닐기이며, 이때, 상기 슬러리에 첨가되는 계면 활성제의 농도는 1wt% 이하 이다.Here, the surfactant is a carboxyl group or a carbonyl group having a neutral pH, wherein the concentration of the surfactant added to the slurry is 1 wt% or less.
또한, 상기 산화막을 화학적기계연마하는 단계는 3∼5 PSI의 압력에서 연마패드의 회전속도를 50∼70 RPM으로 하여 수행한다.In addition, the step of chemical mechanical polishing the oxide film is carried out at a rotational speed of 50 to 70 RPM of the polishing pad at a pressure of 3 to 5 PSI.
본 발명에 따르면, 슬러리와 함께 첨가된 카르복실기 또는 카르보닐기는 질화막과의 결합으로 블로킹층을 형성해서 질화막과 산화막간의 연마선택비를 증가시키므로, 소자분리막 형성시 기판 또는 상기 소자분리막에 발생하는 데미지와 디싱을 방지할 수 있다.According to the present invention, the carboxyl group or the carbonyl group added together with the slurry forms a blocking layer by bonding with the nitride film, thereby increasing the polishing selectivity between the nitride film and the oxide film. Can be prevented.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 STI 공정에서의 소자분리막 형성방법을 설명하기 위한 공정별 단면도이다.2A through 2C are cross-sectional views illustrating processes of forming an isolation layer in an STI process according to an exemplary embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 액티브 영역보다 소자분리 영역이 큰 지역, 액티브 영역과 소자분리막 영역이 같은 지역 및 액티브 영역보다 소자분리 영역이 작은 지역이 구획된 반도체 기판(1) 상에 패드산화막(도시안됨)과 패드질화막 (3)을 차례로 증착하고, 이어서, 상기 막들을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시킨다.First, as shown in FIG. 2A, a pad is formed on a semiconductor substrate 1 in which a region having a larger device isolation region than an active region, a region having the same active region and a device isolation layer region, and a region having a smaller device isolation region than the active region are partitioned. An oxide film (not shown) and a pad nitride film 3 are sequentially deposited, and then the films are patterned to expose the substrate portion corresponding to the device isolation region.
그런다음, 상기 노출된 기판(1) 영역을 식각하여 소정 깊이의 트렌치(5)들을 형성하고, 이어서, 상기 트렌치(5)들을 매립하도록 기판(1)의 전 영역 상에 HDP 산화막(7)을 증착한다.Then, the exposed regions of the substrate 1 are etched to form trenches 5 of a predetermined depth, and then the HDP oxide film 7 is deposited on the entire region of the substrate 1 to fill the trenches 5. Deposit.
다음으로, 도 2b에 도시된 바와 같이, 상기 기판 결과물에 슬러리와 함께 계면 활성제(Surfactant)을 첨가하여 패드질화막 표면에 블로킹층(Blocking layer) (9)을 형성한다. 이때, 상기 계면 활성제는 pH가 중성이면서 C＝＜ 의 화학구조를 가진 카르보닐기 또는 RCOOH의 화학구조를 가진 카르복실기이다. 여기서, 상기 슬러리에 첨가되는 계면 활성제의 농도는 1wt% 이하이며, 이때, 상기 슬러리와 계면 활성제는 1시간 동안 충분히 교반(Stirring) 되는 것이 바람직하다.Next, as shown in FIG. 2B, a surfactant (Surfactant) is added to the substrate resultant together with the slurry to form a blocking layer 9 on the pad nitride film surface. In this case, the surfactant is a carbonyl group having a chemical structure of C = <or a carboxyl group having a chemical structure of RCOOH while having a neutral pH. Here, the concentration of the surfactant added to the slurry is 1wt% or less, wherein the slurry and the surfactant is preferably sufficiently stirred for 1 hour (Stirring).
여기서, 상기 카르보닐기와 카르복실기는 제타 포텐셜(Zeta potential)값, 즉, -30∼-50㎷의 마이너스(－) 챠지 값을 가지고 있기 때문에 플러스(＋) 챠지값을 가진 HDP 산화막(7)과는 결합하지 않고, 마이너스(－) 챠지값을 가진 패드질화막(3)과 결합한다.Here, since the carbonyl group and the carboxyl group have a zeta potential value, that is, a negative charge value of −30 to −50 μs, the carbonyl group and the carboxyl group are combined with the HDP oxide film 7 having a positive charge value. Instead, it combines with the pad nitride film 3 having a negative charge value.
또한, 상기 블로킹층(9)은 패드질화막(3)과 HDP 산화막(7)간의 연마 선택비는 종래의 4:1에서 100:1 정도로 증가시킨다.In addition, the blocking layer 9 increases the polishing selectivity between the pad nitride film 3 and the HDP oxide film 7 from about 4: 1 to about 100: 1.
한편, 상기 HDP 산화막(7)을 연마할 경우에 상기 슬러리는 실리카(Silica) 계열 혹은 세리아(Ceria) 계열의 입자를 가진 슬러리를 사용하는 것이 연마율 및후속의 소자분리막의 디싱(Dishing) 측면에서 유리한다.On the other hand, when polishing the HDP oxide film (7), the slurry is a slurry having a silica or Ceria particles in terms of polishing rate and subsequent dishing of the device isolation film. Advantageous.
이때, 상기 HDP 산화막을 연마할때의 연마율을 고려하여 실리카 계열의 슬러리의 농도는 10wt% 이상, 그리고, 세리아 계열의 슬러리의 농도는 1wt%∼3wt%로 조종하는 것이 바람직하다.At this time, in consideration of the polishing rate when polishing the HDP oxide film, the concentration of the silica-based slurry is preferably 10wt% or more, and the concentration of the ceria-based slurry is preferably controlled to 1wt% to 3wt%.
또한, 상기 카르보닐기 또는 카르복실기와 함께 첨가되는 슬러리로서 실리카 계열 보다는 후속의 소자분리막의 폭 보다 입자가 큰 세리아 계열의 슬러리를 사용하는 것이 유리하다.In addition, it is advantageous to use a ceria-based slurry having larger particles than the width of a subsequent device separation membrane as a slurry added together with the carbonyl group or carboxyl group.
그런 다음, 도 2c에 도시된 바와 같이, 상기 패드질화막(3)의 표면이 노출되도록 3∼5 PSI의 압력조건에서 연마패드의 회전속도를 50∼70 RPM으로 하여 상기 HDP 산화막을 연마하고, 이를 통해, 기판(1)의 소자분리 영역에 트렌치형의 소자분리막(10)들을 형성한다.Then, as shown in FIG. 2C, the HDP oxide film is polished at a rotational speed of 50 to 70 RPM at a pressure of 3 to 5 PSI so that the surface of the pad nitride film 3 is exposed. The trench isolation device isolation layers 10 are formed in the device isolation region of the substrate 1.
여기서, 5 PSI 이상의 압력 조건에서 상기 HDP 산화막을 연마할 경우에는 패드질화막(3) 표면의 블로킹층의 결합이 파괴되어 상기 HDP 산화막과 패드질화막(3)간에 원하는 연마선택비를 얻을 수 없게된다.When the HDP oxide film is polished under a pressure condition of 5 PSI or more, the bonding of the blocking layer on the surface of the pad nitride film 3 is broken so that a desired polishing selectivity cannot be obtained between the HDP oxide film and the pad nitride film 3.
본 발명에 따르면, 상기 패드질화막(3) 표면에 블로킹층을 형성하여 패드질화막(3)과 HDP 산화막간의 연마선택비를 종래의 그것과 비교하여 현저하게 증가시킬 수 있다.According to the present invention, by forming a blocking layer on the surface of the pad nitride film 3, the polishing selectivity between the pad nitride film 3 and the HDP oxide film can be significantly increased as compared with the conventional one.
따라서, 상기 HDP 산화막을 CMP하여 소자분리막을 형성할때 질화막 상의 잔류된 산화막을 완전히 제거하기 위한 과도 연마를 생략할 수 있으며, 이를 통해, 도 3에 도시된 바와 같이, 액티브 영역보다 소자분리 영역이 작은 지역뿐만 아니라액티브 영역과 소자분리막 영역이 같은 지역 및 액티브 영역보다 소자분리 영역이 큰 지역에서도 상기 소자분리막과 기판에 발생하는 데미지와 디싱을 방지할 수 있다.Therefore, when the device isolation film is formed by CMP of the HDP oxide film, the excessive polishing to completely remove the remaining oxide film on the nitride film can be omitted. As a result, as shown in FIG. Damage and dishing to the device isolation layer and the substrate can be prevented not only in a small area but also in an area in which the active area and the device isolation layer area are the same and in an area in which the device isolation area is larger than the active area.
이후, 도시하지는 않았지만, 상기 패터닝된 패드질화막(3) 및 패드산화막(도시안됨)을 제거한다.Subsequently, although not shown, the patterned pad nitride film 3 and the pad oxide film (not shown) are removed.
이상에서와 같이, 본 발명의 소자분리막 형성방법은 패드질화막과 HDP 산화막간의 연마선택비를 종래의 그것과 비교하여 현저하게 증가시키므로, 이를 통해, 소자분리막 형성시 발생되는 기판과 소자분리막에 발생하는 데미지 및 디싱을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있다.As described above, the method for forming a device isolation film of the present invention significantly increases the polishing selectivity between the pad nitride film and the HDP oxide film, as compared with the conventional one. Damage and dishing can be prevented to improve the reliability of the semiconductor device.
한편, 전술한 본 발명의 실시예는 예시의 목적을 위해 개시된 것이므로, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경 및 부가 등이 가능할 것이며, 따라서, 이러한 수정 및 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.On the other hand, since the embodiments of the present invention described above are for the purpose of illustration, various modifications, changes, and additions will be possible to those skilled in the art within the spirit and scope of the present invention, and therefore, such modifications and changes are claimed It should be seen as belonging to a range.
Claims (4)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000025637A (en) * | 1998-10-13 | 2000-05-06 | 김영환 | Method for manufacturing device isolation layer using chemical and mechanical planarization |
| KR20010041248A (en) * | 1998-02-24 | 2001-05-15 | 오하시 미츠오 | Abrasive composition for polishing semiconductor device and process for producing semiconductor device with the same |
| KR20030002479A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Nitride CMP Slurry having Selectivity to Oxide |
| KR20030089360A (en) * | 2002-05-17 | 2003-11-21 | 주식회사 하이닉스반도체 | CMP Slurry for Oxide and Formation Method of Semiconductor Device Using the Same |
| KR20030089362A (en) * | 2002-05-17 | 2003-11-21 | 주식회사 하이닉스반도체 | Formation Method of Flash Memory Device |
-
2002
- 2002-11-14 KR KR1020020070729A patent/KR20040042430A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010041248A (en) * | 1998-02-24 | 2001-05-15 | 오하시 미츠오 | Abrasive composition for polishing semiconductor device and process for producing semiconductor device with the same |
| KR20000025637A (en) * | 1998-10-13 | 2000-05-06 | 김영환 | Method for manufacturing device isolation layer using chemical and mechanical planarization |
| KR20030002479A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Nitride CMP Slurry having Selectivity to Oxide |
| KR20030089360A (en) * | 2002-05-17 | 2003-11-21 | 주식회사 하이닉스반도체 | CMP Slurry for Oxide and Formation Method of Semiconductor Device Using the Same |
| KR20030089362A (en) * | 2002-05-17 | 2003-11-21 | 주식회사 하이닉스반도체 | Formation Method of Flash Memory Device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100800481B1 (en) * | 2006-08-16 | 2008-02-04 | 삼성전자주식회사 | Chemical mechanical polishing method and a method of forming isolation layer comprising the polishing method |
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