KR20040041291A - Flat panel display device - Google Patents

Abstract

PURPOSE: A flat panel display apparatus is provided to reduce a PCB(Printed Circuit Board) area of the bottom surface of the flat panel display apparatus and the number of parts. CONSTITUTION: A liquid crystal panel(305) includes an array substrate, a color filter substrate corresponding to the array substrate, and a liquid crystal layer, thereby displaying an image. For displaying the image, the liquid crystal panel(305) receives a scan signal from a drive PCB(330) and image signals from first and second data drive PCB(340). The data drive PCB(340)s are connected to a data line terminal unit of a pixel array of the liquid crystal panel(305) through a film cable having a drive chip formed by a COF(Chip On Film) method.

Description

Flat Panel Display {FLAT PANEL DISPLAY DEVICE}

The present invention relates to a flat panel display device, and more particularly, to a flat panel display device suitable for a large screen and a high resolution.

In general, a liquid crystal display includes a liquid crystal panel for displaying an image using a liquid crystal layer filled between two substrates, and a data driver disposed on one side of the liquid crystal panel to transmit an image signal to the liquid crystal panel. And a gate driver disposed on the other side of the liquid crystal panel to select the image signal.

In recent years, flat panel display devices require a large screen and high resolution. However, as the large screen and the high resolution progress, the load of the data line and the gate line included in the flat panel display panel increases, so that a data driver and a gate driver are employed on one side and the other side of the liquid crystal panel to satisfy the requirements of the large screen and high resolution. There is a disadvantage that can not be.

In order to solve this disadvantage, a method of arranging and driving gate drivers on both sides of the gate lines provided in the liquid crystal panel (hereinafter referred to as dual gate driving) or adopting and driving data drivers on both sides of the data lines provided in the liquid crystal panel is driven. The following method (hereinafter referred to as dual data drive) is adopted.

However, the dual data driving requires 48 data lines, and because of the characteristics of the data drive IC requiring 10 or more gamma reference voltages, the number of components for driving increases, and the area of the PCB increases. have. For example, the problem can be confirmed in a liquid crystal display having a resolution of 2048 × 2048 × 3.

FIG. 1 is a diagram for describing a general flat panel display, and particularly illustrates a rear surface of a liquid crystal display.

Referring to FIG. 1, the liquid crystal display 100 may include a liquid crystal panel 105, a control PCB 110, a plurality of film cables 121, 122, 123, 124, 125, 126, 127, 128, and 129. The first data driving PCB 130, the second data driving PCB 140, the gate driving PCB 150, and the first to fourth inverters 130, 140, 150, and 160 are included.

The liquid crystal panel 105 is filled with an array substrate having a pixel array composed of a plurality of data lines and a gate line orthogonal to the data lines, a color filter substrate facing the array substrate, and filled between the array substrate and the color filter substrate. The image is displayed including the liquid crystal layer. At this time, a scan signal is provided from the gate driving PCB 150 to display the image, and an image signal is provided from the first and second data driving PCBs 130 and 140.

The control PCB 110 receives a video input signal provided from an external graphic controller (not shown) via the video input cable 111 and the connector 112, and then connects the plurality of film cables 121 connected to the first data driving PCB. The first data driving PCB 130 is provided with a power for driving the first data signal through the first, second, second, second, second, second, second, second, second, second, second, second, second, second, second, second, second, second, third, fifth and third terms. In addition, the control PCB 110 supplies a power for driving the signal for the first data through the plurality of film cables 125, 126, 127, and 128 connected to the second data driving PCB 140. ) And a gate signal and power for driving the gate driving PCB 150 through the film cable 129 connected to the gate driving PCB 330. At this time, the video input signal has a data transmission rate of about 140M to 280Mbit / sec, as shown in Figure 2, LVDS (Low Voltage Differential Signaling) that can improve the EMI and signal interference problems by reducing the conversion width of the data voltage Can be delivered using an interface.

As shown in FIG. 2, the LVDS interface includes a first CMOS inverter 10 including a first transistor M1 and a second transistor M2, and a third transistor M3 and a fourth transistor M4. Comprising a second CMOS inverter 20 and a terminating resistor unit 30, one input signal D0 is divided into two output signals OUT1 and OUT2, and the divided output signal is divided into a video input cable 111. Output to For example, as the high level input signal is input, the N-type first transistor M1 is turned on, the P-type second transistor M2 is turned off, and the P-type third transistor ( Since the M3 is turned off and the N-type fourth transistor M4 is turned on, the first differential output signal OUT1 having a high level and the second differential output signal OUT2 having a low level are output.

Referring to FIG. 1, the gate driving PCB 150 is connected to a gate line terminal portion of a pixel array of the liquid crystal panel 105 through a film cable, so that the scan signal for sequentially selecting a gate line is supplied to the liquid crystal panel 105. Output sequentially. The first data driving PCB 130 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 105 through a plurality of film cables, and outputs a first image signal to the data line based on the first data signal. do. The second data driving PCB 140 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 105 through a plurality of film cables, and outputs a second image signal to the data line based on the second data signal. do.

As described above, a general liquid crystal display device may be driven by adopting a single gate driving method because the screen has a square shape. However, as the resolution gradually increases, the length of the data line becomes longer, thereby adopting a dual data driving method.

However, under the above-described structure, since one PCB covers almost most of the rear surface of the liquid crystal panel, it is difficult to mount another board such as an inverter, and thus there is a problem that many restrictions occur in design.

In addition, since the image data and the gamma voltage must be supplied to each of the upper data driver and the lower data driver, the number of parts increases and power consumption also increases.

Accordingly, the present invention has been made in an effort to solve such a conventional problem, and an object of the present invention is to provide a flat panel display device for reducing the number of parts while reducing the PCB area employed on the rear surface of the flat panel display panel.

1 is a diagram for describing a general flat panel display.

2 is a diagram illustrating a general LVDS interface.

3 is a view for explaining the structure of a flat panel display device according to an embodiment of the present invention.

4 is a diagram for describing the structure of a flat panel display device according to another exemplary embodiment.

5 is a view for explaining an LVDS interface according to the present invention.

6 is a view for explaining the structure of a flat panel display device according to still another embodiment of the present invention.

FIG. 7A is a diagram for describing a structure of a flat panel display device according to another exemplary embodiment. FIG. 7B is a diagram for describing a master-slave driving method.

8 is a diagram for describing a structure of a flat panel display device according to still another exemplary embodiment of the present invention.

9 is a diagram for describing a structure of a flat panel display device according to another exemplary embodiment of the present invention.

10 is a view for explaining the structure of a flat panel display device according to another exemplary embodiment of the present invention.

11 is a diagram for describing a structure of a flat panel display device according to still another embodiment of the present invention.

12 is a diagram for describing a structure of a flat panel display device according to still another embodiment of the present invention.

According to a first aspect of the present invention, there is provided a flat panel display device comprising: a flat panel display panel; Data driving PCBs respectively formed on upper and lower sides of the flat panel display panel and providing a data signal to the flat panel panel; Scan driving PCBs respectively formed at left and right sides of the flat panel display panel and providing scan signals to the flat panel display panel; And a timing control circuit configured to receive and process an input signal from an external source and generate a driving signal to generate an image signal to be supplied to the flat panel display panel, and to convert some of the generated driving signals into the data driving PCB and the gate driving PCB. And a control PCB for transmitting to the rear surface of the flat panel display panel, wherein the control PCB has a substantially H shape.

In addition, a flat panel display device according to a second aspect for realizing the above object of the present invention includes a flat panel display panel; A first control PCB to output a first data signal and a first scan signal based on a first video input signal input through the first connector; A second control PCB configured to output a second data signal and a first scan signal based on a second video input signal input through the second connector; A gate driving PCB generating a first scan signal based on the first scan signal and outputting the generated first scan signal to the flat panel display panel; A first data driving PCB generating a first data signal based on the first data signal and outputting the generated first data signal to the flat panel display panel; And a second data driving PCB generating a second data signal based on the second data signal and outputting the generated second data signal to the flat panel display panel.

Further, a flat panel display device according to a third aspect for realizing the above object of the present invention includes a flat panel display panel; A control PCB which receives a video input signal through a connector and outputs a signal for master data, a signal for scanning, and a signal for slave data; A master data driving PCB configured to output a first image signal to one side of the flat panel display panel based on the master data signal; A gate driving PCB configured to output a scan signal to the flat panel display panel based on the scan signal; And a slave data driving PCB outputting a second image signal for compensating the first image signal to the other side of the flat panel display panel based on the slave data signal.

Further, a flat panel display device according to a fourth aspect for realizing the above object of the present invention includes a flat panel display panel; A control PCB which receives a video input signal through a connector and outputs signals for first and second master data, signals for first and second scans, and signals for first and second slave data; A first master data driving PCB for outputting a first image signal to the flat panel display panel based on the first master data signal and transferring the first scan signal and the first slave data signal; A second master data driving PCB for outputting a second image signal to the flat panel display panel based on the second master data signal and transferring the second scan signal and the second slave data signal; A first gate driving PCB configured to output a first gate signal to the flat panel display panel based on the first scan signal, and to transmit the first slave data signal; A second gate driving PCB configured to output a second gate signal to the flat panel display panel based on the second scan signal, and to transmit the second slave data signal; A first slave data driving PCB outputting a third image signal for compensating the first image signal to the flat panel display panel based on the first slave data signal; And a second slave data driving PCB configured to output a fourth image signal to the flat panel display panel to compensate for the second image signal based on the second slave data signal.

According to such a flat panel display device, the number of parts can be reduced while reducing the PCB area employed on the rear surface of the flat panel display panel for a large screen and high resolution.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

3 is a view for explaining the structure of a flat panel display device according to an embodiment of the present invention. In particular, FIG.

Referring to FIG. 3, the liquid crystal display 200 according to an exemplary embodiment of the present invention may include a liquid crystal panel 205, a control PCB 210, a plurality of film cables 220, 221, 222, 223, 224, 225, 226, 227, 228, and 229, upper first data driving PCB 230, upper second data driving PCB 235, lower first data driving PCB 240, lower second data driving PCB 245, and first gate. The driving PCB 250, the second gate driving PCB 255, and the first to fifth inverters 260, 265, 270, 275, and 280 are included.

The control PCB 210 is disposed on the rear surface of the liquid crystal panel 205, and receives a video input signal provided from an external graphic controller (not shown) via the video input cable 207 and the connector 209 and a film cable. The first data signal and the power supply for driving the upper first data driving PCB 230 are supplied to the upper first data driving PCB 230 through the 220 and 221, and the film cables 222 and 223 are provided. The second data signal and power for driving the upper second data driving PCB 235 are provided to the upper second data driving PCB 235 through the second data signal.

In addition, the control PCB 210 provides power for driving the lower first data driving PCB 240 and the third data signal through the film cables 224 and 225 to the lower first data driving PCB 240. The power supply for driving the fourth data signal and the lower second data driving PCB 245 is provided to the lower second data driving PCB 245 through the film cables 226 and 227. In addition, the control PCB 210 provides a signal for the first gate and power for driving the first gate driving PCB 250 to the first gate driving PCB 250 through the film cable 228, and the film cable A signal for the second gate and power for driving the second gate driving PCB 255 are provided to the second gate driving PCB 255 through 229.

The upper first data driving PCB 230 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a data driving chip formed by a COF (CHIP ON FILM) method, and by the power supply. It is activated, and outputs a first image signal to the data line based on the first data signal. In this case, the output first image signal is an image signal corresponding to 1/2 of a left data line among the data lines included in the virtually left and right pixel arrays.

The upper second data driving PCB 235 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a data driving chip formed in a COF manner, and is activated by the power supply. The second image signal is output to the data line based on the data signal. In this case, the second image signal output is an image signal corresponding to 1/2 of the right data line among the data lines included in the virtually left and right pixel arrays.

The lower first data driving PCB 240 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a data driving chip formed in a COF manner, and is activated by the power supply. A third image signal is output to the data line based on the three data signals. In this case, the output third image signal is an image signal corresponding to the remaining half of the left data line among the data lines included in the virtually left and right pixel arrays.

The lower second data driving PCB 245 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a data driving chip formed in a COF manner, and is activated by the power supply. Fourth image signal is output to the data line based on the data signal. In this case, the output fourth image signal is an image signal corresponding to the other half of the right data line among the data lines included in the virtually divided pixel array.

The first gate driving PCB 250 is connected to the gate line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a gate driving chip formed in a COF manner, and is activated by the power supply. The first scan signal is output to the gate line based on the gate signal. In this case, the output first scan signal is applied to the left gate line among the gate lines included in the virtually divided pixel array.

The second gate driving PCB 255 is connected to the gate line terminal portion of the pixel array of the liquid crystal panel 205 through a plurality of film cables having a gate driving chip formed in a COF manner, and is activated by the power source. The second scan signal is output to the gate line based on the gate signal. In this case, the output second scan signal is applied to the right gate line among the gate lines included in the virtually right and left pixel arrays.

The first to fifth inverters 260, 265, 270, 275, and 280 are disposed on the rear surface of the liquid crystal panel 205. In particular, the upper first and second data drives without the control PCB 210 are disposed. When the PCBs 230 and 235 and the lower first and second data driving PCBs 240 and 245 are folded and disposed on the rear surface of the liquid crystal panel 205, the PCBs 230 and 235 may be disposed in areas not overlapped with each other.

In the above, it has been described that one gate driving PCB is disposed on both the left and right sides of the liquid crystal panel for dual gate driving and the dual data driving, and two data driving PCBs are disposed on the upper and lower sides of the liquid crystal panel, respectively. However, those skilled in the art may arrange one gate driving PCB on both left and right sides of the liquid crystal panel and dual data driving PCBs on the upper and lower sides of the liquid crystal panel for dual gate driving and dual data driving.

4 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, FIG. 4 illustrates a rear structure of a liquid crystal display device employing an LVDS method and having a single gate-dual data driving method. to be.

Referring to FIG. 4, the liquid crystal display 300 according to another exemplary embodiment of the present invention may include a liquid crystal panel 305, a first control PCB 310, a second control PCB 320, a gate driving PCB 330, The first data driving PCB 340, the second data driving PCB 350, and the first to fourth inverters 360, 370, 380, and 390 are included. For convenience of description, the components disposed on the rear surface of the liquid crystal panel 305 and the components disposed on the front surface are illustrated on the same plane.

The liquid crystal panel 305 includes an array substrate having a plurality of data lines, a gate line orthogonal to the data lines, and a pixel array composed of switching elements connected between the data lines and the gate lines, a color filter substrate facing the array substrate; And a liquid crystal layer filled between the array substrate and the color filter substrate to display an image. In this case, a scan signal is provided from the gate driving PCB 330 to display the image, and an image signal is provided from the first and second data driving PCB 340.

The first control PCB 310 is disposed on the rear surface of the liquid crystal panel 305 so that the first video input signal provided from an external graphic controller (not shown) may be provided to the first video input cable 311 and the first connector 312. The first data driving PCB is supplied via the first to fourth film cables 313, 314, 315, and 316 to supply power for driving the first data signal and the first data driving PCB 340. And a power for driving the gate driving PCB and a signal for the first gate through the fifth film cable 317.

The second control PCB 320 receives the second video input signal provided from an external graphic controller (not shown) via the second video input cable 321 and the second connector 322. Through the film cables 323, 324, 325, and 326, a signal for the second data and a power for driving the second data driving PCB 350 are provided to the second data driving PCB 350.

The gate driving PCB 330 is connected to the gate line terminal portion of the pixel array of the liquid crystal panel 305 through a film cable having a gate driving chip formed in a COF manner, and is activated by the power supply and receives the signal for the first gate. As a result, scan signals for sequentially selecting the gate lines are sequentially output to the liquid crystal panel 305.

The first data driving PCB 340 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 305 through a film cable having a data driving chip formed in a COF manner, and is activated by the power supply. The first image signal is output to the data line based on the signal.

The second data driving PCB 350 is connected to the data line terminal portion of the pixel array of the liquid crystal panel 305 through a film cable having a data driving chip formed by a COF (CHIP ON FILM) method, and is activated by the power supply. The second image signal is output to a plurality of data lines provided in the liquid crystal panel 305 based on the second data signal.

The first to fourth inverters 360, 370, 380, and 390 are disposed on the rear surface of the liquid crystal panel 305. In particular, an area not overlapped when the first and second data driving PCBs 340 and 350 are folded and disposed on the rear surface of the liquid crystal panel 305 without the first and second control PCBs 310 and 320 being disposed. It is preferably arranged in.

As described above, by dividing the control PCB into two to receive two LVDS inputs, the area occupied by the PCB can be reduced, and the overall area of the PCB can be reduced, thereby reducing manufacturing costs.

In addition, since the position of the inverter for supplying power to drive the liquid crystal display device may be arranged in various ways such as horizontal arrangement, vertical arrangement, and zigzag arrangement using an area where no PCB is arranged, the width of the design may be widened.

FIG. 5 is a diagram for explaining an LVDS interface according to the present invention. In particular, FIG. 5 is a diagram for explaining a split output of two LVDS signals.

Referring to FIG. 5, the LVDS interface according to the present invention includes a first CMOS inverter 40 including a first transistor M1 and a second transistor M2, a third transistor M3, and a fourth transistor M4. And a second CMOS inverter 50, a first termination resistor portion 60, and a second termination resistor portion 70, and convert one input signal D0 into two differential output signals OUT1 and OUT2. And outputs the divided differential output signal to the first video input cable 311 connected to the first output port PORT1 and to the second video input cable 321 connected to the second output port PORT2. do. In this case, the signals output through the first and second output ports PORT1 and PORT2 are summarized in Table 1 below.

D0 OUT1 OUT2 PORT1 PORT2 OUT1 OUT2 OUT1 OUT2 H H L H L H L L L H L H L H

In the above, the control PCB is divided into two by receiving two LVDS inputs in the liquid crystal display having the single gate-dual data driving method. 6 may be applied to a liquid crystal display having a dual gate-dual data driving scheme while employing the LVDS scheme.

FIG. 6 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, FIG. 6 illustrates a rear structure of a liquid crystal display device employing an LVDS method and having dual gate-dual data driving. to be.

Referring to FIG. 6, the liquid crystal display device 400 includes a liquid crystal display panel 405, a first control PCB 410, a second control PCB 420, an upper first data driving PCB 430, and an upper second data. The driving PCB 435, the lower first data driving PCB 440, the lower second data driving PCB 445, the first gate driving PCB 450, the second gate driving PCB 460, and the first to fifth inverters. (470, 475, 480, 485, 490). For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 405 and the components disposed on the front surface are illustrated on the same plane.

The first control PCB 410 is disposed on the rear surface of the liquid crystal display panel 405 and receives a first video input signal provided from an external graphic controller via the first video input cable 411 and the first connector 412. The first data signal and the power for driving the upper first data driving PCB 430 to the upper first data driving PCB 430 through the first and second film cables 413 and 414. The second data driving PCB 435 is provided with a power supply for driving the second data signal and the upper second data driving PCB 435 through the third and fourth film cables 415 and 416. . In this case, the first and second data signals are signals corresponding to the upper, left, and right regions of the liquid crystal panel in four equally divided states.

The second control PCB 420 is disposed on the rear surface of the liquid crystal display panel 405 so that a second video input signal provided from an external graphic controller is passed through the second video input cable 421 and the twenty-first connector 422. And a third data signal and power for driving the lower first data driving PCB 440 through the fifth and sixth film cables 423 and 424 to the lower first data driving PCB 440. The fourth data signal and the power supply for driving the lower second data driving PCB 445 are provided to the lower second data driving PCB 445 through the seventh and eighth film cables 425 and 426. . In this case, the third and fourth data signals are signals corresponding to each of the lower left and right regions in the four equally divided state of the liquid crystal display panel.

The upper first data driving PCB 430 and the upper second data driving PCB 435 receive the first and second data signals and respective power supplies to provide a data signal to an upper region of the liquid crystal display panel 405. In this case, the upper first data driving PCB 430 transmits a signal for the first gate provided from the first control PCB 410 to the first gate driving PCB 450 through the ninth film cable 432, and the upper first driving data. The second data driving PCB 435 transmits a signal for the first gate provided from the first control PCB 410 to the first gate driving PCB 450 through the tenth film cable 437.

In addition, the lower first data driving PCB 440 and the lower second data driving PCB 445 are provided with the third and fourth data signals and respective power supplies to supply data signals to the lower region of the liquid crystal display panel 405. to provide.

Meanwhile, the first gate driving PCB 450 may include a gate line of the gate line provided in the liquid crystal display panel based on a signal for the first gate transmitted from the upper first data driving PCB 430 via the ninth film cable 432. The scan signal is transmitted to one side, and the second gate driving PCB 460 is a liquid crystal display panel based on a signal for the second gate transmitted from the upper second data driving PCB 435 via the tenth film cable 437. The scan signal is transmitted to the other side of the gate line.

As explained above, applying two LVDS inputs and dividing the control PCB into two parts eliminates the components and power required for long distance transmission, and sends signals and power to the gate through the data PCB. PCB lengths can also be significantly reduced.

In addition, signals and power transmitted to the gate drive IC may be transmitted through the metal wiring of the panel. The application of this technique also eliminates film cables. In addition, the significant reduction in PCB area allows greater freedom of placement of the inverter.

In addition, by driving the liquid crystal display with two control PCBs by receiving two LVDS input signals, the total area occupied by the PCB can be greatly reduced, thereby reducing manufacturing costs.

In addition, the area of the control PCB can be reduced, allowing more flexibility in the placement of other circuit boards, such as inverters or A / D boards.

In addition, a signal cable for driving the gate drive IC and a film cable for transmitting power can be connected through the data PCB.

FIG. 7A illustrates a structure of a flat panel display device according to still another embodiment. In particular, FIG. 7A illustrates a rear structure of a liquid crystal display device employing a master-slave method and each having a data PCB and a gate PCB. 7B is a diagram for explaining a master-slave driving method.

7A and 7B, the liquid crystal display 510 may include a liquid crystal display panel 5105, a control PCB 5110, a master data drive PCB 5120, a gate drive PCB 5130, and a slave data drive PCB ( 5140 and first to fourth inverters 5150, 5160, 5170, and 5180. For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 5105 and the components disposed on the front surface are illustrated on the same plane.

The control PCB 5110 is disposed on the rear surface of the liquid crystal display panel 5105, and receives a video input signal provided from an external graphic controller (not shown) via the video input cable 5107 and the connector 5109, and receives a film. Signals for master data and signals for slave data are received through the cables 5111, 5112, 5113, and 5114 and provided to the master data driving PCB 5120. The master data signal is typically a signal applied to a data driving PCB, and the slave data signal is a slave IC power supply provided to the slave data driving PCB, a slave on / off control signal, and a polarity signal. It includes.

The master data driving PCB 5120 supplies the data signal to one side of the data line of the liquid crystal display panel 5106 as shown in FIG. 7B based on the master data signal provided from the control PCB 5110. The Eve data signal is transmitted to the liquid crystal display panel 5105 through a separately provided film cable 5122. In this case, an outer side of the liquid crystal display panel 5106 has a separate transmission line for transmitting the slave data signal.

The gate driving PCB 5130 is connected to the control PCB 5110 through the film cable 5115 to scan the signal to one side of the gate line provided in the liquid crystal display panel based on the gate signal provided from the control PCB 5110. To pass.

The slave data driving PCB 5140 is connected to the liquid crystal display panel 5105 through a film cable 5152 and displays a slave data signal for compensating for distortion of the data signal based on the slave data signal. As shown in Fig. 2, the second supply is supplied to the other side of the data line of the liquid crystal display panel 5106. In this case, the slave data driving PCB 5140 may receive power for driving through the same path as the transmission path of the slave data signal, or may be transferred through a film cable separately provided from the control PCB 5110. have.

The first to fourth inverters 5150, 5160, 5170, and 5180 are disposed on the rear surface of the liquid crystal display panel 5105. In particular, the control PCB 5110 is preferably disposed in an area where it is not disposed.

As shown in the figure, the slave data signal output from the control PCB 5110 is a film cable 5122 connected between the master data drive PCB 5120 and the liquid crystal display panel 5105, and the liquid crystal display panel 5105. ) Is transferred to the slave data driving PCB 5140 via a transmission wiring (not shown) provided in the C-axis) and a film cable 5152 connected between the liquid crystal display panel 5105 and the slave driving PCB 5140.

As shown in FIG. 7A, the PCB area, which occupies most of the rear surface of the flat panel display shown in FIG. 1, can be reduced to almost one quarter, and also half as compared to a flat panel display using two LVDS input signals. Can be.

8 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, the rear structure of the liquid crystal display device employing a master-slave method and each having a data PCB and a gate PCB will be described. do.

Referring to FIG. 8, the liquid crystal display 520 may include a liquid crystal display panel 5205, a control PCB 5210, a master data drive PCB 5220, a gate drive PCB 5230, a slave data drive PCB 5240, and the like. First to fourth inverters 5250, 5260, 5270, and 5280 are included. For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 5205 and the components disposed on the front surface are illustrated on the same plane.

The control PCB 5210 is disposed on the rear surface of the liquid crystal display panel 5205 to receive a video input signal provided from an external graphic controller (not shown) through the video input cable 5207 and the connector 5305 and to receive a film. Cables 5211, 5212, 5213, and 5214 provide a master data signal and a power supply for driving the master data driving PCB 5220.

The master data driving PCB 5220 supplies the data signal to one side of the data line of the liquid crystal display panel 5206 based on the master data signal provided from the control PCB 2110.

The gate driving PCB 5130 is connected to the control PCB 5210 through the film cable 5215 to receive a signal for a gate, a power supply, and a slave data from the control PCB 5210 and receive the signal for the gate. The scan signal is transmitted to one side of the gate line provided in the liquid crystal display panel 5205, and the slave data signal is transmitted to the slave data driving PCB 5240 through the film cable 5252. In this case, the gate driving PCB 5130 has a separate transmission line for transmitting the slave data signal.

The slave data driving PCB 5240 is connected to the gate driving PCB 5130 through a film cable 5252 to display a slave data signal for compensating for the distortion of the data signal based on the slave data signal. As shown in Fig. 2, the second supply is supplied to the other side of the data line of the liquid crystal display panel 5205. In this case, the slave data driving PCB 5240 may receive power for driving through the same path as the transmission path of the slave data signal, or may be transmitted through a film cable separately provided from the control PCB 5210. have.

The first to fourth inverters 5250, 5260, 5270, and 5280 are disposed on the rear surface of the liquid crystal display panel 5205. In particular, the control PCB 5210 may be disposed in an area where the control PCB 5210 is not disposed.

As shown in the figure, the signal for slave data output from the control PCB 5210 is connected to the film cable 5215 and the gate drive PCB 5230 connected between the control PCB 5210 and the gate drive PCB 5230. It is transmitted to the slave data driving PCB 5240 via the provided transmission wiring (not shown in the figure) and the film cable 5252 connected between the gate driving PCB 5230 and the slave driving PCB 5240.

9 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, a rear structure of a liquid crystal display device employing a master-slave method and having a data PCB and a gate PCB respectively will be described. do.

Referring to FIG. 9, the liquid crystal display 530 may include a liquid crystal display panel 5305, a control PCB 5310, a master data drive PCB 5320, a gate drive PCB 5330, a slave data drive PCB 5340, and a liquid crystal display panel 5530. First to fourth inverters 5350, 5360, 5370, and 5380 are included. For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 5305 and the components disposed on the front surface are illustrated on the same plane.

The control PCB 5310 is disposed on the rear surface of the liquid crystal display panel 5305 to receive a video input signal provided from an external graphic controller (not shown) via the video input cable 5307 and the connector 5309. Signals for master data, slave data, and power for driving the master data driving PCB 5220 are provided through cables 5311, 5312, 5313, and 5314.

The master data driving PCB 5320 supplies the data signal to one side of the data line of the liquid crystal display panel 5305 based on the master data signal provided from the control PCB 5310.

The gate drive PCB 5330 is connected to the control PCB 5310 through the film cable 5315 to receive signals and power for the gate from the control PCB 5310, and the master data drive PCB 5320 and the film cable 5322. ), The slave data signal is transmitted to the slave data driving PCB 5340 in a zigzag manner with the liquid crystal display panel 5305.

In other words, the slave data signal is a film having a transmission line (not shown) separately formed in the liquid crystal display panel 5305, a data driving chip connected to the gate driving PCB 5330, and formed by a chip on film (COF) method. The transmission data is transferred to the slave data driving PCB 5340 in a zigzag manner between a separate transmission wiring (not shown) formed in the cable and a transmission wiring (not shown) separately formed on the gate driving PCB.

The slave data driving PCB 5340 is connected to the gate driving PCB 5330 through a film cable 5332 to display a slave data signal for compensating for distortion of the data signal based on the slave data signal. As shown in Fig. 2, the second supply is supplied to the other side of the data line of the liquid crystal display panel 5305. In this case, the slave data driving PCB 5340 may receive power for driving through the same path as the transmission path of the slave data signal, or may be transferred through a film cable separately provided from the control PCB 5310. have.

The first to fourth inverters 5350, 5360, 5370, and 5380 are disposed on the rear surface of the liquid crystal display panel 5305. In particular, the control PCB 5310 may be disposed in an area where the control PCB 5310 is not disposed.

As shown above, signals and power for driving the gate drive IC and the slave data drive IC are transmitted to the PCB of the master data drive IC through the control PCB 5310, and the gate drive through the film cable 5325. The signal / power source connected to the PCB 5330 and also for the slave data drive IC may be configured to transfer from the gate drive PCB 5330 to the slave data drive IC via a film cable. In this case, all the film cables used may be transferred through the metal wiring of the panel.

FIG. 10 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, a rear structure of a liquid crystal display device having a data PCB and a gateless structure using a master-slave method will be described. do.

Referring to FIG. 10, the liquid crystal display 610 may include a liquid crystal display panel 6105, a control PCB 6110, a master data drive PCB 6120, a slave data drive PCB 6130, and first to fourth inverters ( 6140, 6145, 6150, 6155. For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 6105 and the components disposed on the front surface are illustrated on the same plane.

The control PCB 6110 is disposed on the rear surface of the liquid crystal display panel 6105 to receive a video input signal provided from an external graphic controller (not shown) via the video input cable 6107 and the connector 6109 and to film. The cables 6111, 6112, 6113, and 6114 provide a master data signal, a slave data signal, and a power supply for driving the master data driving PCB 6120.

The master data driving PCB 6120 supplies the data signal to one side of the data line of the liquid crystal display panel 6105 based on the master data signal provided from the control PCB 6110.

The slave data driving PCB 6130 receives a signal for slave data through a separate transmission line (not shown) formed in the liquid crystal display panel 6105. In this case, a separate gate driver circuit part is formed in the liquid crystal display panel 6105 to convert the gate signal into a scan signal and transmit the scan signal to a gate line of the liquid crystal display panel on the same substrate on which the thin film transistor is formed. It has a gateless structure. In operation, the slave data driving PCB 6130 may generate a slave data signal for compensating for the distortion of the data signal based on the slave data signal, as shown in FIG. 7B, of the liquid crystal display panel 6105. Supply to the other side of the data line. In this case, the slave data driving PCB 6130 may receive power for driving through the same path as the transmission path of the slave data signal, or may be transmitted through a film cable separately provided from the control PCB 6110. have.

The first to fourth inverters 6140, 6145, 6150, and 6155 are disposed on the rear surface of the liquid crystal display panel 6105. In particular, the control PCB 6110 may be disposed in an area where the control PCB 6110 is not disposed.

As shown, the signal output from the control PCB 6110 is a TCP film between the master-side data PCB 6120 and the liquid crystal display panel 6105-master data PCB 6120 via the film cable 6111 (drawings). Slave-side data PCB 6130 via the TCP film (not numbered) between the liquid crystal display panel 6105 and the slave data PCB 6130 and the transmission wiring formed in the liquid crystal display panel 6105. Is entered.

FIG. 11 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, a rear surface of a liquid crystal display device employing a master-slave method and having a data PCB and a gateless structure is shown. Explain the structure.

Referring to FIG. 11, the liquid crystal display 620 includes a liquid crystal display panel 6205, a control PCB 6210, and a master data driving PCB 6220. The first to fourth inverters 6140, 6145, 6150, and 6155 may be used. do. Compared with FIG. 10, even though the same components are given different reference numbers, their connection relations and operations are similar, the detailed description thereof will be omitted and only the differences will be described.

The liquid crystal display panel 6205 generates a scan signal for controlling the turn-on / turn-off operation of the thin film transistor based on the gate signal transmitted from the control PCB 6110, and generates the generated scan signal in the liquid crystal display panel. It has a gateless structure in which a separate gate driving circuit for transferring to the gate line is formed, and the slave data driving circuit 6230 incorporates a COG method.

As shown, the signal output from the control PCB 6210 is a TCP film between the master side data PCB 6220 and the liquid crystal display panel 6205 to the master data PCB 6220 via the film cable 6211 (drawings). The number is inputted to the slave data driving circuit 6230 via the transmission line (not shown) formed on the liquid crystal display panel 6205.

12 is a view for explaining the structure of a flat panel display device according to another embodiment of the present invention. In particular, a rear structure of a liquid crystal display device employing a master-slave method and having a dual gate-dual data driving method is shown. Explain.

Referring to FIG. 12, the liquid crystal display 700 may include a liquid crystal display panel 705, a control PCB 710, a first master data driving PCB 720, a second master data driving PCB 730, and a first gate driving. PCB 740, second gate drive PCB 750, first slave data drive PCB 760, second slave data drive PCB 770, and first to fifth inverters 781, 782, 783, 784 , 785). For convenience of description, the components disposed on the rear surface of the liquid crystal display panel 705 and the components disposed on the front surface are illustrated on the same plane.

The control PCB 710 is disposed on the rear surface of the liquid crystal display panel 705 to receive a video input signal provided from an external graphic controller via the first video input cable 411 and the first connector 412. The first and second film cables 711 and 712 provide the first master data signal, the first gate signal, and the first slave data signal to the first master data driving PCB 720. The second slave data signal, the second gate signal, and the second slave data signal are provided to the second master data driving PCB 730 through the fourth film cables 713 and 714. In this case, the first master data signal and the first slave data signal are signals corresponding to one region of the liquid crystal display panel 705, and the second master data signal and the second slave data signal are liquid crystal displays. The signal corresponds to the other side area of the panel 705.

The first master data driving PCB 720 includes a separate transmission line 725 for transmitting the signal for the first gate and the signal for the first slave data, and the signal for the first gate transmitted from the control PCB 710. And a signal for the first slave data are provided to the first gate driving PCB 740 through the film cable 727.

The second master data driving PCB 730 has a separate transmission line 735 for transmitting the signal for the second gate and the signal for the second slave data, and the signal for the second gate transmitted from the control PCB 710. And a signal for second slave data to the second gate driving PCB 750 through the film cable 737.

The first gate driving PCB 740 has a separate transmission wiring 745 for transmitting a signal for the first slave data and is connected to the first master data driving PCB 720 through the film cable 727. The film cable 747 is connected to the first slave data driving PCB 760. In operation, the scan signal is transmitted to one side of a gate line provided in the liquid crystal display panel based on the signal for the first gate transmitted from the first master data driving PCB 720 via the film cable 727, and the film cable The first slave data signal transmitted from the first master data driving PCB 720 via the 727 is transmitted to the first slave data driving PCB 760 through the film cable 747.

The second gate driving PCB 750 has a separate transmission line 755 for transmitting a signal for the second slave data and is connected to the second master data driving PCB 730 through the film cable 737. The film cable 757 is connected to the second slave data driving PCB 770. In operation, the scan signal is transmitted to one side of a gate line provided in the liquid crystal display panel based on the second gate signal transmitted from the second master data driving PCB 730 via the film cable 737, and the film cable The second slave data signal transmitted from the second master data driving PCB 730 via the 737 is transferred to the second slave data driving PCB 770 through the film cable 757.

The first slave data driving PCB 760 has a separate transmission wiring 765 for transmitting a signal for the first slave data and is connected to the first gate driving PCB 740 through the film cable 747. do. In operation, the first slave data signal for compensating for the distortion of the first data signal based on the signal for the first slave data transmitted from the first gate drive PCB via the film cable 747 is shown in FIG. 7B. As described above, the signal is supplied to the other side of the data line of the liquid crystal display panel 705. In this case, the first slave data driving PCB 760 may receive power for driving through the same path as the transmission path of the signal for the first slave data, and may provide a film cable separately provided from the control PCB 710. It can also be delivered.

The second slave data driving PCB 770 has a separate transmission wiring 775 for transmitting a signal for the second slave data and is connected to the second gate driving PCB 750 through the film cable 757. do. In operation, a second slave data signal for compensating for distortion of the second data signal based on the signal for second slave data transmitted from the second gate drive PCB via the film cable 757 is shown in FIG. 7B. As described above, the signal is supplied to the other side of the data line of the liquid crystal display panel 705. In this case, the second slave data driving PCB 770 may receive power for driving through the same path as the transmission path of the signal for the second slave data, and may provide a film cable separately provided from the control PCB 710. It can also be delivered.

The first to fifth inverters 781, 782, 783, 784, and 785 are disposed on the rear surface of the liquid crystal display panel 705. In particular, the control PCB 710 is preferably disposed in an area where it is not disposed.

As described above, by using the master-slave data drive IC as a method for driving a large-screen, high-resolution liquid crystal display device, the demand for PCB can be reduced by half, and the number of parts can be reduced by half, thus manufacturing The cost can be reduced and a great degree of freedom can be obtained in the design of the mechanism structure.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, the control PCB disposed on the rear surface of the flat panel display device adopting the large screen, the dual gate driving method and the dual data driving method suitable for high resolution has a substantially H shape. The area of the device can be minimized, and thus a space for arranging other components such as an inverter can be secured, thereby providing sufficient margin in the design.

In addition, it is possible to reduce the area of the control PCB by dividing the control PCB disposed in the large-screen, high-resolution flat panel display into two, and applying two LVDS signals obtained by converting the video input signal to each divided control PCB.

Also, by setting the gate driver that drives the upper gate line of the flat panel display as a master and the gate driver that drives the lower gate line as a slave, the flat panel display can be adapted to a large screen and high resolution even if a control PCB is implemented as one. Can be implemented.

Claims (22)

Flat panel display panel; Data driving PCBs respectively formed on upper and lower sides of the flat panel display panel and providing a data signal to the flat panel panel; Scan driving PCBs respectively formed at left and right sides of the flat panel display panel and providing scan signals to the flat panel display panel; And In order to generate an image signal to be supplied to the flat panel display panel, a timing control circuit is installed to receive an input signal from an external source, process the signal, and generate a driving signal. And a control PCB for transmitting, wherein the control PCB is formed on a rear surface of the flat panel display panel and has a substantially H shape. The flat panel display of claim 1, wherein the flat panel is a liquid crystal display panel. Flat panel display panel; A first control PCB to output a first data signal and a first scan signal based on a first video input signal input through the first connector; A second control PCB configured to output a second data signal and a first scan signal based on a second video input signal input through the second connector; A gate driving PCB generating a first scan signal based on the first scan signal and outputting the generated first scan signal to the flat panel display panel; A first data driving PCB generating a first data signal based on the first data signal and outputting the generated first data signal to the flat panel display panel; And And a second data driving PCB generating a second data signal based on the second data signal and outputting the generated second data signal to the flat panel display panel. The method of claim 3, A first inverting unit for first inverting and outputting an input signal provided from an external graphic controller, a second inverting unit for inverting and outputting the input signal with a different polarity than the first inversion, and the first And a first termination resistor connected to an output terminal of a second inverter, respectively, for outputting the first video input signal in response to the first inverted input signal and the second inverted input signal; A low voltage differential signal interface connected to an output terminal of a second inverting unit, the second terminating resistor unit outputting the second video input signal in response to the second inverted input signal and the first inverted input signal; A flat panel display device comprising: The method of claim 3, wherein the first control PCB transmits the first data signal to the first data driving PCB through a first film cable, and the second control PCB is the second data through a second film cable. And a signal is transmitted to the second data driving PCB. The flat panel display of claim 3, wherein the first control PCB transmits the first scan signal to the gate driving PCB through a third film cable. The method of claim 3, The first data driving PCB includes a first PCB corresponding to an upper first area of the flat panel display panel and a second PCB corresponding to an upper second area of the flat panel display panel, The second data driving PCB includes a third PCB corresponding to a lower first area of the flat panel display panel and a fourth PCB corresponding to a lower second area. And the gate driving PCB includes a fifth PCB corresponding to a left region of the flat panel display panel and a sixth PCB corresponding to a right region of the flat panel display panel. The method of claim 7, wherein the first control PCB generates first and second scan signals based on the first video input signal, and outputs the generated first scan signals to the first PCB. And outputting the second scan signal to the second PCB. The method of claim 8, The first control PCB and the first PCB are connected through a fourth film cable, the first PCB and the fifth PCB are connected through a fifth film cable, and the first scan signal is connected to the fifth film. The flat panel display device, characterized in that the transfer to the fifth PCB via a cable. The method of claim 8, The first control PCB and the second PCB are connected through a sixth film cable, the second PCB and the sixth PCB are connected through a seventh film cable, and the second scan signal is connected to the seventh film. And a sixth PCB transmitted through a cable. The flat panel display of claim 8, wherein the flat panel display is a liquid crystal display panel. Flat panel display panel; A control PCB which receives a video input signal through a connector and outputs a signal for master data, a signal for scanning and a signal for slave data; A master data driving PCB configured to output a first image signal to one side of the flat panel display panel based on the master data signal; A gate driving PCB configured to output a scan signal to the flat panel display panel based on the scan signal; And And a slave data driving PCB configured to output a second image signal for compensating the first image signal to the other side of the flat panel display panel based on the slave data signal. The method of claim 12, The control PCB transmits the signal for master data and the signal for slave data to the master data driving PCB through a first film cable, and the signal for scanning to the gate driving PCB through a second film cable. The master data driving PCB transmits a signal for the slave data to a transmission line formed in the flat panel display panel through a third film cable. And the flat panel display panel transmits the slave data signal transmitted through the transmission line to the slave data driving PCB through a fourth film cable. The method of claim 12, The control PCB transmits a signal for the master data to the master data driving PCB through a fifth film cable, and a signal for scanning and slave data to the gate driving PCB through a sixth film cable, And the gate driving PCB transmits the slave data signal to the slave data driving PCB through a seventh film cable. The method of claim 12, The control PCB transmits the signal for master data and the slave data signal to the master data driving PCB through an eighth film cable, and the signal for scanning to the gate driving PCB through a ninth film cable. The slab data signal is transmitted to the flat panel display panel through a tenth film cable and then transferred to the slab data driving PCB by a zigzag transmission method between the flat panel display panel and the gate driving PCB. Display device. The flat panel display of claim 12, wherein the gate driving PCB is formed on the same substrate as the flat panel display panel. The flat panel display of claim 12, wherein the slave data driving PCB is formed on the same substrate as the flat panel display panel. Flat panel display panel; A control PCB which receives a video input signal through a connector and outputs signals for first and second master data, signals for first and second scans, and signals for first and second slave data; A first master data driving PCB for outputting a first image signal to the flat panel display panel based on the first master data signal and transferring the first scan signal and the first slave data signal; A second master data driving PCB for outputting a second image signal to the flat panel display panel based on the second master data signal and transferring the second scan signal and the second slave data signal; A first gate driving PCB configured to output a first gate signal to the flat panel display panel based on the first scan signal, and to transmit the first slave data signal; A second gate driving PCB configured to output a second gate signal to the flat panel display panel based on the second scan signal, and to transmit the second slave data signal; A first slave data driving PCB outputting a third image signal for compensating the first image signal to the flat panel display panel based on the first slave data signal; And And a second slave data driving PCB configured to output a fourth image signal for compensating for the second image signal to the flat panel display panel based on the second slave data signal. The method of claim 18, The control PCB transmits the signal for the first master data, the signal for the first scan, and the signal for the first slave data to the first master data driving PCB through a first film cable. The first master data driving PCB transmits the first scanning signal and the first slave data signal to the first gate driving PCB through a second film cable. And the first gate driving PCB transmits the signal for the first slave data to the first slave driving PCB through a third film cable. The method of claim 18, The control PCB transmits the signal for the second master data, the signal for the second scan, and the signal for the second slave data to the second master data driving PCB through a fourth film cable. The second master data driving PCB transfers the second scanning signal and the second slave data signal to the second gate driving PCB through a fifth film cable. And the second gate driving PCB transmits the signal for the second slave data to the second slave driving PCB through a sixth film cable. The flat panel display of claim 18, wherein the first and second gate driving PCBs are formed on the same substrate as the flat panel display panel. The flat panel display of claim 18, wherein the flat panel display panel is a liquid crystal display panel.