KR20040037793A - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
- Publication number
- KR20040037793A KR20040037793A KR1020020066434A KR20020066434A KR20040037793A KR 20040037793 A KR20040037793 A KR 20040037793A KR 1020020066434 A KR1020020066434 A KR 1020020066434A KR 20020066434 A KR20020066434 A KR 20020066434A KR 20040037793 A KR20040037793 A KR 20040037793A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- titanium
- titanium nitride
- forming
- nitride film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히The present invention relates to semiconductor manufacturing technology, in particular
COB(Capacitor On Bitline) 구조의 DRAM 소자에서는 비트라인으로 텅스텐막(W)을 사용하는 경우, 주변회로지역의 소스/드레인에 대한 금속선 형성 공정은 비트라인을 형성하는 과정에서 이루어진다. 이러한 경우 텅스텐 비트라인과 소스/드레인과의 콘택을 비트라인콘택(bitline contact)이라고 명명한다.In a DRAM device having a capacitor on bitline (COB) structure, when a tungsten film (W) is used as a bit line, a metal line forming process for a source / drain in a peripheral circuit area is performed in a process of forming a bit line. In this case, the contact between the tungsten bit line and the source / drain is called a bitline contact.
도 1a는 종래기술에 따른 텅스텐비트라인을 포함하는 반도체 소자의 소자 단면도이다.1A is a cross-sectional view of an element of a semiconductor device including a tungsten bit line according to the prior art.
도 1a를 참조하면, 반도체 기판(11)의 소정 영역에 소자간 분리막인 필드산화막(12)이 형성되고, 반도체 기판(11)의 선택된 영역상에 게이트산화막(13), 폴리실리콘막(14), 텅스텐실리사이드막(15), 게이트캡핑막(16)의 순서로 적층된 게이트구조물이 형성되고, 게이트구조물의 양측벽에 측벽스페이서(17)가 형성된다.Referring to FIG. 1A, a field oxide film 12, which is an interlayer isolation film, is formed in a predetermined region of a semiconductor substrate 11, and a gate oxide film 13 and a polysilicon film 14 are formed on a selected region of the semiconductor substrate 11. The gate structures stacked in the order of the tungsten silicide layer 15 and the gate capping layer 16 are formed, and sidewall spacers 17 are formed on both sidewalls of the gate structure.
그리고, 게이트구조물 및 측벽스페이서(17) 하측의 반도체 기판(11)내에 소스/드레인과 같은 접합영역(18)이 형성되고, 반도체 기판(11) 및 게이트구조물 상부를 층간절연막(19)이 덮고 있다.A junction region 18 such as a source / drain is formed in the semiconductor substrate 11 under the gate structure and the sidewall spacers 17, and the interlayer insulating film 19 covers the semiconductor substrate 11 and the gate structure. .
그리고, 층간절연막(19)을 식각하여 제공되는 비트라인콘택에 티타늄막과 티타늄나이트라이드막의 순서로 적층된 Ti/TiN 배리어막(20)과 텅스텐막(21)이 매립된다. 이때, 텅스텐막(21)은 비트라인이고, Ti/TiN 배리어막(20)과 접합영역간 계면에는 티타늄실리사이드막(22)이 형성되어 있다.Then, the Ti / TiN barrier film 20 and the tungsten film 21 stacked in the order of the titanium film and the titanium nitride film are buried in the bit line contact provided by etching the interlayer insulating film 19. At this time, the tungsten film 21 is a bit line, and a titanium silicide film 22 is formed at the interface between the Ti / TiN barrier film 20 and the junction region.
도 1a에서, 티타늄실리사이드막(22)을 형성하기 위해 티타늄막과 티타늄나이트라이드막을 증착한 후 급속열처리(Rapid Thermal Process; RTP)한다. 이러한 일련의 공정을 완료한 후 콘택 매립 및 배선작업을 위하여 화학기상증착법(CVD)을 이용하여 텅스텐막을 증착한다. 이때, 티타늄실리사이드막은 접촉저항의 감소를 위해 필수적인 구성 요소이며, Ti/TiN 배리어막의 티타늄나이트라이드막은 텅스텐막 증착을 위한 접착층으로 사용되면서 동시에 텅스텐막 증착시 사용되는 육불화텅스텐 (WF6) 가스가 접합영역(18)으로 침투되는 것을 방지하는 역할을 한다. 육불화텅스텐 가스의 침투는 접합영역(18)의 콘택저항을 열화시키는 것으로 알려져 있다. 따라서, 콘택저항을 안정화시키기 위해서는 육불화텅스텐 가스에 대한 접합영역(18)으로의 확산을 효과적으로 방지해야만 한다.In FIG. 1A, a titanium film and a titanium nitride film are deposited to form a titanium silicide film 22, followed by a rapid thermal process (RTP). After completing this series of processes, a tungsten film is deposited by chemical vapor deposition (CVD) for contact filling and wiring. At this time, the titanium silicide film is an essential component for reducing contact resistance, and the titanium nitride film of the Ti / TiN barrier film is used as an adhesive layer for tungsten film deposition and at the same time, tungsten hexafluoride (WF 6 ) gas used for tungsten film deposition is used. It serves to prevent penetration into the junction region 18. Penetration of tungsten hexafluoride gas is known to degrade the contact resistance of the junction region 18. Therefore, in order to stabilize the contact resistance, diffusion into the junction region 18 for tungsten hexafluoride gas must be effectively prevented.
그러나, 티타늄나이트라이드막이 물리기상증착법(PVD)으로 증착한 막일 경우에는 그 막질이 치밀하지 못하여 육불화텅스텐 가스가 접합영역(18)으로 침투하는 것을 효과적으로 억제하지 못하는 문제가 있다.However, in the case where the titanium nitride film is a film deposited by physical vapor deposition (PVD), the film quality is not dense and there is a problem that the tungsten hexafluoride gas does not effectively inhibit penetration of the tungsten hexafluoride gas into the junction region 18.
도 1b는 종래기술에 따른 티타늄막과 티타늄나이트라이드막의 단면을 도시한 도면이다.1B is a view showing a cross section of a titanium film and a titanium nitride film according to the prior art.
도 1b를 참조하면, 티타늄나이트라이드막은 1층 주상정 조직으로 형성되어 육불화텅스텐(WF6) 가스를 사용하는 텅스텐막 증착시 발생하는 불소(F)가 티타늄나이트라이드막의 치밀하지 못한 주상정계면으로 침입하여 티타늄나이트라이드막 하부에 형성된 티타늄막에 확산되어 TixFy계 화합물을 형성하게 된다. 이러한 TixFy계 화합물은 콘택저항을 중가시켜 소자의 신뢰도를 저하시키는 요인이 된다.Referring to FIG. 1B, the titanium nitride film is formed of a single-layer columnar structure, and fluorine (F) generated when the tungsten film is deposited using tungsten hexafluoride (WF6) gas is used as a dense columnar interface of the titanium nitride film. It penetrates and diffuses into the titanium film formed under the titanium nitride film to form a TixFy compound. Such TixFy-based compounds increase the contact resistance, which reduces the reliability of the device.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로, 콘택에 텅스텐막을 매립할 때, 소스가스인 육불화텅스텐 가스에 의한 콘택저항의 열화를 방지하는데 적합한 반도체 소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and provides a method for forming a contact of a semiconductor device suitable for preventing deterioration of contact resistance caused by tungsten hexafluoride gas as a source gas when a tungsten film is buried in the contact. The purpose is.
도 1a는 종래기술에 따른 텅스텐비트라인을 포함하는 반도체 소자의 소자 단면도이다.1A is a cross-sectional view of an element of a semiconductor device including a tungsten bit line according to the prior art.
도 1b는 종래기술에 따른 티타늄막과 티타늄나이트라이드막의 단면을 도시한 도면이다.1B is a view showing a cross section of a titanium film and a titanium nitride film according to the prior art.
도 2는 본 발명의 제1 실시예에 따른 비트라인콘택의 형성 방법을 도시한 공정 흐름도,2 is a process flowchart showing a method of forming a bit line contact according to a first embodiment of the present invention;
도 3은 도 2에 따른 반도체 소자의 단면도,3 is a cross-sectional view of the semiconductor device according to FIG. 2;
도 4는 본 발명의 제2 실시예에 따른 비트라인콘택의 형성 방법을 도시한 공정 흐름도,4 is a process flowchart illustrating a method of forming a bit line contact according to a second embodiment of the present invention;
도 5는 도 4에 따른 반도체 소자의 단면도.5 is a cross-sectional view of the semiconductor device according to FIG. 4.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 38 : 접합영역31 semiconductor substrate 38 junction area
39 : 층간절연막 40 : 비트라인콘택홀39: interlayer insulating film 40: bit line contact hole
41 : 티타늄막 42 : 티타늄나이트라이드막41 titanium film 42 titanium nitride film
43 : 티타늄실리사이드막 44 : 텅스텐막43: titanium silicide film 44: tungsten film
상기 목적을 달성하기 위한 본 발명의 반도체소자의 콘택 형성 방법은 반도체 기판상에 콘택홀을 형성하는 단계, 상기 콘택홀에 티타늄막을 증착하는 단계, 상기 티타늄막상에 바이어스를 인가하면서 티타늄나이트라이드막을 증착하는 단계, 급속열처리를 통해 상기 콘택홀내 상기 반도체기판의 표면에 티타늄실리사이드막을 형성하는 단계, 및 상기 티타늄나이트라이드막상에 상기 콘택홀을 채울때까지 텅스텐막을 증착하는 단계를 포함함을 특징으로 한다.In the method of forming a contact of a semiconductor device of the present invention for achieving the above object, forming a contact hole on a semiconductor substrate, depositing a titanium film in the contact hole, depositing a titanium nitride film while applying a bias on the titanium film And forming a titanium silicide film on the surface of the semiconductor substrate in the contact hole through rapid heat treatment, and depositing a tungsten film until the contact hole is filled on the titanium nitride film.
또한, 본 발명의 반도체소자의 콘택 형성 방법은 반도체 기판상에 콘택홀을 형성하는 단계, 상기 콘택홀에 티타늄막을 증착하는 단계, 상기 티타늄막상에 바이어스를 인가하면서 제1 티타늄나이트라이드막을 증착하는 단계, 급속열처리를 통해 상기 콘택홀내 상기 반도체기판의 표면에 티타늄실리사이드막을 형성하는 단계, 상기 제1 티타늄나이트이드막상에 바이어스를 인가하면서 제2 티타늄나이트라이드막을 증착하는 단계, 및 상기 제2 티타늄나이트라이드막상에 상기 콘택홀을 채울때까지 텅스텐막을 증착하는 단계를 포함함을 특징으로 한다.In addition, the method for forming a contact of a semiconductor device of the present invention comprises the steps of forming a contact hole on a semiconductor substrate, depositing a titanium film in the contact hole, depositing a first titanium nitride film while applying a bias on the titanium film Forming a titanium silicide film on the surface of the semiconductor substrate in the contact hole through rapid thermal treatment, depositing a second titanium nitride film while applying a bias on the first titanium nitride film, and the second titanium nitride film And depositing a tungsten film until the contact hole is filled on the film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2는 본 발명의 제1 실시예에 따른 비트라인콘택의 형성 방법을 도시한 공정 흐름도이고, 도 3은 도 2에 따른 반도체 소자의 단면도이다.2 is a flowchart illustrating a method of forming a bit line contact according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2.
도 2에 도시된 바와 같이, 비트라인콘택의 형성 방법은, 크게 트랜지스터의 소스/드레인과 같은 접합영역을 형성하는 과정(S1), 콘택홀 형성 과정(S2), 티타늄막 증착 과정(S3), IMP법을 이용한 티타늄나이트라이드막 증착 과정(S4), 급속열처리 과정(S5), 화학기상증착법을 이용한 텅스텐막 증착 과정(S6)으로 구성된다.As shown in FIG. 2, the method of forming a bit line contact may include forming a junction region such as a source / drain of a transistor (S1), forming a contact hole (S2), depositing a titanium film (S3), Titanium nitride film deposition process (S4) using the IMP method, rapid thermal treatment (S5), tungsten film deposition process (S6) using the chemical vapor deposition method.
도 3을 참조하여 도 2를 설명하면, 먼저, 접합영역을 형성하는 과정(S1)은 반도체 기판(31)의 소정 영역에 소자간 분리막인 필드산화막(32)을 형성한 후, 반도체 기판(31)의 선택된 영역상에 게이트산화막(33), 폴리실리콘막(34), 텅스텐실리사이드막(35), 게이트캡핑막(36)의 순서로 적층된 게이트구조물을 형성한다. 다음에, 게이트구조물의 양측벽에 측벽스페이서(37)를 형성한 후, 게이트구조물 및측벽스페이서(37) 하측의 반도체 기판(31)내에 소스/드레인과 같은 접합영역(38)을 형성한다. 이때, 접합영역(38)은 LDD(Lightly Doped Drain) 구조일 수 있고, 콘택저항 개선을 위해 도펀트가 추가로 이온주입될 수 있다.Referring to FIG. 3, referring to FIG. 2, first, in a step S1 of forming a junction region, a field oxide layer 32, which is an isolation layer between elements, is formed in a predetermined region of the semiconductor substrate 31, and then the semiconductor substrate 31 is formed. The gate structures stacked in the order of the gate oxide film 33, the polysilicon film 34, the tungsten silicide film 35, and the gate capping film 36 are formed on the selected region of the " Next, after the sidewall spacers 37 are formed on both sidewalls of the gate structure, a junction region 38 such as a source / drain is formed in the semiconductor substrate 31 under the gate structure and the sidewall spacers 37. In this case, the junction region 38 may be a lightly doped drain (LDD) structure, and a dopant may be additionally implanted to improve contact resistance.
콘택홀 형성 과정(S2)은 반도체 기판(31) 및 게이트구조물 상부에 층간절연막(39)을 증착 및 평탄화한 후, 층간절연막(39)을 식각하여 접합영역(38)을 노출시키는 비트라인콘택홀(40)을 형성한다.In the contact hole forming process S2, after depositing and planarizing the interlayer insulating layer 39 on the semiconductor substrate 31 and the gate structure, the bit line contact hole exposing the junction region 38 by etching the interlayer insulating layer 39. 40 is formed.
티타늄막 증착 과정(S3)은 비트라인콘택홀(40)을 포함한 층간절연막(39)상에 티타늄막(41)을 증착한다. 이때, 티타늄막(41)은 후속 급속열처리(RTP) 공정 수행시 접합영역(38)의 실리콘과 반응하여 티타늄실리사이드막을 형성하고, 티타늄실리사이드막은 비트라인 콘택의 접촉 저항을 낮추어 주는 역할을 한다.In the titanium film deposition process S3, the titanium film 41 is deposited on the interlayer insulating film 39 including the bit line contact hole 40. At this time, the titanium film 41 reacts with silicon in the junction region 38 during the subsequent rapid heat treatment (RTP) process to form a titanium silicide film, and the titanium silicide film serves to lower the contact resistance of the bit line contact.
IMP법을 이용한 티타늄나이트라이드막 증착 과정(S4)을 살펴보면, 티타늄막(41)상에 IMP(Ionized Metal Plasma)법을 이용하여 티타늄나이트라이드막(42)을 100Å∼300Å의 두께로 증착한다.Looking at the titanium nitride film deposition process (S4) using the IMP method, the titanium nitride film 42 is deposited on the titanium film 41 by using the ionized metal plasma (IMP) method to a thickness of 100 ~ 300Å.
이때, 티타늄나이트라이드막(42)은 배리어막으로서의 기능을 한다. 즉, 먼저 형성된 티타늄막(41)이 산화되는 것을 방지하고 또한 후속하여 화학기상증착법(CVD)에 의해 형성되는 텅스텐막(W)에서의 육불화텅스텐(WF) 가스의 침투를 방지할 목적으로 형성된다.At this time, the titanium nitride film 42 functions as a barrier film. That is, the purpose is to prevent the first titanium film 41 from being oxidized and subsequently to prevent penetration of tungsten hexafluoride (WF) gas from the tungsten film (W) formed by chemical vapor deposition (CVD). do.
티타늄나이트라이드막 증착 방법을 살펴보면, 증착막에 바이어스를 인가하여 증착되는 티타늄나이트라이드막의 미세 구조를 치밀화하므로써 육불화텅스텐(WF6)가스에 대한 확산능력을 증대시킨다. 이때, 바이어스는 100W∼400W의 조건에서 조절한다.Looking at the method of depositing the titanium nitride film, by applying a bias to the deposited film to increase the fine structure of the deposited titanium nitride film by increasing the diffusion ability to the tungsten hexafluoride (WF 6 ) gas. At this time, the bias is adjusted under the conditions of 100W to 400W.
예를 들어, 챔버내에서 장착된 RF(Radio Frequency) 코일을 이용하여 Ti과 N의 이온화율을 극대화시킨 후, 기판에 바이어스를 인가하여 Ti와 N 이온을 강하게 끌어당겨 TiN막을 증착한다. 이는 기판에 인가된 바이어스를 조절하므로서 이온화된 TiN이 높은 에너지를 가지고 입사하게 할 수 있음을 의미한다.For example, after maximizing the ionization rate of Ti and N using an RF (Radio Frequency) coil mounted in the chamber, a TiN film is deposited by strongly applying Ti and N ions by applying a bias to the substrate. This means that the ionized TiN can be incident with high energy by adjusting the bias applied to the substrate.
이와 같이 TiN이 높은 에너지를 가지고 기판에 입사하는 경우에는 성장하는 티타늄나이트라이드막과 입사되는 티타늄나이트라이드 사이의 충돌(Ion bombardment)로 인하여 PVD TiN에서 나타나는 주상조직이 보다 치밀한 조직으로 천이된다.As described above, when TiN is incident on the substrate with high energy, columnar tissues appearing in PVD TiN transition to a more dense structure due to an ion bombardment between the growing titanium nitride film and the incident titanium nitride.
PVD TiN에서 나타나는 주상조직은 주상과 주상사이의 계면이 확산의 지름길로 작용하여 확산방지능력이 저하된다. 이에 비해 IMP법에 의한 치밀한 조직은 주상과 주상 사이의 계면이 없으므로 확산의 지름길로 사용되는 부분에 제거됨에 따라 육불화텅스텐가스에 대한 배리어 능력이 크게 향상된다.In the columnar structure of PVD TiN, the diffusion prevention ability decreases because the interface between columnar and columnar acts as a shortcut for diffusion. On the other hand, the dense structure by the IMP method has no interface between the columnar phase and the columnar phase and is removed in the portion used as a shortcut for diffusion, thereby greatly improving the barrier ability against tungsten hexafluoride gas.
급속열처리 과정(S5)을 살펴보면, 티타늄나이트라이드막을 형성한 후 열처리를 위한 챔버내에서 650℃로 급속열처리한다. 이때, 급속열처리시 티타늄막(41)의 티타늄이 접합영역(38)의 실리콘원자와 반응하여 티타늄실리사이드막(43)을 형성시킨다.Looking at the rapid heat treatment process (S5), after forming the titanium nitride film is subjected to rapid heat treatment at 650 ℃ in the chamber for heat treatment. At this time, the titanium of the titanium film 41 reacts with the silicon atoms of the junction region 38 in the rapid heat treatment to form the titanium silicide film 43.
다음으로, 화학기상증착법을 이용한 텅스텐막의 증착 과정(S6)을 살펴보면,소스가스로 육불화텅스텐(WF6) 가스를 이용하여 비트라인콘택홀을 매립시킬 때까지 텅스텐막(44)을 증착한다.Next, referring to the deposition process (S6) of the tungsten film using the chemical vapor deposition method, the tungsten film 44 is deposited until the bit line contact holes are filled using tungsten hexafluoride (WF 6 ) gas as the source gas.
도 4는 본 발명의 제2 실시예에 따른 비트라인콘택의 형성 방법을 도시한 공정 흐름도이고, 도 5는 도 4에 따른 반도체 소자의 단면도이다.4 is a flowchart illustrating a method of forming a bit line contact according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4.
도 4에 도시된 바와 같이, 비트라인콘택의 형성 방법은, 크게 트랜지스터의 소스/드레인과 같은 접합영역을 형성하는 과정(S11), 콘택홀 형성 과정(S12), 티타늄막 증착 과정(S13), IMP법을 이용한 제1 티타늄나이트라이드막 증착 과정(S14), 급속열처리 과정(S5), IMP법을 이용한 제2 티타늄나이트라이드막 증착 과정(S16), 화학기상증착법을 이용한 텅스텐막 증착 과정(S17)으로 구성된다.As shown in FIG. 4, the method of forming a bit line contact may include forming a junction region such as a source / drain of a transistor (S11), forming a contact hole (S12), depositing a titanium film (S13), The first titanium nitride film deposition process using the IMP method (S14), the rapid heat treatment process (S5), the second titanium nitride film deposition process using the IMP method (S16), the tungsten film deposition process using the chemical vapor deposition method (S17) It is composed of
도 5를 참조하여 도 4를 설명하면, 먼저, 접합영역을 형성하는 과정(S11)은 반도체 기판(31)의 소정 영역에 소자간 분리막인 필드산화막(32)을 형성한 후, 반도체 기판(31)의 선택된 영역상에 게이트산화막(33), 폴리실리콘막(34), 텅스텐실리사이드막(35), 게이트캡핑막(36)의 순서로 적층된 게이트구조물을 형성한다. 다음에, 게이트구조물의 양측벽에 측벽스페이서(37)를 형성한 후, 게이트구조물 및 측벽스페이서(37) 하측의 반도체 기판(31)내에 소스/드레인과 같은 접합영역(38)을 형성한다. 이때, 접합영역(38)은 LDD(Lightly Doped Drain) 구조일 수 있고, 콘택저항 개선을 위해 도펀트가 추가로 이온주입될 수 있다.Referring to FIG. 5, a process of forming a junction region (S11) is performed by forming a field oxide film 32, which is an interlayer isolation film, in a predetermined region of a semiconductor substrate 31. The gate structures stacked in the order of the gate oxide film 33, the polysilicon film 34, the tungsten silicide film 35, and the gate capping film 36 are formed on the selected region of the " Next, after the sidewall spacers 37 are formed on both sidewalls of the gate structure, a junction region 38 such as a source / drain is formed in the gate structure and the semiconductor substrate 31 under the sidewall spacers 37. In this case, the junction region 38 may be a lightly doped drain (LDD) structure, and a dopant may be additionally implanted to improve contact resistance.
콘택홀 형성 과정(S12)은 반도체 기판(31) 및 게이트구조물 상부에 층간절연막(39)을 증착 및 평탄화한 후, 층간절연막(39)을 식각하여 접합영역(38)을 노출시키는 비트라인콘택홀(40)을 형성한다.In the contact hole forming process S12, after depositing and planarizing the interlayer insulating layer 39 on the semiconductor substrate 31 and the gate structure, the bit line contact hole exposing the junction region 38 by etching the interlayer insulating layer 39. 40 is formed.
티타늄막 증착 과정(S13)은 비트라인콘택홀(40)을 포함한 층간절연막(39)상에 티타늄막(41)을 증착한다. 이때, 티타늄막(41)은 후속 급속열처리(RTP) 공정 수행시 접합영역(38)의 실리콘과 반응하여 티타늄실리사이드막을 형성하고, 티타늄실리사이드막은 비트라인 콘택의 접촉 저항을 낮추어 주는 역할을 한다.In the titanium film deposition process S13, the titanium film 41 is deposited on the interlayer insulating film 39 including the bit line contact hole 40. At this time, the titanium film 41 reacts with silicon in the junction region 38 during the subsequent rapid heat treatment (RTP) process to form a titanium silicide film, and the titanium silicide film serves to lower the contact resistance of the bit line contact.
IMP법을 이용한 제1 티타늄나이트라이드막 증착 과정(S14)을 살펴보면, 티타늄막(41)상에 IMP(Ionized Metal Plasma)법을 이용하여 제1 티타늄나이트라이드막(42a)을 100Å∼300Å의 두께로 증착한다.Looking at the first titanium nitride film deposition process (S14) using the IMP method, the thickness of the first titanium nitride film 42a on the titanium film 41 by using an ionized metal plasma (IMP) method of 100 ~ 300Å To be deposited.
이때, 제1 티타늄나이트라이드막(42a)은 배리어막으로서의 기능을 한다. 즉, 먼저 형성된 티타늄막(41)이 산화되는 것을 방지하고 또한 후속하여 화학기상증착법(CVD)에 의해 형성되는 텅스텐막(W)에서의 육불화텅스텐(WF) 가스의 침투를 방지할 목적으로 형성된다.At this time, the first titanium nitride film 42a functions as a barrier film. That is, the purpose is to prevent the first titanium film 41 from being oxidized and subsequently to prevent penetration of tungsten hexafluoride (WF) gas from the tungsten film (W) formed by chemical vapor deposition (CVD). do.
제1 티타늄나이트라이드막(42a) 증착 방법을 살펴보면, 증착막에 바이어스를 인가하여 증착되는 티타늄나이트라이드막의 미세 구조를 치밀화하므로써 육불화텅스텐(WF6) 가스에 대한 확산능력을 증대시킨다. 이때, 바이어스는 100W∼400W의 조건에서 조절한다.Looking at the deposition method of the first titanium nitride film 42a, by applying a bias to the deposited film, the microstructure of the deposited titanium nitride film is densified to increase the diffusion ability to the tungsten hexafluoride (WF 6 ) gas. At this time, the bias is adjusted under the conditions of 100W to 400W.
예를 들어, 챔버내에서 장착된 RF(Radio Frequency) 코일을 이용하여 Ti과 N의 이온화율을 극대화시킨 후, 기판에 바이어스를 인가하여 Ti와 N 이온을 강하게 끌어당겨 TiN막을 증착한다. 이는 기판에 인가된 바이어스를 조절하므로서 이온화된 TiN이 높은 에너지를 가지고 입사하게 할 수 있음을 의미한다.For example, after maximizing the ionization rate of Ti and N using an RF (Radio Frequency) coil mounted in the chamber, a TiN film is deposited by strongly applying Ti and N ions by applying a bias to the substrate. This means that the ionized TiN can be incident with high energy by adjusting the bias applied to the substrate.
이와 같이 TiN이 높은 에너지를 가지고 기판에 입사하는 경우에는 성장하는 티타늄나이트라이드막과 입사되는 티타늄나이트라이드 사이의 충돌(Ion bombardment)로 인하여 PVD TiN에서 나타나는 주상조직이 보다 치밀한 조직으로 천이된다.As described above, when TiN is incident on the substrate with high energy, columnar tissues appearing in PVD TiN transition to a more dense structure due to an ion bombardment between the growing titanium nitride film and the incident titanium nitride.
PVD TiN에서 나타나는 주상조직은 주상과 주상사이의 계면이 확산의 지름길로 작용하여 확산방지능력이 저하된다. 이에 비해 IMP법에 의한 치밀한 조직은 주상과 주상 사이의 계면이 없으므로 확산의 지름길로 사용되는 부분에 제거됨에 따라 육불화텅스텐가스에 대한 배리어 능력이 크게 향상된다.In the columnar structure of PVD TiN, the diffusion prevention ability decreases because the interface between columnar and columnar acts as a shortcut for diffusion. On the other hand, the dense structure by the IMP method has no interface between the columnar phase and the columnar phase and is removed in the portion used as a shortcut for diffusion, thereby greatly improving the barrier ability against tungsten hexafluoride gas.
급속열처리 과정(S15)을 살펴보면, 제1 티타늄나이트라이드막(42a)을 형성한 후 열처리를 위한 챔버내에서 650℃로 급속열처리한다. 이때, 급속열처리시 티타늄막(41)의 티타늄이 접합영역(38)의 실리콘원자와 반응하여 티타늄실리사이드막(43)을 형성시킨다.Referring to the rapid heat treatment process (S15), the first titanium nitride film 42a is formed and then rapidly heat treated at 650 ° C. in the chamber for heat treatment. At this time, the titanium of the titanium film 41 reacts with the silicon atoms of the junction region 38 in the rapid heat treatment to form the titanium silicide film 43.
IMP법을 이용한 제2 티타늄나이트라이드막 증착 과정(S16)을 살펴보면, 제1 티타늄나이트라이드막(42a)상에 IMP법을 이용하여 제2 티타늄나이트라이드막(42b)을 100Å∼300Å의 두께로 증착한다.Looking at the second titanium nitride film deposition process (S16) using the IMP method, the second titanium nitride film 42b on the first titanium nitride film 42a by using the IMP method to a thickness of 100 ~ 300Å Deposit.
이때, 제2 티타늄나이트라이드막(42b)은 육불화텅스텐 가스의 배리어 특성을 증대시키기 위하여 도입된 층으로, 제1 티타늄나이트라이드막이 급속열처리과정중 티타늄과 실리콘의 반응으로 인해 발생되는 스트레스에 의한 미소 크랙이 발생되어 육불화텅스텐에 대한 배리어능력이 저하되는 경우를 보충하는 역할을 수행한다.In this case, the second titanium nitride film 42b is a layer introduced to increase the barrier property of the tungsten hexafluoride gas, and the first titanium nitride film is caused by the stress generated due to the reaction of titanium and silicon during the rapid heat treatment process. It acts as a supplement to the case where the microcracks are generated and the barrier ability to tungsten hexafluoride is lowered.
따라서, 제2 티타늄나이트라이드막(42b)을 증착할때도 바이어스를 인가하여 치밀한 조직을 형성한다. 이때, 바이어스는 100W∼400W의 조건에서 조절한다.Therefore, when the second titanium nitride film 42b is deposited, a bias is applied to form a dense structure. At this time, the bias is adjusted under the conditions of 100W to 400W.
다음으로, 화학기상증착법을 이용한 텅스텐막의 증착 과정(S17)을 살펴보면, 소스가스로 육불화텅스텐(WF6) 가스를 이용하여 비트라인콘택홀을 매립시킬 때까지 텅스텐막(44)을 증착한다.Next, referring to the deposition process (S17) of the tungsten film using the chemical vapor deposition method, the tungsten film 44 is deposited until the bit line contact hole is filled using tungsten hexafluoride (WF 6 ) gas as the source gas.
도 6은 바이어스에 따른 티타늄나이트라이드막의 미세조직을 비교한 도면이다.6 is a view comparing the microstructure of the titanium nitride film according to the bias.
도 6에 도시된 바와 같이, 바이어스 인가없이 티타늄나이트라이드막을 증착하는 경우 주상과 주상 사이의 계면(i)이 다수 존재하지만, 400W의 바이어스를 인가하여 티타늄나이트라이드막을 증착하는 경우 막의 미세조직이 치밀화됨을 알 수 있다.As shown in FIG. 6, when the titanium nitride film is deposited without bias, there are many interfaces (i) between the main phase and the main phase. However, when the titanium nitride film is deposited by applying a bias of 400 W, the microstructure of the film becomes denser. It can be seen that.
도 7은 바이어스의 인가여부에 따른 콘택저항을 비교한 도면이다.7 is a view comparing contact resistance according to whether bias is applied.
도 7을 살펴보면, 바이어스를 인가하지 않은 경우의 콘택저항이 1170 정도이나, 바이어스를 200W로 인가한 경우의 콘택저항은 1100임을 감안하면, 바이어스를 인가하여 티타늄나이트라이드막을 증착하는 경우에 콘택저항이 감소됨을 알 수 있다.Referring to FIG. 7, considering that the contact resistance when the bias is not applied is about 1170 and the contact resistance when the bias is applied at 200W, the contact resistance is 1100 when the titanium nitride film is deposited by applying the bias. It can be seen that the decrease.
전술한 실시예들에서는 비트라인콘택에 대해서 설명하였으나, 텅스텐막을 화학기상증착법으로 이용하는 모든 콘택 공정에 적용 가능하다.In the above-described embodiments, the bit line contact has been described, but it is applicable to all the contact processes using the tungsten film by chemical vapor deposition.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 비트라인과 접합영역을 연결하는 비트라인콘택에 형성되는배리어막인 티타늄나이트라이드막의 미세조직을 치밀화하므로써 텅스텐막 증착시 발생되는 육불화텅스텐 가스에 대한 배리어능력을 증대시켜 콘택저항을 감소시킬 수 있는 효과가 있다.The present invention described above provides a contact resistance by increasing the barrier ability against tungsten hexafluoride gas generated during tungsten film deposition by densifying the microstructure of the titanium nitride film, which is a barrier film formed at the bit line contact connecting the bit line and the junction region. There is an effect that can reduce.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020066434A KR20040037793A (en) | 2002-10-30 | 2002-10-30 | Method for forming contact in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020066434A KR20040037793A (en) | 2002-10-30 | 2002-10-30 | Method for forming contact in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040037793A true KR20040037793A (en) | 2004-05-07 |
Family
ID=37336071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020066434A KR20040037793A (en) | 2002-10-30 | 2002-10-30 | Method for forming contact in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040037793A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100613348B1 (en) * | 2004-12-22 | 2006-08-21 | 동부일렉트로닉스 주식회사 | Method of forming a metal wiring layer having barrier metal layer by homogeneous deposition |
| KR100695497B1 (en) * | 2004-06-30 | 2007-03-15 | 주식회사 하이닉스반도체 | Method for forming cylindrical capacitor having titanium nitride bottom electrode in semiconductor memory device |
-
2002
- 2002-10-30 KR KR1020020066434A patent/KR20040037793A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100695497B1 (en) * | 2004-06-30 | 2007-03-15 | 주식회사 하이닉스반도체 | Method for forming cylindrical capacitor having titanium nitride bottom electrode in semiconductor memory device |
| KR100613348B1 (en) * | 2004-12-22 | 2006-08-21 | 동부일렉트로닉스 주식회사 | Method of forming a metal wiring layer having barrier metal layer by homogeneous deposition |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100243286B1 (en) | Method for manufacturing a semiconductor device | |
| US5767004A (en) | Method for forming a low impurity diffusion polysilicon layer | |
| US6614082B1 (en) | Fabrication of semiconductor devices with transition metal boride films as diffusion barriers | |
| US6514841B2 (en) | Method for manufacturing gate structure for use in semiconductor device | |
| US6337274B1 (en) | Methods of forming buried bit line memory circuitry | |
| KR20040017655A (en) | Method for forming metal contact in semiconductor device | |
| US6686277B1 (en) | Method of manufacturing semiconductor device | |
| US6800907B2 (en) | Method for fabricating semiconductor device | |
| US6087259A (en) | Method for forming bit lines of semiconductor devices | |
| KR20040037793A (en) | Method for forming contact in semiconductor device | |
| US6800553B2 (en) | Method for manufacturing a silicide layer of semiconductor device | |
| US6245631B1 (en) | Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line | |
| KR20010003695A (en) | method for forming gate electrode of semiconductor device | |
| US6537909B1 (en) | Method of preventing silicide spiking | |
| KR100451493B1 (en) | Metal wiring formation method of semiconductor device | |
| US7332796B2 (en) | Devices and methods of preventing plasma charging damage in semiconductor devices | |
| KR101003488B1 (en) | Method for forming semiconductor device | |
| KR100695483B1 (en) | Method of forming metal contact in semiconductor device | |
| KR20010059996A (en) | Method for manufacturing semiconductor device | |
| KR20040003491A (en) | Method of forming a metal wire in a semiconductor device | |
| KR100745905B1 (en) | Method of Forming Tungsten Bit Line | |
| US7537995B2 (en) | Method for fabricating a dual poly gate in semiconductor device | |
| US20020106863A1 (en) | Method for fabricating semiconductor devices | |
| KR100517353B1 (en) | Method for fabricating barrier metal of semiconductor device | |
| KR20030079298A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |