KR20040035120A - Method for manufacturing liquid crystal display - Google Patents

Abstract

PURPOSE: A method for manufacturing an LCD is provided to form a pad portion to have the same structure as a general mask as maintaining a resin film in an active area without an additional mask process in the pad portion, thereby realizing a high opening ratio. CONSTITUTION: A gate(100) is deposited on a transparent insulating substrate(50). A gate insulating layer(120) is deposited on the transparent insulating substrate(50) including the gate(100). A protective film(140) and a resin film(150a) are deposited on the gate insulating layer(120) in order. The resin film(150a) is exposed with the first and second shots having different energies. By performing a developing process in an upper part of an exposed material and etching the resin film(150a) of a via hole part of a pad portion, a via hole(160) is defined. By masking the resin film(150a) where the via hole(160) is formed, the gate(100) under the via hole(160) is exposed after etching the protective film(140) and the gate insulating layer(120) under the via hole(160).

Description

Liquid crystal display manufacturing method {Method for manufacturing liquid crystal display}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display, and more particularly, to a method for manufacturing a liquid crystal display used for manufacturing a high aperture ratio, a reflective panel, etc. using a resin film.

1 and 2 are cross-sectional views showing pads of a general 5 mask and a high opening ratio (resin film applied) 5 mask, and the test itself is not executed correctly due to lack of test margin during array & cell testing. The pin should contact the pixel electrode of the region accurately, but there is a problem that the pin contacts the pixel electrode of the region other than the via hole due to lack of margin.

In general, when the test pin is in contact with the pixel electrode (ITO or IXO) 17 on the resin film 15, the pixel electrode 17 of the portion is broken, so that an accurate test cannot be performed. Therefore, there is no problem in the test in the general 5 mask process, but it is a big problem in the high-aperture rate 5 mask process.

As shown in FIG. 3, when the resin film is completely removed in order to eliminate a margin shortage in the test generated in the high-aperture-five-mask process, the following problem occurs.

Therefore, the biggest difference between the conventional 5 mask pad portion and the high-aperture rate 5 mask pad portion is that the difference in test margin (Δ1 >> Δ2) is large depending on the presence or absence of the resin film 15 during the array & cell test.

That is, in the high-aperture-five mask process, since the resin film serves as a photoresist of the via hole at the same time, when the resin film is completely removed from the pad part, the photoresist for the via hole pattern is removed. As a result, the lower passivation layer and the gate insulating layer are also completely etched so that only the gate metal remains. Therefore, in the case of the pad part structure of FIG. 3, there is a problem that the pad part is easily peeled off during the pad rework in the module process.

As described above, even if the resin film is left in the pad portion or the resin film is completely removed during the process according to the prior art, a problem occurs.

Accordingly, the present invention has been made to solve the above problems of the prior art, the liquid crystal display manufacturing method to have the same structure as the general five masks on the pad portion while maintaining the resin film in the active region without additional mask process on the pad portion. The purpose is to provide.

1 is a process cross-sectional view showing a method for manufacturing a liquid crystal display using a pad portion of a typical five masks according to the prior art.

Figure 2 is a process cross-sectional view showing a method of manufacturing a liquid crystal display using a high aperture pad portion of a typical five mask using a resin film according to the prior art.

Figure 3 is a process cross-sectional view showing a method of manufacturing a liquid crystal display using a high-permeability pad portion of a typical five masks removed resin film according to the prior art.

4A to 4E are cross-sectional views illustrating a method of manufacturing a liquid crystal display using two shots having different exposure amounts according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display using a gray tone mask according to another embodiment of the present invention.

(Code description of main parts of drawing)

50: glass substrate 100: gate

120, 120a, 220: gate insulating layer 140, 140a, 240: protective film

150, 150a, 250: resin film 170: pixel electrode

280: Gray Tone Mask

The present invention for achieving the above object, forming a gate on a transparent insulating substrate; Forming a gate insulating layer on the transparent insulating substrate including the gate; Sequentially forming a protective film and a resin film on the gate insulating layer; Exposing the resin film to first and second shots having different energies; Forming a via hole by etching the resin film of the via portion of the pad part by performing a developing process on the exposed result; Etching the passivation layer under the via hole and the gate insulating layer using the resin film having the via hole as a mask to expose the gate under the via hole; And forming a transparent electrode on the passivation layer including the exposed portion of the gate.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4E are cross-sectional views illustrating a method of manufacturing a liquid crystal display using two shots having different exposure amounts according to an embodiment of the present invention.

First, as shown in FIG. 4A, the deposition of a protective film (eg, Phosphorus Doped Vapor Deposited Silicon (PVX)) is performed in the same manner as a general five-mask process. After deposition of the protective film 140, a resin film (organic insulating film) is formed. Deposit. In this case, the thickness T1 of the resin film 150 may be 2 μm or more in order to reduce the coupling capacitance.

4B and 4C, the exposure process is performed in two shots by varying the exposure amount with the same mask.

In the first shot (shown in FIG. 4B), an exposure process is performed at an exposure amount corresponding to the energy of Eop to form a pad hole and a via hole (region B) of the active region. In this case, the exposure amount corresponding to the energy of Eop is such that the resin film 150 in the A and C regions is not exposed and only the resin film 150 in the B region is completely removed to the surface of the protective film 140.

Subsequently, the second shot (shown in FIG. 4C) performs an exposure process with energy of Eop or less to partially expose the resin film 150 in the peripheral portions (regions A and C) of the pad portion.

That is, in the second shot, the exposure process is performed at an exposure amount corresponding to the energy of Eop or less over the entire areas A, B, and C, wherein the exposure amount corresponding to the energy of Eop or less is a protective film for via etching, which is a subsequent process ( The energy of the resin film 150 in the A and C regions is completely ashed during the etching of the 140 and the gate insulating layer 120.

Here, exposure to the B area is irrelevant, and the order of the first shot and the second shot is also irrelevant.

Next, as illustrated in FIG. 4D, the resin film 150 of the via hole (region B) is completely removed to expose the lower protective film, and the resin film 150a of the peripheral portions (A and C regions) is exposed. ) Will remain at the desired thickness T2.

At this time, the residual thickness T2 of the resin film 150a is calculated by the following equation.

Residual thickness of resin film T2 = (protective film thickness + gate insulation layer thickness) * (selectivity of protective film and resin film) * (1+ over etching)

Here, the selectivity of the resin film 150a is greater than that of the protective film 140, and the thickness of the protective film 140 is 200 to 4000 kPa.

Next, as shown in FIG. 4E, the protective film 140 is dry-etched using the residual resin film 150a as a photoresist pattern. At this time, oxygen is included in the etching gas so that the resin film 150a can be ashed.

That is, when the passivation layer 140 is dry-etched, the passivation layer 140 and the gate insulation layer 120 are etched in the via hole (B region) of the pad part to leave the passivation layer 140a and the gate insulation layer 120a. While the metal 100 is exposed to form the via hole 160, in the peripheral portions A and C of the via hole 160, the residual resin film 150a functions as an etch stop layer during the dry etching of the passivation layer 140a. At the same time, since the ashing of the residual resin film 150a is performed, the residual resin film 150a is finally removed and the protective film 140a remains.

Then, a pixel electrode (ITO or IXO) 170 is formed on the passivation layer 140a including the via hole 160.

Therefore, in the active region (not shown), the residual resin film 150a still remains to realize a high opening ratio, and in the pad part, the residual resin film 150a is removed, thereby testing array and cells and reworking the pad. This can solve problems that occur.

Meanwhile, a method of manufacturing a liquid crystal display using a gray tone mask according to another embodiment of the present invention will be described with reference to FIG. 5.

5 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display using the gray tone mask 280 according to another embodiment of the present invention.

First, as in the embodiment of the present invention, the deposition of the protective film proceeds in the same manner as the general five-mask process, and after the deposition of the protective film 240, a resin film (organic insulating film) 250 is deposited. In this case, the thickness T1 of the resin film 250 may be 2 μm or more in order to reduce the coupling capacitance.

Then, during the exposure process, the exposure process is performed using the half-tone gray tone mask 280, whereby the via hole (region B) of the pad part is the energy of Eop by the gray tone mask 280. (A and C regions) are simultaneously exposed with energy of Eop or less.

Subsequently, the same development process as in the embodiment of the present invention is performed to form the same structure as in FIG. 4D.

Subsequent subsequent processes are the same as the via hole forming process and the pixel electrode forming process illustrated in FIG. 4E, which will be briefly described as follows.

First, the protective film 240 is dry-etched using the resin film 250 as a photoresist pattern. At this time, oxygen is included in the etching gas so that the resin film 250 can be ashed.

That is, when the protective layer 240 is dry etched, the protective layer 240 and the gate insulating layer 220 are etched in the via hole (B region) of the pad part to expose the gate metal 200, and the peripheral portion A of the via hole is exposed. In region C), since the resin film 250 functions as an etch stop film of the passivation layer 240 during the dry etching of the passivation layer, and the ashing of the resin layer 250 is performed, the resin layer 250 is finally removed. The passivation layer 240 remains.

Then, a pixel electrode ITO or IXO (not shown) is formed on the passivation layer 240 including the via hole.

Therefore, as in the embodiment of the present invention, the resin region 250 is left in the active region (not shown) to realize a high opening ratio, and the pad portion is removed to remove the resin layer 250 during the test of the array & cell. This can solve problems that occur during and rework pads.

In addition, looking at another embodiment of the present invention, because the effect of the contact resistance due to the interfacial properties is the greatest, the deposition of the pixel electrode (ITO or IXO) in the deposition process under O ₂ pre-condition can bring the effect of the present invention have.

As described above, the effects of the present invention that can be expected by completely removing the resin film of the pad portion will be described in two main ways.

First, according to the present invention, there is an effect that the test itself may not be executed correctly due to the lack of test margin during the array & cell test.

That is, the pin should contact the pixel electrode of the via hole accurately, but the pin electrode contacts the pixel electrode other than the via hole due to lack of margin, which causes the pixel electrode to break, which causes the test to not proceed. There is an effect that can be solved.

In addition, when the resin film of the pad part is completely removed in order to remove the margin shortage during the first test, only the gate metal and the pixel electrode (ITO) are present in the pad part, and the rework is performed in a subsequent module process. There is an effect that can solve the problem that peeling occurs in the pad portion.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (14)

Forming a gate on the transparent insulating substrate; Forming a gate insulating layer on the transparent insulating substrate including the gate; Sequentially forming a protective film and a resin film on the gate insulating layer; Exposing the resin film to first and second shots having different energies; Forming a via hole by etching the resin film of the via portion of the pad part by performing a developing process on the exposed result; Etching the passivation layer under the via hole and the gate insulating layer using the resin film having the via hole as a mask to expose the gate under the via hole; And And forming a transparent electrode on the passivation layer including an exposed portion of the gate. The method of claim 1, wherein the first shot has a greater energy than the second shot. The method of manufacturing a liquid crystal display according to claim 1 or 2, wherein the first shot is exposed only to the resin film of the pad portion via hole portion. The method of claim 1 or 2, wherein the second shot is exposed to the entirety of the resin film or a resin film around the via hole portion. The method of claim 1, wherein the exposing step is performed using a gray tone mask. 6. The method of claim 5, wherein the energy exposed to the pad portion via hole portion of the gray tone mask is greater than the energy exposed to the peripheral portion of the pad portion via hole portion of the gray tone mask. The method of claim 1, wherein the resin film is removed by ashing a portion of the periphery of the via hole during the etching of the passivation layer and the gate insulating layer. The liquid crystal display manufacturing method according to claim 1 or 2, wherein the first and second shots are exposed in reverse order during the exposure process. The method of claim 1, wherein the etching gas of the passivation layer and the gate insulation layer contains oxygen. 7. The method of claim 1 or 6, wherein the resin film has a greater selectivity than the passivation layer and the gate insulating layer. The residual thickness of the resin film according to claim 1 or 7, wherein the residual thickness of the resin film is the following formula: (thickness of the protective film + gate insulating layer) * (selectivity of the protective film and the resin film) * (1 + over etching) Liquid crystal display manufacturing method characterized in that it is calculated as. 9. The method of manufacturing a liquid crystal display according to claim 8, wherein the protective film has a thickness of 200 to 4000 mm. The method of claim 1, wherein the resin film has a thickness of 2 μm or more. The method of claim 1, wherein the resin film comprises a photosensitive resin film.