KR20010011855A - method for manufacturing the TFT- LCD - Google Patents

Abstract

PURPOSE: A method of fabricating thin film transistor-liquid crystal display device is provided to reduce the number of masks necessary for the process of fabricating a thin film transistor. CONSTITUTION: The first resist pattern is formed by the exposure and the development using a gate defining mask. A gate electrode(12) is formed by the etching of a metal film in the resist pattern. A source and drain metal film(16) is patterned by using the second resist pattern as a mask. The second resist pattern is substituted for the third resist pattern and a channel layer(14a) is defined by the patterning of a doped semiconductor layer(15) and an amorphous silicon layer(14) by using the source and drain metal film(16) as a mask. Therefore, an active region, the source electrode(16a) and the drain electrode(16b) are defined by the active region defining mask and the number of masks necessary for the process of fabricating a thin film transistor is reduced.

Description

A method for manufacturing a thin film transistor-liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor-liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor-liquid crystal display device capable of manufacturing a thin film transistor with four masks.

In general, the active matrix liquid crystal display device among the liquid crystal display devices has high speed response and has a large number of pixels. As a result, the display screen has high characteristics such as high image quality, large size, and color screen, and is used in portable TVs, notebook PCs, automobile navigation systems, and the like.

In such an active matrix liquid crystal display device, a switching device such as a diode or a thin film transistor is disposed at the intersection of the gate bus line and the data bus line to selectively turn on / off the pixel electrode.

A conventional method of manufacturing a liquid crystal display device including the thin film transistor will be described with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a metal film for a gate bus line is deposited on a surface of an insulating substrate 1 to a predetermined thickness. Then, the metal film is patterned through the first photolithography process to form the gate electrode 2. Subsequently, the first gate insulating film 3, the second gate insulating film 4, the amorphous silicon layer 5, and the etch stopper layer 6 are sequentially deposited on the insulating substrate 1 including the gate electrode 2. do.

Thereafter, as shown in FIG. 1B, the etch stopper layer 6 is patterned to be present in the corresponding portion of the gate electrode 1 through the second photolithography process to form the etch stopper 6a. At this time, the etch stopper 6a, as is well known, prevents damage to the channel layer when forming the source and drain electrodes, thereby increasing the operating current of the thin film transistor and reducing the leakage current.

Next, as shown in FIG. 1C, the doped semiconductor layer 7 is deposited on the amorphous silicon layer 5 on which the etch stopper 6a is formed.

Next, referring to FIG. 1D, the doped semiconductor layer 7 and the amorphous silicon layer 5 are partially patterned by a third photolithography process to form the ohmic contact layers 7a and 7b and the channel layer 5 '. ). At this time, the ohmic contact layers 7a and 7b are patterned to exist on both sides of the etch stopper 6.

Subsequently, as shown in FIG. 1E, the first and second insulating layers 3 and 4 are etched by the fourth photolithography process so that the gate electrode pad portion outside the substrate may be exposed.

Then, as illustrated in FIG. 1F, a metal film for data bus lines is deposited on the lower substrate 1, and the metal film is etched through a fifth photolithography process to form an upper portion of the ohmic contact layers 7a and 7b. Source and drain electrodes 8a and 8b are formed.

However, in manufacturing the above-described conventional thin film transistor, there are at least five masks such as a gate electrode forming step, an etch stopper forming step, a channel layer forming step, a pad opening step, a source, and a drain forming step. Should proceed.

In this case, the mask designed to form the pattern is very expensive, and as the number of masks applied to the process increases, the cost of manufacturing the liquid crystal display device increases proportionally. Accordingly, it is urgent to reduce the number of masks in the current process.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor-liquid crystal display device which can reduce the number of masks used in the process and lower the manufacturing cost.

1A to 1F are cross-sectional views of respective processes for explaining a method of manufacturing a conventional thin film transistor-liquid crystal display device.

2A to 2F are cross-sectional views of respective processes for explaining a method of manufacturing a thin film transistor-liquid crystal display device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

11-insulated substrate 12-gate electrode

13-gate insulating film 14a-channel layer

15a-ohmic contact layer 16-metal film for source and drain electrodes

16a, 16b-source, drain electrode 17-second resist pattern

17-1-Third Resist Pattern 18-Protective Film

19-pixel electrode

In order to achieve the above object of the present invention, according to an embodiment of the present invention, forming a gate electrode on the insulating substrate; Sequentially depositing a gate insulating film, a doped semiconductor layer, and a source and drain metal film on the gate electrode; Forming an active resist pattern on the source and drain metal film to define an active region, wherein the active resist pattern has a relatively thin thickness of a portion corresponding to the gate electrode; Using the active resist pattern as a mask to etch a source, a drain metal film, a doped semiconductor layer, and an amorphous silicon layer in an active form to define a channel layer with the amorphous silicon layer; Removing a portion having a relatively thin thickness of the active resist pattern to form a resist pattern for a source and a drain electrode; Forming a source and a drain electrode by etching the source, the drain metal layer and the doped semiconductor layer using the resist pattern for the source and drain electrode; Removing the source and drain electrode resist patterns; Depositing a passivation layer on the substrate product; Etching the passivation layer to expose the drain electrode on the passivation layer; And forming a pixel electrode on the passivation layer to be in contact with the drain electrode.

The forming of the active resist pattern may include applying a photoresist film; Exposing a photoresist film using an active mask having a plurality of patterns smaller than an exposure limit in a portion corresponding to the gate electrode; And developing the exposed photoresist film.

In the present invention, the step of forming the source and drain electrode resist patterns is formed by re-exposure and development using the active mask.

According to the present invention, a thin film transistor and a pixel electrode can be formed with four masks, that is, a gate limiting mask, an active limiting mask, a drain electrode opening mask, and a pixel electrode limiting mask, and thus the number of masks can be reduced. have.

Accordingly, by reducing the number of masks, the manufacturing cost is reduced.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing a thin film transistor liquid crystal display according to the present invention.

First, as shown in FIG. 2A, a metal film for a gate electrode is deposited to a predetermined thickness on an insulating substrate 11, for example, on a transparent glass substrate. Subsequently, a photoresist film (not shown) is applied over the metal film, and then exposed and developed using a mask for defining a gate electrode to form a first resist pattern (not shown). The metal film is etched in the form of a resist pattern to form the gate electrode 12. The first resist pattern is then removed in a known manner.

Subsequently, a gate insulating film 13 made of a laminated film of a silicon nitride oxide film and a silicon nitride film is formed on the insulating substrate 11 on which the gate electrode 12 is formed. An amorphous silicon film 14, a doped amorphous silicon film 15, a source, and a drain metal film 16 are sequentially stacked on the gate insulating layer 13.

Next, as shown in FIG. 2B, a photoresist film is coated on the source and drain metal film 16, and the photoresist film is exposed and developed using a thin film transistor limiting mask, that is, an active mask. The resist pattern 17 is formed. In this case, a portion of the second resist pattern 17 corresponding to the gate electrode 12 is formed to have a relatively thin thickness. In order to form different thicknesses of the second resist pattern 17, fine patterns having a line width of less than or equal to a resolution limit (about 3 μm) are concentrated in a mask corresponding to a portion to be formed relatively thinly. Then, although the part is completely exposed and is not removed by the development afterwards, more light is applied as compared to the part completely shielded, so that the development has a relatively thin thickness.

Next, as shown in FIG. 2C, the exposed source and drain metal films 16 are patterned using the second resist pattern 17 as a mask. A relatively thin portion of the second resist pattern 17, that is, a portion corresponding to the gate electrode 12 is reexposed and developed to form the third resist pattern 17-1. That is, the second resist pattern is re-exposed and developed by the active mask.

Then, since the third resist pattern 17-1 is exposed and developed by a relatively thin portion of the second resist pattern 17, the third resist pattern 17-1 has a thickness smaller than that of the second resist pattern 17, and thus, the third resist pattern 17-3 is formed. By (17-1), a portion of the source and drain metal film 16 corresponding to the gate electrode 12 is exposed. In this case, the third resist pattern 17-1 is a mask on which the second resist pattern is formed, and is formed by exposure and development, so that a separate mask is not required.

Then, as shown in FIG. 2D, the exposed doped semiconductor layer 15 and the amorphous silicon layer, using the partially patterned source and drain metal film 16 as a mask, that is, in the form of a second resist pattern. Patterning 14, the channel layer 14a is defined. Accordingly, the active area is limited.

Then, as shown in FIG. 2E, the exposed source and drain metal films 16 and the doped semiconductor layer 15 are sequentially etched using the third resist pattern 17-1 as a mask. Source and drain electrodes 16a and 16b are formed. Accordingly, the thin film transistor is completed. In this case, during the process of forming the source and drain electrodes 16a and 16b by the third resist pattern 17-1, the channel layer 14a may be partially lost, and the doped semiconductor layer 15 may be It is patterned in the form of source and drain electrodes 16a and 16b to serve as an ohmic contact layer between the channel layer 14a and the source and drain electrodes 16a and 16b.

Thereafter, the protective film 18 is deposited on the substrate 11 on which the thin film transistor is formed. Subsequently, a fourth resist pattern (not shown) is formed on the passivation layer 18 so that the drain electrode 16b can be exposed, and then the passivation layer 18 is etched using the fourth resist pattern to drain. The electrode 16b is opened.

Then, as shown in FIG. 2F, an ITO film is deposited to contact the drain electrode 16b exposed on the resultant, and then patterned by a predetermined portion to form the pixel electrode 19.

In this way, the active limiting mask can be used to limit the active region, and to form the source and drain electrodes, thereby reducing one mask.

As described in detail above, according to the present invention, a thin film transistor and a pixel electrode can be formed of four masks, that is, a gate limiting mask, an active limiting mask, a drain electrode opening mask, and a pixel electrode limiting mask. The number of masks can be reduced more.

Accordingly, by reducing the number of masks, the manufacturing cost is reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Forming a gate electrode on the insulating substrate; Sequentially depositing a gate insulating film, a doped semiconductor layer, and a source and drain metal film on the gate electrode; Forming an active resist pattern on the source and drain metal film to define an active region, wherein the active resist pattern has a relatively thin thickness of a portion corresponding to the gate electrode; Using the active resist pattern as a mask to etch a source, a drain metal film, a doped semiconductor layer, and an amorphous silicon layer in an active form to define a channel layer with the amorphous silicon layer; Removing a portion having a relatively thin thickness of the active resist pattern to form a resist pattern for a source and a drain electrode; Forming a source and a drain electrode by etching the source, the drain metal layer and the doped semiconductor layer using the resist pattern for the source and drain electrode; Removing the source and drain electrode resist patterns; Depositing a passivation layer on the substrate product; Etching the passivation layer to expose the drain electrode on the passivation layer; And And forming a pixel electrode on the passivation layer to be in contact with the drain electrode. The method of claim 1, wherein the forming of the active resist pattern comprises: applying a photoresist film; Exposing a photoresist film using an active mask having a plurality of patterns smaller than an exposure limit in a portion corresponding to the gate electrode; And developing the exposed photoresist film. The method of claim 1, wherein the forming of the source and drain electrode resist patterns is performed by re-exposure and development using the active mask.