KR20040034918A - Switching method of transistor and switching circuit using the same - Google Patents

Abstract

PURPOSE: A switching method of a transistor and a switching circuit using the same are provided to switch the transistor by using a lower voltage range than an output voltage with only an N-type or a P-type transistor. CONSTITUTION: A gate voltage and a source voltage are differently changed by forming differently each capacitive coupling effect of a gate and a source of a switching transistor. A voltage difference between the gate voltage and the source voltage is larger than a threshold voltage of the transistor by increasing a variation of the gate voltage and reducing a variation of the source voltage. A supply voltage is applied to an output terminal by turning on the transistor and performing a bootstrapping operation.

Description

Transistor Switching Method and Switching Circuit Using the Same {SWITCHING METHOD OF TRANSISTOR AND SWITCHING CIRCUIT USING THE SAME}

The present invention relates to a switching method of a transistor and a switching circuit using the same.

In general, a transistor that is the basis of an electronic circuit serves as a switch that is the basis of a circuit, and based on this, signal output and logic operations are performed through a complementary MOS (CMOS) transistor using N-type and P-type transistors. Implement the circuit. In addition, these transistors have a wide range of applications, and are expanding their areas such as thin film transistors (TFTs).

1 is a circuit diagram of a conventional CMOS switching circuit, the principle of switching the N-type and P-type transistors with reference to this as follows.

In order to turn on the transistor, a voltage must be applied to the gate such that the magnitude of the applied voltage between the gate and the source is greater than the threshold voltage of the transistor. Therefore, in the case of the N-type transistor 1, in order to transfer the source voltage of -10V to the drain, a voltage of -8V or more higher than the -10V threshold voltage (assuming 2V) must be applied to the gate. In the case of the P-type transistor 2, in order to transfer the source voltage 10V to the drain, a voltage of 8V or less lowered by a threshold voltage (assuming 2V) from 10V should be applied to the gate. Due to this characteristic, in order to obtain a wider output range from an input having a narrow range, for example, -8V to 8V swing input, for example, -10V to 10V swing output, as shown in FIG. There is a need for a switching circuit of the type in which the -type transistor 2 is combined.

However, since the conventional CMOS switching circuit manufactures N-type and P-type transistors together, a large number of masks are required in the process, and an additional process is required to match the threshold voltages. This is a major cause of lowering process yields and increasing process costs, and can also lead to reproducibility problems with poor operation reliability of the circuit. Therefore, the implementation of a switching circuit using only N-type or P-type transistors is required.

2A and 2B are diagrams showing an example of a switching circuit using only one conventional P-type transistor, and FIGS. 3A and 3B are views showing an example of a switching circuit using only a conventional N-type transistor. .

If the circuit is configured using only one N-type or P-type transistor, the input swing range must be wider than the output swing range because the input requires a higher or lower input than the output value to obtain the desired output swing range. This occurs. For example, as shown in FIG. 2A, a swing output of -10V to 10V using only a P-type transistor will be described. In FIG. 2A, the 10V output is not a problem, but in order to output -10V, the gate input of the transistor T2 must be -12V. However, if the usable voltage range of the system is limited to -10V, it will not output -10V. Therefore, when -10V is input to the gate of the transistor T2, as shown in FIG. 2B, the output voltage of -8V is limited due to the threshold voltage.

As shown in FIG. 3A, the above-described problem occurs even when the circuit is configured using only N-type transistors. In this case, as shown in FIG. 3B, the output of 10V becomes a problem and only an output of about 8V is obtained. There is nothing but a problem.

Accordingly, an object of the present invention is to turn on a transistor even with an input signal having a voltage lower than an output voltage in the case of an N-type transistor by using capacitive coupling and boot-strapping. On, the P-type transistor provides a switching method of the transistor to turn on the transistor even with an input signal having a voltage higher than the output voltage.

Another object of the present invention is to provide a switching circuit capable of full swing with only one N-type or P-type transistor.

In order to achieve the above object, in the switching method of the transistor of the present invention, the capacitive coupling effect at the gate and the source of the transistor to be switched is different from each other so that the gate voltage is changed greatly, and the source voltage is changed small to The difference between the gate voltage and the source voltage is greater than or equal to the threshold voltage of the transistor, thereby turning on the transistor and delivering the power supply voltage to the output terminal by boot-strapping.

In addition, in order to achieve the above object, the switching circuit of the present invention comprises: first and second power supply terminals to which power is supplied; An output terminal; A first transistor having a source / drain current path formed between the first power supply terminal and the output terminal; A second transistor having a source / drain current path formed between the second power supply terminal and the output terminal, and a clock signal supplied to a gate; And a third transistor having a source / drain current path formed at a gate of the first transistor and the second power supply terminal, and a clock signal supplied to the gate, wherein a clock feed of the second transistor and the third transistor is performed. The turn-on of the first transistor is controlled by adjusting the voltage difference between the gate and the source of the first transistor by causing the through effect to be different.

Preferably, the first to third transistors are P-type transistors, and the second transistor has a longer channel length and a wider channel width than the third transistor.

More preferably, a source / drain current path is formed between the first power supply terminal and the gate of the first transistor, and further includes a fourth transistor supplied with an inverted clock signal to the gate.

1 is a circuit diagram of a conventional CMOS switching circuit,

2A and 2B are diagrams illustrating an example in which a switching circuit is configured using only a conventional P-type transistor;

3A and 3B illustrate an example in which a switching circuit is configured using only a conventional N-type transistor;

4A is a diagram for explaining capacitive coupling;

4B is a diagram for explaining boot-strapping,

5A to 5C are diagrams for describing an implementation principle of a switching circuit using a P-type transistor according to the present invention;

6 is a circuit diagram of a switching circuit according to a first embodiment of the present invention;

7 is a view showing simulation results for a switching circuit using a P-type transistor as a first embodiment of the present invention;

8A to 8C are diagrams for describing an implementation principle of a switching circuit using an N-type transistor according to the present invention;

9 is a circuit diagram of a switching circuit according to a second embodiment of the present invention;

10 is a circuit diagram of a switching circuit according to a third embodiment of the present invention;

Fig. 11 shows simulation results for the switching circuit of the third embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 11. Note that the same components in the drawings are represented by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

First, the technical principle of the present invention will be described.

The present invention uses capacitive coupling and boot strapping to turn on a transistor even with an input signal having a voltage lower than the output voltage in the case of an N-type transistor. In the case of a P-type transistor, the present invention relates to a technique of turning on a transistor even with an input signal having a voltage higher than an output voltage.

In capacitive coupling, the voltages at both ends influence each other by capacitance existing between voltage nodes. For example, as shown in FIG. 4A, either side is connected to a signal such as the clock CLK, and if the clock signal changes, the opposite voltage is affected and fluctuation occurs in the same waveform.

Boot-strapping is based on the phenomenon that when the gate of the transistor is electrically floating as shown in FIG. 4B, the gate voltage follows when the source / drain voltage is changed. It is a way to overcome the problem and turn on the transistors sufficiently. Such boot-strapping may be referred to as a method of using parasitic capacitance existing between the gate and the source, and the gate and the drain of the transistor. Such parasitic capacitances exist not only in general SOI MOSFETs but also in amorphous silicon TFTs and polysilicon TFTs, and artificial capacitors are connected as necessary to use boot-strapping and the like.

5A and 5C are diagrams for describing an implementation principle of a switching circuit using a P-type transistor according to the present invention.

Assuming that node A and node B have a lower voltage than the gate in the P-type transistor of FIG. 5A, the transistor is currently turned off. Here, node A (Vss) is a lower voltage than gate and node B and is assumed to be the lowest voltage in the system. The node A (Vss) is assumed to be the lowest voltage in the system. In this case, if the capacitive coupling condition is properly adjusted, the magnitude of the gate voltage and the voltage of the node B may be changed.

Referring to FIG. 5B, when the gate voltage is changed small and the voltage of the node B is changed greatly, and the difference is lower than the threshold voltage of the transistor, the transistor is turned on.

In this case, the gate and node B voltages may be electrically floating because the voltage is adjusted by capacitive coupling. Therefore, as shown in FIG. 5C, when the transistor is turned on and the voltage of the node A is transferred to the node B, the gate voltage electrically floated by the boot-strapping principle also follows the voltage change of the node B. As a result, when the voltage of node A is transferred to node B and the voltage of node B is lowered, the transistor is kept turned on because the gate voltage is also lowered by the boot-strapping effect. Therefore, the voltage of node A is transferred to node B as it is, and the voltage Vss of node A is output to the output terminal.

6 is a circuit diagram of a switching circuit according to a first embodiment of the present invention and shows an example implemented using only a P-type transistor.

In Fig. 6, the power supply voltage Vdd is connected to the drain of the P-channel thin film transistor (hereinafter simply referred to as a transistor) T1, and the source of the T1 transistor is connected to the output terminal through the node B. The drain of the T2 transistor is connected to the source of the T1 transistor, and the drain of the T3 transistor is connected to the gate of the T1 transistor. The clock signal CLK is supplied directly to the gates of the T2 transistor and the T3 transistor from an external device. At this time, the T2 transistor and the T3 transistor have different channel widths and channel lengths (W / L). This is to cause the feed-through effect (capacitive coupling effect) caused by the clock to be different so that the voltage difference between the gate and the source of the T1 transistor to be switched is larger than the threshold voltage. That is, the channel width and length of the T2 transistor are made larger than the channel width and length of the T3 transistor so that the feed-through effect is large in the T2 transistor and the feed-through effect is small in the T3 transistor.

Let's look at the operation of the switching circuit of the present invention having the configuration as described above. First, assume that the clock CLK outputs 0V and 5V as an output, and output a Vss voltage of node A -10V through this clock input. In FIG. 6, when the clock CLK is set to 0V, the T2 transistor is turned on and a 5V voltage is delivered to the output. In addition, since the T3 transistor is also turned on and the 5V voltage is transmitted to the gate of the T1 transistor, the T3 transistor supports the state in which the T1 transistor is turned off.

Now, when the clock CLK is changed from 0V to 5V, the T2 transistor is turned off and at the same time, the node B voltage of the T1 transistor is increased by 5V by the feed-through by the clock CLK. Let the voltage at this time be 5 + α. In the case of the T3 transistor, the gate voltage of the T1 transistor is also increased by 5 V by clock feed-through. Let the gate voltage at this time be 5 + β. Here, the floc feed-through effect shows that the T2 transistor, which has a relatively large channel width and length, is larger than the T3 transistor. As a result, the gate voltage of the transistor T1 is (5 + α)-(5 + β) lower than the node B voltage. If the difference is greater than the threshold voltage of the transistor T1, the transistor T1 is turned on. Therefore, the Vss power supply of node A connected to the T1 transistor is transferred to the node B through the channel of the T1 transistor, and the node B voltage begins to decrease. When the voltage of node B decreases due to the boot-strapping effect, the voltage of the floating gate terminal also decreases, so that the T1 transistor is continuously turned on. Vss = -10V) is delivered.

FIG. 7 is a diagram showing a simulation result of a switching circuit using a P-type transistor as a first embodiment of the present invention. In the figure, it can be seen that a -10V output O can be obtained with a clock CLK input I having a swing width of 0V to 5V. In order to output -10V using a conventional P-type transistor, the input should be lower than -10V.

On the other hand, the N-type transistor can be turned on by capacitive coupling in the same manner as in the case of the P-type transistor described above, in which the gate voltage is higher than the threshold voltage of the node B voltage. Turn the transistor on.

8A to 8C are diagrams for describing an implementation principle of a switching circuit using an N-type transistor according to the present invention.

In the N-type transistor of FIG. 8A, node A (Vdd) is higher than gate and node B and is the highest voltage in the system. Assuming that node A and node B have a higher voltage than gate, the current transistor is turned- It is off. Here, the gate and node B are given a signal by capacitive coupling so that the gate voltage and the node B voltage change. In this case, if the capacitive coupling condition is properly adjusted, the magnitude of the gate voltage and the voltage of the node B may be changed.

Referring to FIG. 8B, the gate voltage is greatly changed and the voltage of the node B is changed small so that the transistor is turned on when the difference is greater than or equal to the threshold voltage of the transistor.

In this case, the gate and node B voltages may be electrically floating because the voltage is adjusted by capacitive coupling. Therefore, as shown in FIG. 8C, when the transistor is turned on and the voltage of the node A is transferred to the node B, the gate voltage electrically floated by the boot-strapping principle also follows the voltage change of the node B. As a result, when the voltage of node A is transferred to node B while the voltage of node B is increased, the transistor keeps being turned on because the gate voltage is also increased due to the boot-strapping effect. Therefore, the voltage of node A is transferred to node B as it is, and the voltage Vdd of node A is output to the output terminal.

9 is a circuit diagram of a switching circuit according to a second embodiment of the present invention and shows an example implemented using only an N-type transistor.

In Fig. 9, the power supply voltage Vdd is connected to the drain of the P-channel thin film transistor (hereinafter simply referred to as a transistor) T1, and the source of the T1 transistor is connected to the output terminal through the node B. The drain of the T2 transistor is connected to the source of the T1 transistor, and the drain of the T3 transistor is connected to the gate of the T1 transistor. The clock signal CLK is supplied directly to the gates of the T2 transistor and the T3 transistor from an external device. At this time, the T2 transistor and the T3 transistor have different channel widths and channel lengths (W / L). This is to cause the feed-through effect (capacitive coupling effect) caused by the clock to be different so that the voltage difference between the gate and the source of the T1 transistor to be switched is larger than the threshold voltage. That is, the channel width and length of the T3 transistor are made smaller than the channel width and length of the T2 transistor so that the feed-through effect is small in the T3 transistor, and the feed-through effect is large in the T2 transistor.

Consider the operation of the N-type transistor switching circuit having the above configuration. First, assuming that the clock CLK outputs 5V and 0V, and outputs the Vdd voltage 10V of the node A through the clock input. Think about it. In FIG. 9, when the clock CLK is set at 5V, the T2 transistor is turned on and the Vs (0V) voltage is transmitted to the output. In addition, since the T3 transistor is also turned on and the voltage Vs (0V) is transmitted to the gate of the T1 transistor, the T3 transistor supports the state in which the T1 transistor is turned off.

In FIG. 9, the gate and node B voltage values of the T1 transistor are changed by using the clock feed-through effect that appears as the clock CLK changes from 5V to 0V. At this time, the gate and node B voltages of the T1 transistor are electrically floated. If the gate voltage is made higher than the threshold voltage of T1 above the voltage of the node B, the T1 transistor is turned on and the node is also bootstraped. A voltage (e.g. 10V) is delivered to node B.

10 is a circuit diagram of a switching circuit according to a third embodiment of the present invention, and shows an example implemented using only a P-type transistor. The difference between the switching circuit of this embodiment and the switching circuit of the first embodiment is that a T4 transistor that receives an inverted clock (CLK Bar) signal to the gate is added between the drain and the gate of the T1 transistor. In general, in the case of a thin film transistor, since the threshold voltage is relatively high at around 3V, the value of (5 + α)-(5 + β) should be 4V or more. Therefore, the effect of increasing the gate voltage of the T1 transistor at the 5V reference by the feed-through while the T3 transistor is turned off may be reduced to less than 5V. That is, the value of β should be small or negative. To this end, in the present invention, as illustrated in FIG. 10, a T4 transistor is added and an inverted clock signal CLKB is supplied.

The gate voltage (5 + β) of the T1 transistor is determined by the conflicting clock (CLK) feed-through effect of the T3 and T4 transistors, making the channel width and channel length of the T4 transistor larger than the channel width and length of the T3 transistor. Β value is adjusted in the negative direction. Therefore, (5 + β) is lower than 5 V (for example, 4 V), and as a result, (5 + α)-(5 + β) has a voltage difference of 5 V or more to facilitate turn-on of the T1 transistor. This method is also applicable to the case of using an N-type transistor.

11 is a diagram showing simulation results for the switching circuit of the third embodiment of the present invention. It can be seen that an improved switching result can be obtained as compared with FIG. 7 showing a simulation result of the switching circuit using the P-type transistor as the first embodiment of the present invention.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention enables the transistor to be switched using only the N-type or P-type transistor by using a voltage region below the output voltage. Therefore, when the circuit driving is subject to the limitation of having a fixed input range within the voltage range of the system, the COMS circuit can be implemented with only one type of transistor.

Claims (4)

The gate voltage is largely changed and the source voltage is changed small so that the capacitive coupling effects at the gate and the source of the transistor to be switched are different from each other so that the difference between the gate voltage and the source voltage is the threshold voltage of the transistor. The transistor is turned on by the size or more, and the switching method of the transistor characterized in that the power supply voltage is transferred to the output terminal by the bootstrapping. First and second power supply terminals to which power is supplied; An output terminal; A first transistor having a source / drain current path formed between the first power supply terminal and the output terminal; A second transistor having a source / drain current path formed between the second power supply terminal and the output terminal, and a clock signal supplied to a gate; And A third transistor having a source / drain current path formed at a gate of the first transistor and the second power supply terminal, and a clock signal supplied to the gate; Switching on the first transistor by adjusting the voltage difference between the gate and the source of the first transistor by causing the clock feed-through effect of the second transistor and the third transistor to be different from each other. Circuit. The switching circuit of claim 2, wherein the first to third transistors are formed of transistors of the same conductivity type, and the second transistor has a longer channel length and a wider channel width than the third transistor. . 4. The semiconductor device of claim 2, further comprising a fourth transistor configured to form a source / drain current path between the first power supply terminal and the gate of the first transistor, and to supply an inverted clock signal to the gate. Switching circuit, characterized in that.