KR20040033353A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor substrate and a method for manufacturing the same are provided to reduce resistance of wiring by using aluminum and prevent an undercut structure by not forming an aluminum layer where contact holes are formed. CONSTITUTION: Data wiring includes source electrodes, drain electrodes, data lines(171), and data pads(179) formed on an ohmic contact layer(161) in the same plane pattern as the ohmic contact layer. The data wiring is formed of double layers of a chrome pattern(711) and an aluminum pattern(712) except the data pads and the drain electrodes. The drain electrodes and an electrode(177) for maintenance capacity contacting with pixel electrodes are formed of a chrome mono layer each, and the data pads contacting with auxiliary pads are formed of a chrome mono layer.

Description

Thin film transistor substrate and manufacturing method thereof

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

A thin film transistor (TFT) substrate is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. In the lower substrate on which the thin film transistor is formed, wirings such as a gate line for supplying a scan signal to the thin film transistor and a data line for supplying an image signal are formed. However, as the liquid crystal display devices become larger and higher in size, the resistance of these wirings has become a problem. This problem is particularly acute for data lines carrying image signals. That is, when the resistance of the data line is large, signal distortion becomes severe due to the RC delay, and as the distance from the driver increases, the amount of charge charged to the pixel electrode decreases, resulting in a difference in luminance between the top and bottom of the panel, and flicker. ) Defects become severe.

Conventionally, chromium (Cr) is mainly used as a data line. This is because chromium is chemically relatively stable and can be prevented from being damaged by indium tin oxide (ITO) etchant in the pixel electrode formation process after forming the data line. However, chromium is a metal having a relatively high resistance. Cause.

Another method is to increase the deposition thickness of the chromium layer constituting the data line, but in this case, there is a limit because the stress on the panel increases, causing another defect.

A more improved method is to reduce the resistance of the wiring by forming an aluminum layer on the chromium layer, but aluminum is inferior in contact with the ITO forming the pixel electrode. Therefore, before depositing ITO on the protective layer, aluminum is removed from the exposed part through the contact hole of the protective layer, but when the aluminum layer is etched through the contact hole, an undercut structure is formed below the protective layer to deposit the ITO. Has a problem that is frequently disconnected inside the contact hole.

Accordingly, an object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same, in which aluminum is used as the main wiring to reduce the resistance of the wiring and at the same time, the undercut structure is not formed.

1A is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along lines Ib-Ib 'and Ic-Ic' of FIG. 1A.

2A to 7C are diagrams sequentially illustrating a manufacturing process of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

8A is a layout view of a thin film transistor substrate according to the second embodiment of the present invention.

FIG. 8B is a cross-sectional view taken along lines VIIIb-VIIIb 'and VIIIc-VIIIc' of FIG. 8A.

9A to 10B are diagrams for describing a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

11A is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 11B is a cross-sectional view taken along line XIb-XIb ′ of FIG. 11A.

※ Explanation of symbols on main parts of drawing ※

110 substrate 140 gate insulating layer

121: gate line 123: gate electrode

125: gate pad 131: sustain electrode line

133: sustain electrode 171: data line

173 Source electrode 175 Drain electrode

177: electrode for holding capacitance 179: date pad

180: protective layer 190: pixel electrode

A thin film transistor substrate for achieving the above object is a gate wiring including an insulating substrate, a gate line formed on the insulating substrate, a gate electrode which is part of the gate line, and a gate pad connected to one end of the gate line, and formed on the gate wiring. A resistive contact layer formed in the same planar pattern as the semiconductor layer except for a gate insulating layer, a semiconductor layer formed in a predetermined region on the gate insulating layer, and a predetermined region on the semiconductor layer, and the same as the resistive contact layer on the resistive contact layer. A source electrode, a drain electrode, a data line, a data line including a data pad, a data layer including a data pad, a protective layer including a contact hole exposing the drain electrode, and a contact layer formed on the protective layer. A pixel electrode connected to the drain electrode through the And, at least the data line of the data line and is made up of a first metal layer, second metal layer, the drain electrode is formed from only the first metal layer.

Here, the data line may further include a third metal layer formed on the second metal layer and having the same planar pattern as the first metal layer, wherein the second metal layer is formed to have a predetermined width smaller than that of the first metal layer and the third metal layer. It is preferably formed to be wrapped by the third metal layer.

The first metal layer and the third metal layer are preferably made of chromium, and the second metal layer is preferably made of aluminum.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method including forming a conductive layer on an insulating substrate and then patterning to form a gate wiring including a gate electrode, a gate line, and a gator pad, on the gate wiring. Forming a gate insulating layer, a non-conductive amorphous silicon layer, a conductive amorphous silicon layer, a first chromium layer, an aluminum layer, patterning the aluminum layer to form an aluminum pattern to cross the gate line, and forming a second chromium layer on the aluminum pattern Forming a photoresist layer on the second chromium layer and patterning the same to form a photoresist layer, leaving a first photoresist layer pattern on the gate electrode to define a first region, and a second thicker layer on the first data line than the first photoresist layer pattern. Leaving a photosensitive layer pattern to define a second region, and defining a region where the photosensitive layer pattern is not formed to a third region, a third Removing the second chromium layer and the first chromium layer, thereby exposing the conductive amorphous silicon layer, removing the first photosensitive layer pattern, and removing the conductive amorphous silicon layer and the non-conductive amorphous silicon layer of the third region. Forming a layer, and removing the second chromium layer and the first chromium layer of the first region so that the source electrode, the drain electrode, the data line, and the data pad are formed to have the same planar pattern as the semiconductor layer except for the predetermined region of the semiconductor layer. Forming a data wiring comprising: forming a resistive contact layer having the same planar pattern as the data wiring by removing the chromium layer and the conductive amorphous silicon layer in the first region, removing the second photosensitive layer pattern, data Forming a protective layer having a first contact hole exposing the drain electrode on the wiring; a pixel connected to the drain electrode through the first contact hole on the protective layer Forming an electrode.

The aluminum pattern is formed to be smaller than the first and second chromium patterns by a predetermined width so that the first and second chromium patterns surround the aluminum pattern. In addition, at least one of the drain electrode and the data pad may be formed of only the first and second chromium patterns, and the source electrode and the data line may be formed of the first and second chromium patterns and the aluminum pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1A is a layout view of a thin film transistor substrate according to the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib 'of FIG. 1A.

As illustrated, gate wirings 121, 123, and 125 are formed on the transparent insulating substrate 110. The gate lines 121, 123, and 125 are formed in one direction of the gate line 121, the gate electrode 123, which is a part of the gate line 121, and the gate pads formed at one end of the gate line 121. 125). The storage electrode line 131 is formed. The storage electrode line 131 overlaps with the storage capacitor electrode 177 connected to the pixel electrode 190, which will be described later, to form a storage capacitor that improves charge storage capability of the pixel.

A gate insulating layer 140 made of a material such as silicon nitride (SiNx) is formed on the gate lines 121, 123, and 125. The semiconductor layers 151, 154, 157, and 159 made of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 140, and phosphorus (or phosphorus) is formed on the semiconductor layers 151, 154, 157, and 159. An ohmic contact layer (161, 163, 165, 167, 169) formed of an amorphous silicon doped with n-type impurities or p-type impurities such as P) at a high concentration is formed.

The ohmic contacts 161, 163, 165, 167, and 169 are formed to have the same planar pattern except for a predetermined region of the semiconductor layer 154. The predetermined region is a channel region that forms a channel between the source electrode 173 and the drain electrode 175.

Data wirings 171, 173, 175, 179 having the same planar pattern as the ohmic contact layers 161, 163, 165, 167, and 169 on the ohmic contact layers 161, 163, 165, 167, and 169, and electrodes for the storage capacitors ( 177) is formed. The data wires 171, 173, 175, and 179 are formed at one end of the data line 171 and the data line 171 that cross the gate line 121 and define the pixel area, and receive image signals from the outside. The pad 179 includes a source electrode 173, which is a branch of the data line 171, and a drain electrode 175 positioned opposite to the source electrode 173 with a channel region therebetween.

A storage capacitor electrode 177 overlapping with the storage electrode line 131 to form a storage capacitor is formed. When the storage electrode line 131 is not formed, the storage capacitor electrode 177 is not formed.

In this case, except for the data pad 179 and the drain electrode 175, the data line is formed of a double layer of the chrome patterns 711 and 731 and the aluminum patterns 712 and 732. Since the data pad 179 and the drain electrode 175 are in contact with ITO, aluminum is removed. The storage capacitor electrode 177 is also formed of a single chromium layer. This is because the storage capacitor electrode 177 also contacts the pixel electrode 177.

The first contact hole 181 exposing the drain electrode 175, the second contact hole 182 exposing the gate pad 125, and the data pad 179 are disposed on the data wires 171, 173, 175 and 179. A protective layer 180 having a third contact hole 183 exposing and a fourth and fifth contact holes 184 and 185 exposing the storage capacitor electrode 177 are formed. The gate pads may be formed on the passivation layer 180 through the pixel electrodes 190 and the second contact holes 182 connected to the drain electrodes 175 through the first, fourth, and fifth contact holes 181, 184, and 185. An auxiliary gate pad 95 connected to 125 and an auxiliary data pad 97 connected to the data pad 179 through the third contact hole 183 are formed.

The pixel electrode 190 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and these materials have poor contact properties with aluminum. Accordingly, the drain electrode 175 connected to the pixel electrode 190, the storage capacitor electrode 177, and the data pad 175 contacting the auxiliary data pad 97 made of ITO are formed of chromium only.

The pixel electrode 190 overlaps the adjacent gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. The auxiliary gate pad 95 or the auxiliary data pad 97 does not necessarily play a role of supplementing adhesion with an external circuit device and protecting the pads 125 and 175, and application thereof is optional.

Next, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2C.

First, as shown in FIGS. 2A to 2C, a conductive layer is formed on the transparent insulating substrate 110 and then patterned to form gate wirings 121, 123, and 125.

The conductive layer is formed by depositing a metal in a thickness of 1,000 kPa to 3,000 kPa by a sputtering method. The conductive layer is patterned and formed by a photolithography process.

As shown in FIGS. 3A and 3C, the gate insulating layer 140, the amorphous silicon layer 150 which is not doped with impurities, the amorphous silicon layer 160 which is doped with impurities, are formed on the gate lines 121, 123, and 125. The chromium layer 701 and the aluminum layer are sequentially stacked. The aluminum layer is subjected to a photolithography process to form aluminum patterns 711 and 731.

As shown in FIGS. 4A and 4B, the photosensitive layers are formed on the aluminum patterns 711 and 731 and then patterned to form the photosensitive layer patterns PR.

In the photosensitive layer pattern, the first region A serving as the channel region is formed thinner than the second region B serving as the data wiring 171, 173, 175, and 179 or the storage capacitor electrode 177. The region except for the first region A and the second region B is a region in which the photosensitive layer pattern PR is not formed and is referred to as a third region C. FIG.

In this case, the thickness ratio of the photoresist layer pattern PR remaining in the first region C and the photoresist layer pattern remaining in the second region B may vary depending on the process conditions of the subsequent process. It is preferable to make the thickness of A) 1/2 of the thickness of the 2nd area | region B. FIG.

As such, there may be various ways of varying the thickness of the photosensitive layer pattern, and in order to control the light transmittance of each region, a slit, a lattice-shaped pattern is mainly used or a translucent film is used.

As shown in FIGS. 5A and 5B, the chromium layer 701 of the third region C is removed using the photosensitive layer pattern PR as a mask to expose the amorphous silicon layer 160 doped with impurities. Subsequently, the amorphous silicon layer 160 doped with impurities in the third region C and the amorphous silicon layer 150 not doped with impurities are etched together with the photosensitive layer pattern PR of the first region A. Referring to FIG. At this time, the semiconductor layers 151, 154, 157, and 159 are completed, and an ohmic contact layer 160A and a source / drain electrode 702 having no channel region separated are formed. At this time, the photosensitive layer pattern of the second region is also partially etched.

As shown in FIGS. 6A and 6C, the photosensitive layer residue left in the first region A is removed by ashing. The data line 171 or 173 including the aluminum patterns 711 and 731 and the chrome patterns 712, 732, 175, 177 and 179 by removing the chromium layer and the doped amorphous silicon layer of the first region A is removed. , 175, 179, and the storage capacitor electrode 177 are formed, and at the same time, the ohmic contacts 161, 163, 165, 167, and 169 are completed. The aluminum patterns 711 and 731 are not formed on the data pad 179, the drain electrode 175, and the storage capacitor electrode 177, which are portions where the contact holes are formed.

Thereafter, the photosensitive layer pattern of the second region B is removed. The photosensitive layer pattern of the second region B may be removed before the chromium layer of the first region A is etched.

As shown in FIGS. 7A and 7C, the protective layer 180 is formed on the data lines 171, 173, 175, and 179 and the storage capacitor electrode 177, and then etched using a photolithography process to form the first to first layers. Three contact holes 181, 182, and 183 are formed.

The first contact hole 181 exposes the drain electrode 175, the second contact hole 182 exposes the gate pad 125, and the third contact hole 183 exposes the data pad 179. When the storage capacitor electrode 177 is formed, the fourth contact hole 184 and the fifth contact hole 185 exposing the storage capacitor electrode 177 are further formed.

Finally, a transparent conductive material is deposited on the passivation layer 180 and then patterned to form a drain electrode 175, a storage capacitor electrode 177, and a pixel electrode through the first, fourth, and fifth contact holes 181, 184, and 185. The first connection port 190 connects the gate pad 125 and the auxiliary gate pad 95 through the second contact hole 182, and connects the auxiliary data pad 97 through the third contact hole 183. . (See FIGS. 1A and 1C)

Second Embodiment

8A is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along lines VIIIb-VIIIb 'and VIIIc-VIIIc' of FIG. 8A.

As shown in the figure, except for the data wirings 171, 173, 175, and 179 and the storage capacitor electrode 177, they are formed in the same structure. The data wires 171, 173, 175, and 179 may include first chromium patterns 711, 731, 751, and 791 made of chromium, aluminum patterns 712 and 732 made of aluminum, and second chromium patterns made of chromium. (713, 733, 752, 792).

In other words, the first chromium patterns 711, 731, 751, and 791 serving as barrier layers are formed, and the first chrome patterns 711 as main wirings on the first chromium patterns 711, 731, 751, and 791. , 731, 751, and 791 are formed with aluminum patterns 712 and 732 having a smaller width. As in the first embodiment, the aluminum pattern is not formed at the portion where the contact hole is formed.

The second chrome patterns 713, 733, 752, and 792 are formed to have the same planar pattern as the first chrome patterns 711, 731, 751, and 791. The second chrome patterns 713, 733, 752, and 792 cover the aluminum patterns 712 and 732 to prevent the aluminum patterns 712 and 732 from being damaged by being exposed to subsequent processes.

A method of forming a thin film transistor substrate having such a structure is as follows.

First, a gate wiring is formed on a substrate in the same manner as in the first embodiment, and a gate insulating layer, an amorphous silicon layer without doping impurities, an amorphous silicon layer doping with impurities, a first chromium layer 701, and aluminum are formed on the gate wiring. Form a layer.

9A to 9C, the aluminum layers are patterned to form aluminum patterns 712 and 732. The aluminum patterns 712 and 732 are formed to have a predetermined width smaller than the data lines 171, 173, 175 and 179 to be formed.

As shown in FIGS. 10A and 10B, a second chromium layer 702 is formed on the aluminum patterns 712 and 732. The photosensitive layer is formed on the second chromium layer 702 and then patterned to form the photosensitive layer pattern PR. The photosensitive layer pattern PR is formed in the same manner as in the first embodiment, and the subsequent steps are also the same as in the first embodiment. (See FIGS. 5A-7C)

Third Embodiment

11A is a layout view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along line XIb-XIb ′ of FIG. 11A.

As shown in FIGS. 11A to 11B, gate wirings 121, 123, and 125 are formed on the transparent insulating substrate 110. The gate wires 121, 123, and 125 are connected to one end of the gate line 121 and the gate line 121 that are formed to extend in the horizontal direction, and receive a gate signal from the outside and transfer the gate signal to the gate line 121. The pad 125 includes a gate electrode 123 that is a part of the gate line 121.

The gate insulating layer 140 is formed on the entire surface of the substrate including the gate wirings 121, 123, and 125.

On the gate insulating layer 140 corresponding to the gate electrode 123, the semiconductor layers 151 and 154 formed of a semiconductor material such as amorphous silicon and a semiconductor material such as amorphous silicon are doped with a high concentration of n-type impurities. The formed ohmic contacts 161, 163, and 165 are formed.

Data wires 171, 173, 175, 177, and 179 are formed on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140.

The data wires 171, 173, 175, and 179 are perpendicular to the gate line 121 to branch to the data line 171 and the data line 171 to define a pixel area, and are also connected to the ohmic contact layer 163. It is connected to one end of the source electrode 173 and the data line 171, and is separated from the data pad 179 and the source electrode 173 to which an image signal from an external source is applied. A drain electrode 175 formed over the opposing ohmic contact 165 of 173. In order to improve the storage capacitance, the storage capacitor electrode 177 overlapping the gate line 121 may be formed.

The data wirings 171, 173, 175, and 179 and the storage capacitor electrode 177 are formed in the same manner as in the first embodiment. That is, the data line is formed of a double layer of the chrome patterns 712 and 732 and the aluminum patterns 711 and 731 except for the data pad 179 and the drain electrode 175. Since the data pad 179 and the drain electrode 175 are in contact with ITO, the aluminum layer is removed. Since the storage capacitor electrode 177 is also in contact with the pixel electrode 190, the storage capacitor electrode 177 is formed only of the chromium single pattern 171.

A first contact hole 181 exposing the drain electrode 175 on the substrate, a second contact hole 182 exposing the gate pad 125, a third contact hole 183 exposing the data pad 125, The protective layer 180 having the fourth contact hole 184 exposing the storage capacitor electrode 177 is formed.

The pixel electrode 190 and the second contact hole 182 connected to the drain electrode 175 and the storage capacitor electrode 177 through the first and fourth contact holes 181 and 184, respectively, on the passivation layer 180. Auxiliary gate pad 95 is connected to the gate pad 125 and the auxiliary data pad 97 is connected to the data pad 179 through the third contact hole 183. The pixel electrode 190 may be formed to partially overlap the gate line 121 and the data line 171 to increase the aperture ratio, or may not be overlapped (not shown). In this case, in order to increase the aperture ratio, the pixel electrode 190 may be formed to overlap the data line 190 to form a protective layer 180 made of a low dielectric constant material, thereby forming a gap between the data line 171 and the pixel electrode 190. This is possible because signal interference can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, a part of the data line exposed by the contact hole may be formed only in the chrome pattern to improve the bonding property between the pixel electrode and the auxiliary data pad. In addition, although the etching ratio of aluminum and chromium is different when etching to form a contact hole in the related art, an undercut is not generated in the present invention since the aluminum layer is not formed in a portion where the contact hole is formed. In addition, aluminum can be used to reduce wiring resistance.

Claims (8)

Insulation board, A gate wiring including a gate line formed on the insulating substrate, a gate electrode which is a part of the gate line, and a gate pad connected to one end of the gate line; A gate insulating layer formed on the gate wiring; A semiconductor layer formed in a predetermined region on the gate insulating layer, An ohmic contact layer formed in the same planar pattern as the semiconductor layer except for a predetermined region on the semiconductor layer; A data line including a source electrode, a drain electrode, a data line, and a data pad formed on the ohmic contact layer in the same planar pattern as the ohmic contact layer; A protective layer formed on the data line and including a contact hole exposing the drain electrode; A pixel electrode formed on the protective layer and connected to the drain electrode through the contact hole; At least said data line of said data wiring consists of a 1st metal layer and a 2nd metal layer, The said drain electrode is formed from only the said 1st metal layer. In claim 1, The data line further includes a third metal layer formed on the second metal layer and having the same planar pattern as the first metal layer. In claim 2, The second metal layer is formed to have a predetermined width smaller than the first metal layer and the third metal layer, and is formed to be surrounded by the first and third metal layers. In claim 2, The first metal layer and the third metal layer are formed of chromium, and the second metal layer is formed of aluminum. In claim 1, And the data pad is formed of only the first metal layer. Forming and then patterning a conductive layer on the insulating substrate to form a gate wiring including a gate electrode, a gate line, and a gator pad, Forming a gate insulating layer, an amorphous silicon layer not doped with impurities, an amorphous silicon layer doped with impurities, a first chromium layer, and an aluminum layer on the gate wiring; Patterning the aluminum layer to form an aluminum pattern to intersect the gate line; Forming a second chromium layer on the aluminum pattern; After the photosensitive layer is formed on the second chromium layer, the photosensitive layer is patterned to leave a first photosensitive layer pattern on the gate electrode to define a first region, and a second photosensitive layer thicker than the first photosensitive layer pattern on the first data line. Defining a second region by leaving a layer pattern, and defining a region where the photosensitive layer pattern is not formed as a third region, Exposing the amorphous silicon layer doped with impurities by removing the second chromium layer and the first chromium layer of the third region; Forming a semiconductor layer by removing the first photosensitive layer pattern and simultaneously removing an amorphous silicon layer doped with impurities in the third region and an amorphous silicon layer not doped with impurities; A source electrode, a drain electrode, a data line, and a data pad to remove the second chromium layer and the first chromium layer of the first region to form the same planar pattern as the semiconductor layer except for the predetermined region of the semiconductor layer; Forming a data wiring, Removing the chromium layer and the amorphous silicon layer doped with the impurity in the first region to form an ohmic contact layer having the same planar pattern as the data line; Removing the second photosensitive layer pattern; Forming a protective layer having a first contact hole exposing the drain electrode on the data line; And forming a pixel electrode connected to the drain electrode through the first contact hole on the passivation layer. In claim 6, The aluminum pattern may be formed to be smaller than the first and second chromium patterns by a predetermined width so that the first and second chromium patterns surround the aluminum pattern. In claim 6, At least one of the drain electrode and the data pad is formed of only the first and second chromium patterns, and the source electrode and the data line are formed of the first and second chromium patterns and the aluminum pattern.