KR20040032665A - Control signal generating circuit and method for driver IC - Google Patents

Abstract

PURPOSE: A circuit and a method for generating the control signal for a driver integration circuit are provided to reduce the power consumption by performing one time or a predetermined times of scan operation during the write/read operation when the write/read control signal and the scan control signal are enabled at the same time. CONSTITUTION: A circuit for generating the control signal for a driver integration circuit includes a write/read enable signal generation circuit(10), a first scan signal generation circuit(12), a second scan generation circuit(14) and a third scan generation circuit(16). The write/read enable signal generation circuit(10) generates the write/read enable signal in response to the write/read control signal. The first scan signal generation circuit(12) generates the first scan signal in response to the scan control signal. The second scan generation circuit(14) generates a second scan signal having a phase opposite to that of the write/read enable signal during the enable period of the first scan signal. And, the third scan generation circuit(16) generates a second scan signal satisfying the scan enable time margin among the second scan signals as the third scan signal.

Description

Control signal generating circuit and method for driver integrated circuit

TECHNICAL FIELD The present invention relates to driver integrated circuits, and more particularly, to control signal generation circuits and methods for driver integrated circuits.

A driver integrated circuit for driving a display element of a display panel, such as a conventional liquid crystal display panel, includes a graphic memory for storing graphic data and a control signal generating circuit for generating a control signal for controlling the graphic memory.

The control signal generation circuit of the conventional driver integrated circuit generates a write / lead enable signal in response to the write / lead control signal and generates a scan enable signal in response to the scan control signal. When the write / lead control signal and the scan control signal are simultaneously generated, the control signal generation circuit of the conventional driver integrated circuit masks the scan enable signal generated internally and applies it to the graphics memory, and the write / lead enable signal Is applied as is to graphic memory. Accordingly, the graphic memory of the conventional driver integrated circuit performs the write / read operation first in response to the write / lead enable signal and then performs the scan operation in response to the scan enable signal. This masks the scan enable signal because write / read data is lost when masking the write / lead enable signal.

1 is a block diagram showing the configuration of a control signal generation circuit of a conventional driver integrated circuit, wherein a write / lead enable signal generation circuit 10, a first scan signal generation circuit 12, and a second scan signal generation circuit are shown in FIG. It consists of (14).

The function of each of the blocks shown in FIG. 1 will be described below.

The write / lead enable signal generation circuit 10 generates the write / lead enable signal WEN / REN in response to the write / lead control signal WCON / RCON. The first scan signal generation circuit 12 generates the first scan enable signal SEN1 in response to the scan control signal SCON. The second scan signal generation circuit 14 masks the first scan enable signal SEN1 when the write / lead enable signal WEN / REN and the first scan enable signal SEN1 are generated at the same time. A second scan enable signal SEN2 is generated which is enabled at the disable time of the enable signal WEN / REN.

FIG. 2 is an operation timing diagram for explaining the operation of the block diagram shown in FIG.

The write / lead enable signal generation circuit 10 generates the write / lead enable signal WEN / REN in response to the write / lead control signal WCON / RCON. The first scan signal generation circuit 12 generates a scan enable signal SEN in response to the scan control signal SCON. As shown in the timing diagram, the enable time of the scan enable signal is longer than the enable time of the write / lead enable signal. For example, when the write / read time is 50ns and the display time of one line is 12500ns, the scan operation for one line is repeatedly performed 250 times while the 250 write / read operations are performed. The second scan signal SEN2 enabled by the second scan signal generation circuit 14 at the disable time of the write / lead enable signal WEN / REN when the first scan signal SEN1 is at the "low" level. Will occur). As shown in the timing diagram, the write / lead enable signal WEN / REN and the second scan signal SEN2 are shifted in time.

However, as described above, when the control signal generation circuit of the conventional driver integrated circuit generates the second scan signal SEN2, power consumption is increased because the scan operation for one line is repeatedly performed for several tens to several hundred times. There was a problem. That is, as described above, since the driver integrated circuit repeatedly performs a scan operation for one line 250 times, power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control signal generation circuit for a driver integrated circuit which can reduce power consumption by limiting the scan operation for one line when the write / lead enable signal and the scan enable signal are simultaneously generated. have.

Another object of the present invention is to provide a control signal generation method for a driver integrated circuit for achieving the above object.

A first aspect of the control signal generation circuit for a driver integrated circuit of the present invention for achieving the above object is a write / read enable signal generating means for generating a write / read enable signal in response to the write / read control signal, scan First scan signal generating means for generating a first scan signal in response to a control signal, and a second scan signal having a phase opposite to the write / lead enable signal in an enable period of the first scan signal; Scan signal generation means and a third scan signal generation means for inputting the second scan signal to generate the second scan signal as a third scan signal that satisfies the scan enable time margin among the second scan signals; Characterized in that.

A second aspect of the control signal generation circuit for a driver integrated circuit of the present invention for achieving the above object is a write / read enable signal generation means for generating a write / read enable signal in response to the write / read control signal, scan First scan signal generating means for generating a first scan signal in response to a control signal, and a second scan signal having a phase opposite to the write / lead enable signal in an enable period of the first scan signal; And third scan signal generation means for inputting the second scan signal and generating the second scan signal as a third scan signal generated a predetermined number of times of the second scan signal.

A first aspect of the control signal generation method for a driver integrated circuit of the present invention for achieving the above another object is a write / read enable signal generation step of generating a write / read enable signal in response to the write / read control signal, Generating a first scan signal in response to a scan control signal; generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; A second scan signal generating step and a third scan signal generating step of inputting the second scan signal to generate the second scan signal as a third scan signal satisfying a scan enable time margin among the second scan signals; It is characterized by including.

A second aspect of the control signal generation method for a driver integrated circuit of the present invention for achieving the above another object is a write / read enable signal generation step of generating a write / read enable signal in response to the write / read control signal, Generating a first scan signal in response to a scan control signal; generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; And a second scan signal generating step, and a third scan signal generating step of inputting the second scan signal to generate the second scan signal, which is generated a predetermined number of times of the second scan signal, as a third scan signal. .

1 is a block diagram showing the configuration of a control signal generation circuit of a conventional driver integrated circuit.

FIG. 2 is an operation timing diagram for explaining the operation of the block diagram shown in FIG.

3 is a block diagram of a control signal generation circuit for a driver integrated circuit of the present invention.

FIG. 4 is a block diagram of an embodiment of the third scan signal generation circuit shown in FIG.

FIG. 5 is a block diagram of an embodiment of the mask enable signal generation circuit shown in FIG.

6 is an operation timing diagram for explaining the operation of the control signal generation circuit of the driver integrated circuit shown in FIGS.

Hereinafter, a control signal generation circuit and method for a driver integrated circuit of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a block diagram of a control signal generation circuit for the driver integrated circuit of the present invention, in which a third scan signal generation circuit 16 is added to the control signal generation circuit of FIG.

The function of each of the blocks shown in FIG. 3 will be described below.

Since the functions of the write / lead enable signal generation circuit 10, the first scan signal generation circuit 12, and the second scan signal generation circuit 14 are the same as those of the blocks of the same reference numerals and symbols shown in FIG. See the explanation in 1.

The third scan signal generation circuit 16 selects only two second scan signals SEN2 within the enable time of the first scan signal SEN1 and generates the third scan signal SEN3.

FIG. 4 is a block diagram of an embodiment of the third scan signal generation circuit shown in FIG. 3, and is composed of a mask enable signal generation circuit 20, a reset signal generation circuit 22, and a multiplexer 24. As shown in FIG.

The function of each of the blocks shown in FIG. 4 is as follows.

The mask enable signal generation circuit 20 is reset in response to the reset signal RESETB and counts in response to the second scan signal SEN2, so that the mask enable signal of the "high" level is counted while counting 1 and 2. MEN). The reset signal generation circuit 22 inverts the first scan signal SEN1 to generate a reset signal RESETB. The multiplexer 24 supplies the power supply voltage VDD level while the mask enable signal MEN of the "low" level is generated, and the second scan signal (Men) while the mask enable signal MEN of the "high" level is generated. SEN2 is generated as the third scan signal SEN3.

In FIG. 4, the mask enable signal generation circuit 20 generates the mask enable signal MEN having a “low” level by the reset signal RESETB generated from the reset signal generation circuit 22. The mask enable signal generation circuit 20 may be configured to generate a mask enable signal MEN having a "low" level by the scan signal SEN1. In this case, the reset signal generation circuit 22 may not be additionally provided.

FIG. 5 is a block diagram of an embodiment of the mask enable signal generation circuit shown in FIG. 4, and is composed of a 2-bit counter 30 and an exclusive OR gate 32. As shown in FIG.

The function of each of the blocks shown in FIG. 5 will be described below.

The 2-bit counter 30 is reset in response to the reset signal RESETB, counts in response to the transition from the "high" level of the second scan signal SEN2 to the "low" level, and outputs the 2-bit output signal CNT1, 2) occurs. That is, the 2-bit counter 30 counts sequentially in response to the second scan signal SEN2 to generate the output signals CNT1 and 2 of "00", "01", "10", and "11". The exclusive OR gate 32 generates a mask enable signal MEN having a "low" level when an output signal of "00" and "11" is generated from the 2-bit counter 30, and "01" and "10". When the output signal is generated, the mask enable signal MEN of the "high" level is generated.

6 is an operation timing diagram for explaining the operation of the control signal generation circuit of the driver integrated circuit shown in FIGS.

The write / lead enable signal WEN / REN, the first scan signal SEN1, and the second scan signal SEN2 are generated as shown in the timing diagram of FIG.

The reset signal generation circuit 22 inverts the first scan signal SEN1 to generate a reset signal RESETB. The mask enable signal generation circuit 20 counts in response to the transition from the "high" level to the "low" level of the second scan signal SEN2, and the output signals CNT1 and 2 of the counter 30 are " In the case of 01 "and" 10 ", the mask enable signal MEN of the" high "level is generated, and in the case of" 00 "and" 11 ", the mask enable signal MEN of the" low "level is generated. . The multiplexer 24 generates the third scan signal SEN3 of the power supply voltage level in response to the mask enable signal MEN of the "low" level, and in response to the mask enable signal MEN of the "high" level. The second scan signal SEN2 is generated as the third scan signal SEN3.

The control signal generation circuit of the driver integrated circuit of the present invention shown in FIGS. 3 to 6 performs the write / read operation when the write / read enable signal WEN / REN and the first scan signal SEN1 are simultaneously generated. In this case, the third scan signal SEN3 is enabled twice so that only two scan operations are performed, thereby reducing power consumption.

Although the above-described embodiment shows that the second scan signal is generated as the third scan signal, the second scan signal may be generated as the third scan signal once or a predetermined number of times.

That is, the control signal generation circuit of the conventional driver integrated circuit masks the first scan signal SEN1 when the write / lead enable signal WEN / REN and the first scan signal SEN1 are simultaneously generated. The second scan signal SEN2 is enabled at a timing shifted from the read enable signal WEN / REN. Accordingly, since the second scan signal SEN2 is enabled several tens to hundreds of times, the scan operation for one line is repeatedly performed for several tens to hundreds of times, thereby increasing power consumption.

However, the control signal generation circuit of the present invention masks the first scan signal SEN1 to generate a second scan signal that is enabled and shifted out of the enable time of the write / lead enable signal WEN / REN. Of the two scan signals, only one or a predetermined number of second scan signals satisfying the scan enable time margin are selected to be generated as the third scan signal SEN3. Therefore, power consumption is reduced because a scan operation for one line is performed once or a predetermined number of times.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The control signal generating circuit and the method of the driver integrated circuit of the present invention provide power by allowing one or a predetermined number of scan operations to be performed while the write / read operation is performed when the write / read control signal and the scan control signal are simultaneously enabled. The consumption is reduced.

Claims (11)

Write / lead enable signal generating means for generating a write / lead enable signal in response to the write / lead control signal; First scan signal generating means for generating a first scan signal in response to a scan control signal; Second scan signal generating means for generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; And And a third scan signal generating means for inputting the second scan signal to generate a second scan signal as a third scan signal that satisfies a scan enable time margin among the second scan signals. Control signal generation circuit of an integrated circuit. The method of claim 1, wherein the third scan signal generating means A mask enable signal generation circuit that is reset in response to the first scan signal and generates a mask enable signal that is enabled during counting once in response to the second scan signal; And And a selection circuit for generating the second scan signal as the third scan signal in response to the mask enable signal. The method of claim 1, wherein the third scan signal generation circuit A reset signal generation circuit for inputting the first scan signal to generate a reset signal; A mask enable signal generation circuit that is reset in response to the reset signal and generates a mask enable signal that is enabled during counting once in response to the second scan signal; And And a selection circuit for generating the second scan signal as the third scan signal in response to the mask enable signal. The method of claim 2 or 3, wherein the mask enable signal generation circuit is A counter reset in response to the first scan signal and counting in response to the second scan signal; And And a logic gate for combining the output signal of the counter to generate the mask enable signal. Write / lead enable signal generating means for generating a write / lead enable signal in response to the write / lead control signal; First scan signal generating means for generating a first scan signal in response to a scan control signal; Second scan signal generating means for generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; And And a third scan signal generating means for inputting the second scan signal to generate the second scan signal, which is generated a predetermined number of times of the second scan signal, as a third scan signal. Circuit. The method of claim 5, wherein the third scan signal generating means A mask enable signal generation circuit that is reset in response to the first scan signal and generates a mask enable signal that is enabled while counting a predetermined number of times in response to the second scan signal; And And a selection circuit for generating the second scan signal as the third scan signal in response to the mask enable signal. The method of claim 5, wherein the third scan signal generation circuit A reset signal generation circuit for inputting the first scan signal to generate a reset signal; A mask enable signal generation circuit that is reset in response to the reset signal and generates a mask enable signal that is enabled while counting a predetermined number of times in response to the second scan signal; And And a selection circuit for generating the second scan signal as the third scan signal in response to the mask enable signal. A write / lead enable signal generation step of generating a write / lead enable signal in response to the write / lead control signal; Generating a first scan signal in response to the scan control signal; A second scan signal generating step of generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; And And a third scan signal generating step of generating the second scan signal as a third scan signal by satisfying the scan enable time margin among the second scan signals by inputting the second scan signal. Method of generating a control signal of an integrated circuit. The method of claim 8, wherein the third scan signal generation step A mask enable signal generation step of generating a mask enable signal that is reset in response to the first scan signal and is enabled during counting once in response to the second scan signal; And And a selecting step of generating the second scan signal as the third scan signal in response to the mask enable signal. The method of claim 8, wherein the third scan signal generation step A reset signal generation step of generating a reset signal by inputting the first scan signal; A mask enable signal generation step of generating a mask enable signal that is reset in response to the reset signal and is enabled during counting once in response to the second scan signal; And And a selecting step of generating the second scan signal as the third scan signal in response to the mask enable signal. A write / lead enable signal generation step of generating a write / lead enable signal in response to the write / lead control signal; Generating a first scan signal in response to the scan control signal; A second scan signal generating step of generating a second scan signal having a phase opposite to that of the write / lead enable signal in an enable period of the first scan signal; And And generating a third scan signal to generate the second scan signal as a third scan signal by inputting the second scan signal and generating the second scan signal generated a predetermined number of times of the second scan signal. Way.