KR20040031287A - Semiconductor memory device having means for protecting degradation of characteristics of row precharge time - Google Patents

Abstract

PURPOSE: A semiconductor memory device for preventing the deterioration of the row precharge time(tRP) characteristics is provided to prevent the deterioration of the tRP characteristics with employing the negative word line(NWL) structure. CONSTITUTION: A semiconductor memory device for preventing the deterioration of the row precharge time(tRP) characteristics includes a memory cell, a word line(WL), a sub-word line driver(13), a plurality of control circuits(13,15,17). The word line(WL) is connected to the memory cell. The sub-word line driver(13) discharges the word line(WL) in response to a first control signal and precharges the word line(WL) in response to a second control signal. The control circuits(13,15,17) generate the first control signal and the second control signal. The control circuits(13,15,17) include a first inverter, a second inverter and a third inverter. The first inverter outputs the first control signal by inverting the input signal, the second inverter inverts the input signal and the third inverter outputs the second control signal by inverting the output of the second inverter in response to the third control signal.

Description

Semiconductor memory device having means for protecting degradation of characteristics of row precharge time}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a negative word line (NWL) structure and having a means for preventing tRP (low precharge time) characteristics.

In DRAM, a negative word line (NWL) structure is employed to improve various characteristics and reduce chip area. However, when the NWL structure is adopted, the slope of the word line becomes smoother than when the NWL is not employed, and thus, the tRP (low precharge time) characteristic is deteriorated.

Therefore, while adopting the NWL structure, there is a need for a means to prevent the deterioration of tRP characteristics.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device employing an NWL structure and having a means for preventing tRP deterioration.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram of a semiconductor memory device having a means for preventing a tRP characteristic degradation according to an embodiment of the present invention.

FIG. 2 shows the discharge waveform WL1 of the word line and the threshold voltage of the NMOS transistor 44 when the threshold voltage of the NMOS transistor 44 of the first control circuit 14 is lower than that of other NMOS transistors. In the case of the other NMOS transistors, the discharge waveform WL2 of the word line is illustrated.

3 is a diagram showing a waveform diagram of the input signal PXI when the falling slope control circuit 17 is employed.

In accordance with an aspect of the present invention, a semiconductor memory device includes a memory cell, a word line connected to the memory cell, and a discharge of the word line in response to a first control signal and a response to a second control signal. And a subword line driver for precharging the word line, and a control circuit for receiving an input signal and generating the first control signal and the second control signal.

In particular, the control circuit may include a first inverter outputting the first control signal by inverting the input signal, a second inverter inverting the input signal, and an output signal of the second inverter in response to a third control signal. And a third inverter for inverting the second control signal and outputting the second control signal. Among the NMOS transistors of the third inverter, an NMOS transistor connected to a gate thereof has a threshold voltage compared to other NMOS transistors. It is characterized in that it is formed low.

The semiconductor memory device according to an embodiment of the present invention may further include a falling slope control circuit connected to a line through which the input signal is transmitted and rapidly descending the input signal.

The falling slope control circuit may include a first PMOS transistor to which a power supply voltage is applied to a source, and a control signal is applied to a gate, and a line to which a drain of the first PMOS transistor is connected to a source and the input signal is transmitted to a gate. A second PMOS transistor connected to a drain, a first NMOS transistor connected to a drain of the second PMOS transistor, a control signal applied to a gate, and a ground voltage applied to a source, and the input signal transferred to a drain And a second NMOS transistor connected to a gate thereof, a drain of the second PMOS transistor connected to a gate thereof, and a ground voltage applied to a source.

According to another aspect of the present invention, there is provided a semiconductor memory device including a memory cell, a word line connected to the memory cell, and discharge of the word line in response to a first control signal. A subword line driver that precharges the word line in response, a control circuit that receives an input signal and generates the first control signal and the second control signal, and a line to which the input signal is transmitted and the input signal Equipped with a descending slope control circuit to quickly create a descending slope of the.

The control circuit inverts the output signal of the second inverter in response to a first inverter for inverting the input signal and outputting the first control signal, a second inverter for inverting the input signal, and a third control signal. And a third inverter outputting the second control signal, wherein an NMOS transistor having a third control signal connected to a gate of the NMOS transistors of the third inverter has a threshold voltage compared to other NMOS transistors. It is characterized by being formed low.

The falling slope control circuit may include a first PMOS transistor to which a power supply voltage is applied to a source, and a control signal is applied to a gate, and a line to which a drain of the first PMOS transistor is connected to a source and the input signal is transmitted to a gate. A second PMOS transistor connected to a drain, a first NMOS transistor connected to a drain of the second PMOS transistor, a control signal applied to a gate, and a ground voltage applied to a source, and the input signal transferred to a drain And a second NMOS transistor connected to a gate thereof, a drain of the second PMOS transistor connected to a gate thereof, and a ground voltage applied to a source thereof.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a circuit diagram of a semiconductor memory device having a means for preventing a tRP characteristic degradation according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device according to an embodiment of the present invention may include a memory cell array 11 including a plurality of memory cells, a sense amplifier block 12, a subword line driver 13, and a first word. A control circuit 14, a second control circuit 15, a negative word line enable circuit 16, and a falling slope control circuit 17 are provided.

The subword line driver 13 discharges the word line WL to the back bias voltage VBB level in response to the first control signal PXIB and the word line WL in response to the second control signal PXID. Precharge to a boosted voltage (VPP) level. The word line WL is connected to the memory cells in the memory cell array 11. The subwordline driver 13 includes NMOS transistors 31-34.

The first control circuit 14 receives the input signal PXI and generates a first control signal PXIB and a second control signal PXID. The first control circuit 14 inverts the input signal PXI and outputs the first control signal PXIB. The first inverter 41 outputs the first control signal PXIB, and the second inverter 42 and the third inverter inverts the input signal PXI. And a third inverter 43 for inverting the output signal of the second inverter 42 in response to the control signal CT to output the second control signal PXID. An internal power supply voltage VCCA is used as the power supply voltage of the first inverter 41, and a boost voltage VPP higher than the internal power supply voltage VCCA is used as the power supply voltages of the second inverter 42 and the third inverter 43. This is used.

In particular, the NMOS transistor 44 in which the third control signal CT is connected to the gate among the NMOS transistors constituting the third inverter 43 has a lower threshold voltage Vth than other NMOS transistors. .

The negative word line enable circuit 16 generates a negative word line enable signal NWEI in response to a row address RADD applied from the outside. The negative word line enable circuit 16 includes a NAND gate 61, a PMOS transistor 62, and an NMOS transistor 63.

The falling slope control circuit 17 is connected to the line through which the input signal PXI is transmitted and makes the falling slope of the input signal PXI fast, that is, in response to the control signal CNT. The falling slope control circuit 17 is preferably disposed near the top edge of the memory cell array 11, which is the end of the line through which the input signal PXI is transmitted.

The falling slope control circuit 17 includes a first PMOS transistor 71 to which a boosted voltage VPP is applied to a source, and a control signal CNT is applied to a gate, and a drain of the first PMOS transistor 71 to a source. Is connected to the second PMOS transistor 72 connected to the line to which the input signal PXI is transmitted to the gate, and the drain of the second PMOS transistor 72 is connected to the drain, and the control signal CNT is applied to the gate. A first NMOS transistor 73 to which a ground voltage VSS is applied to a source, a line to which an input signal PXI is transmitted to a drain, and a drain of the second PMOS transistor 72 are connected to a gate thereof. A second NMOS transistor 74 is provided to which a ground voltage VSS is applied to the source.

Referring to FIG. 1, the charge of the word line WL during the discharge operation is performed through the NMOS transistor 44 up to the threshold voltage Vth level of the NMOS transistor 44 of the first control circuit 14. Exit to ground (VSS). Next, at a level lower than the threshold voltage Vth of the NMOS transistor 44, the charge of the word line WL is applied to the NMOS transistor 32 of the subword line driver 13 and the NMOS of the second control circuit 15. After exiting through the transistor 52, the level of the word line WL finally becomes the back bias voltage VBB level.

However, in the manufacturing process of the general semiconductor memory device, the threshold voltage Vth of all the NMOS transistors including the NMOS transistor 44 of the first control circuit 14 is about 1 Volt. As a result, when the level of the word line WL is about 1 volt, the NMOS transistor 32 of the subword line driver 13 and the NMOS transistor 52 of the second control circuit 15 become discharge paths. The falling slope of the line WL signal becomes very gentle, resulting in poor tRP (low precharge time) characteristics.

However, in the semiconductor memory device according to the present invention, as described above, the threshold voltage of the NMOS transistor 44 of the first control circuit 14 is about 0.3 volts lower than that of other NMOS transistors. As a result, the charge of the word line is discharged through the NMOS transistor 44 of the first control circuit 14, and thus the falling slope of the word line WL signal is increased.

FIG. 2 shows the discharge waveform WL1 of the word line and the threshold voltage of the NMOS transistor 44 when the threshold voltage of the NMOS transistor 44 of the first control circuit 14 is lower than that of other NMOS transistors. In the case of the other NMOS transistors, the discharge waveform WL2 of the word line is illustrated. As can be seen in Figure 2 it can be seen that WL1 is faster down slope than WL2.

In FIG. 1, the turn-on time of the NMOS transistor 32 of the subword line driver 13 and the NMOS transistor 52 of the second control circuit 15 is determined by the rising point of the first control signal PXIB. do. In other words, the faster the rising point of the first control signal PXIB is, the faster the turn-on time of the NMOS transistor 32 and the NMOS transistor 52 becomes, and accordingly, the falling slope of the word line WL signal is faster.

However, as described above, the semiconductor memory device according to the present invention is connected to the line through which the input signal PXI is transmitted, and the falling slope control circuit which rapidly inclines the falling slope of the input signal PXI in response to the control signal CNT. (17) is provided. As a result, as illustrated in FIG. 3, the falling slope of the input signal PXI is accelerated by the falling slope control circuit 17, and thus, the rising point of the first control signal PXIB is increased, so that the word line WL is eventually used. D) The slope of the signal becomes faster.

Therefore, the semiconductor memory device according to the present invention has an advantage that the tRP characteristic is not degraded while employing the NWL structure.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device according to the present invention has an advantage that the tRP characteristic is not deteriorated while employing the NWL structure.

Claims (5)

Memory cells; A word line connected to the memory cell; A subword line driver configured to discharge the word line in response to a first control signal and to precharge the word line in response to a second control signal; And A control circuit for receiving an input signal and generating the first control signal and the second control signal; The control circuit, A first inverter outputting the first control signal by inverting the input signal; A second inverter for inverting the input signal; And A third inverter outputting the second control signal by inverting the output signal of the second inverter in response to a third control signal, The NMOS transistor having the third control signal connected to a gate of the NMOS transistors of the third inverter has a lower threshold voltage than other NMOS transistors. The method of claim 1, And a falling slope control circuit connected to a line through which the input signal is transmitted and rapidly descending the input signal. The method of claim 2, wherein the falling slope control circuit, A first PMOS transistor to which a source voltage is applied to the source and a control signal is applied to the gate; A second PMOS transistor having a source connected to a drain of the first PMOS transistor and a line through which the input signal is transmitted to a gate; A first NMOS transistor having a drain connected to the drain of the second PMOS transistor, a control signal applied to a gate, and a ground voltage applied to a source; And And a second NMOS transistor connected to a line to which the input signal is transmitted to a drain, a drain of the second PMOS transistor to a gate, and a ground voltage applied to a source. Memory cells; A word line connected to the memory cell; A subword line driver configured to discharge the word line in response to a first control signal and to precharge the word line in response to a second control signal; A control circuit for receiving an input signal and generating the first control signal and the second control signal; And A falling slope control circuit connected to a line through which the input signal is transmitted and rapidly descending the input signal; The control circuit, A first inverter outputting the first control signal by inverting the input signal; A second inverter for inverting the input signal; And A third inverter outputting the second control signal by inverting the output signal of the second inverter in response to a third control signal, The NMOS transistor having the third control signal connected to a gate of the NMOS transistors of the third inverter has a lower threshold voltage than other NMOS transistors. The method of claim 4, wherein the falling slope control circuit, A first PMOS transistor to which a source voltage is applied to the source and a control signal is applied to the gate; A second PMOS transistor having a source connected to a drain of the first PMOS transistor and a line through which the input signal is transmitted to a gate; A first NMOS transistor having a drain connected to the drain of the second PMOS transistor, a control signal applied to a gate, and a ground voltage applied to a source; And And a second NMOS transistor connected to a line to which the input signal is transmitted to a drain, a drain of the second PMOS transistor to a gate, and a ground voltage applied to a source.