JP3016998B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a control circuit for controlling a word line potential during an acceleration test in which a voltage higher than normal is applied.

[0002]

2. Description of the Related Art In sorting semiconductor memory devices, an accelerated test (also referred to as a BT test; BT: burn-in test) is performed in order to remove products that may cause an initial failure. At this time, high temperature and high voltage are usually used as a means for creating the acceleration state, but in the present specification, it means high voltage application. Thus, in an acceleration test of a semiconductor memory device, even if a high voltage is applied to a power supply terminal, only a selected word line on a memory cell is applied with a high voltage.

FIG. 4 is a block diagram showing a general configuration of a word line drive circuit of a semiconductor memory device. In FIG. 1, reference numeral 1 denotes a high voltage generation circuit for receiving a high voltage enable signal RAE and generating a row address high voltage signal RAV;
Receives the first row decoder signals WPE1 to WPEj and generates the preceding word line drive signals WPL1 to WPLj from the row address high voltage signal RAV, and 3a outputs the second row decoder signals WLE1 to WLEj.
i, the word line drive signals WL1 to WLi (WPL in this specification)
1 to WPLj also mean the first word line, and WL1
To WLi also indicate word lines) (the other word line driving signals WP for the other stages).
L2 to WPLj are similarly input to another post-stage word line drive circuit and processed into word line drive signals, but illustration and description of the other post-stage word line drive circuits are omitted. ).

The preceding word line driving circuit 2 and the succeeding word line driving circuit 3a are connected to a row decoder for decoding a row address signal and are configured to receive an output signal thereof. At this time, the row decoder connected to the preceding word line drive circuit decodes the upper bits of the row address, and the row decoder connected to the subsequent word line drive circuit 3a decodes the lower bits of the row address.
The word lines WL1 to WLi of the memory array are connected to the subsequent word line driving circuit 3a, and the memory cells (not shown) connected to each word line are connected to the latter word line driving circuit 3a via the word lines. Driven by

FIG. 5 is a circuit diagram showing a configuration of the latter word line drive circuit 3a in FIG. As shown in FIG.
The second row decoder output signal WLEk (k = 1, 2,...,
i) is input to the inverter IVk and one end of an n-channel MOS transistor Nka whose gate is connected to the V _CC power supply. The other end of the transistor Nka is an n-channel M
The output terminal of the inverter IVk is connected to the gate of the OS transistor Nkb, and the output terminal of the inverter IVk is connected to the gate of the n-channel MOS transistor Nkc.
And the transistor Nkc are connected in series between the preceding word line WPL1 and the ground, and a connection point between the two transistors is connected to the word line WLk. Note that the preceding word line driving circuit 2 shown in FIG.
It has the same circuit configuration as.

Next, the operation of the word line drive circuit shown in FIGS. 4 and 5 will be described. Power supply voltage V _{CC of the} circuit is 5V
It is assumed that Prior to the word line selection, when the high voltage generation enable signal RAE is activated, the high voltage generation circuit 1 generates a 7.5 V row address high voltage signal RAV. The preceding word line drive circuit 2 transmits RAV to the preceding word line WPLm (m = 1, 2,..., J) selected by the first row decoder output signals WPE1 to WPEj. Now, assuming that WPL1 is selected (first
Assuming that row decoder output signal WPE1 attains a high level), approximately 7.5 V is applied to previous word line WPL1.
Appears. The subsequent word line drive circuit 3a transmits the preceding word line drive signal WPL1 to the word line WLk (k = 1, 2,..., I) selected by the second row decoder output signals WLE1 to WLEi. Now, assuming that the word line WL1 is selected (the second row decoder output signal WL
Assuming that E1 has gone high), the word line W
Approximately 7.5 V appears at L1, and the gates of the memory cells connected to this word line are simultaneously opened. When the second row decoder output signal WLE1 falls to a low level, the transistor N1b turns off, and the output signal of the inverter IV1 goes high, turning on the transistor N1c. Therefore, the potential of word line WL1 is reduced to the ground potential. In synchronization with this, the high voltage signal RAV and the preceding word line drive signal WPL1 also fall to the ground potential.

During the accelerated test, the word line driving circuits 2 and 3a perform almost the same operation. At the time of the acceleration test, the acceleration test signal BT input to the high voltage generation circuit 1 is at a high level. As a result, when the enable signal RAE is activated, the high voltage generation circuit 1
Generate AV. This high voltage RAV is transmitted to the preceding word line WPLm and the word line WLk via the preceding word line driving circuit 2 and the succeeding word line driving circuit 3a, but when the high voltage RAV is increased to 12V, the source of the MOS transistor is increased. The preceding word line drive signals WPL1 to WPLj rise only up to 10.5 V due to the breakdown occurring between the drain diffusion layer and the p-well.
The high level of the word line drive signals WL1 to WLi also remains at 10.5V. That is, an acceleration voltage of 10.5 V is applied to the word line during the acceleration test. Then, as in the normal operation, the decoder output signals WPE1 to WPE
j, the potential of the word line drops to the ground potential when WLE1 to WLEi are deselected.

FIG. 6 shows a potential transition of a preceding word line and a word line during an acceleration test in a conventional semiconductor memory device. Here, in order from the word line WL1, WL2, WL3,.
And activated. First, the preceding word line WPL
1 is increased to the accelerated test potential V _CC + α (10.5 V). Next, the potential of the word line WL1 is raised to V _CC + α, and after a certain period of time, the potentials of the preceding word line WPL1 and the word line WL1 become the ground potential. At this time, the RAV generated by the high voltage generation circuit 1 also drops to the ground potential. Hereinafter, similarly, the word lines WL2 and WL3 are sequentially raised to the accelerated test potential and returned to the ground potential.

[0009]

In the above-described conventional acceleration test, the acceleration voltage applied to each word line is limited to one time when a word line is selected. Stay for a short time. Thus, the acceleration state in the acceleration test is predicted to be proportional to ΔV × T (where ΔV is the difference between the acceleration voltage and the normal applied voltage, and T is the acceleration voltage application time). , 1
Since T per word line becomes extremely short, in order to perform acceleration effectively, it is necessary to perform acceleration over a long time or ΔV
Must be raised. However, as described above, it is impossible to raise the potential of the word line to a certain level or more because junction breakdown occurs. However, on the other hand, p which is normally applied negatively
Set the well to 0
Some attempts have been made to increase the breakdown voltage, but this has its limitations. Further, increasing the voltage of the acceleration test to a certain level or more exceeds the range of the acceleration test, and ΔV × T
Is not preferable because the degree of acceleration cannot be predicted.

Therefore, an object of the present invention is to lengthen the time during which a high voltage is applied to each word line, so that an acceleration test of a semiconductor memory device can be performed in a short time. That is. Another object of the present invention is to make it possible to avoid applying an excessively high voltage so that the acceleration can be stably performed and to quantitatively determine the degree of the acceleration.

[0011]

To achieve the above object, according to the present invention, during normal operation, the potential of a selected word line is set to the first level, and at the time when the selection is completed, the potential of the word line is set. In a semiconductor memory device in which electric charges are drawn and the potential is set to a second level, when a high voltage is applied in an acceleration test, a third level higher than the first level, which is formed by a high voltage generating circuit provided therein, is used. Is applied to the selected word line, and when the word line is not selected, the charge extracting operation for the word line performed during the normal operation is stopped to bring the word line into a floating state ,
A semiconductor memory device characterized by maintaining the word line at a high potential is provided. More specifically, the semiconductor memory device according to the present invention has a normal operation word line drive voltage during normal operation and an acceleration test formed by the high voltage generation circuit (1) during the acceleration test that is higher than the normal operation word line drive voltage. When a word line drive signal line (W
, PL1, WPL2,..., WPLi) and ground.
The OS transistors (N1b, N2b,..., Nib) and the second MOS transistors (N1c, N2c,.
c) are connected in series with the first MOS transistor as the word line drive signal line side, the connection point of both transistors is connected to word lines (WL1, WL2,..., WLi), and the row decoder output signal (WLE1) is connected. , WLE2, ...,
WLEi) is connected to the gate of the first MOS transistor, and the row decoder output signals (WLE1, WLE2,.
, WLEi) and the acceleration test signal (BT) are input to the NOR gates (NR1, NR2,..., NRi) and the word line drive circuit (3) is connected to the gate of the second MOS transistor. Wherein the first MOS transistor is rendered conductive when the row decoder output signal is activated, and the second MOS transistor is rendered non-conductive when the row decoder output signal or the acceleration test signal is activated. .

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a word line driving circuit according to one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a configuration of a subsequent word line driving circuit 3 in FIG. In FIG. 1, the same reference numerals are given to the same parts as those in the conventional example in FIG. 4, and thus the duplicated description will be omitted. The acceleration test signal BT is input. Details of the latter word line drive circuit will be described with reference to FIG.

As shown in FIG. 2, the gate of the second row decoder output signal WLEk (k = 1, 2,..., I) is V _CC.
N-channel MOS transistor Nka connected to power supply
And one input terminal of the NOR gate NRk. The acceleration test signal BT is commonly input to the other input terminal of the NOR gate NRk. Transistor Nka
Is connected to the gate of n-channel MOS transistor Nkb, and the output terminal of NOR gate NRk is connected to the gate of n-channel MOS transistor Nkc. The transistor Nkb and the transistor Nkc are connected in series between the preceding word line WPL1 and the ground, and a connection point of both transistors is connected to the word line WLk.

The acceleration test signal BT is normally at a low level,
This is a signal that goes high during an acceleration test. During normal operation, that is, when BT is at a low level, each NOR gate operates as an inverter, so that the operation of the subsequent word line drive circuit shown in FIG. 2 is not different from that of the conventional example shown in FIG. When the BT goes high during the acceleration test, the output signals of the NOR gates NR1 to NRi become the second signals.
It goes low regardless of the value of the row decoder output signal WLEk. Therefore, the transistors N1c to Nic are always off, and each word line is in a floating state when not selected.

Now, assuming that word lines WL2 and WL3 are selected in order from word line WL1 in the latter word line driving circuit of FIG. 2, as shown in FIG.
The potential of L1 becomes V _CC + α (10.5 V), and subsequently the potential of the word line WL1 also becomes V _CC + α. After a certain time, the word line WL1 is deselected and the previous word line WP
The level of L1 also becomes low, but the word line WL1 keeps the potential of V _CC + α because the transistor N1c that pulls the charge of the word line to the ground is off. Next, the word line WL2 is selected, an acceleration test voltage (V _CC + α) is applied, but then is not selected continues to hold the high voltage. Hereinafter, similarly, the word lines are sequentially selected, and the high voltage is maintained even after the non-selection. By continuing this series of operations, a plurality of word lines can be simultaneously held at a high potential.

The above operation is performed for a specific block or for all the memory cell arrays of the memory device. By the way, since a word line is left in a floating state after being deselected, its holding voltage gradually decreases due to a leak current. In order to avoid this, it is desirable that after selecting all the predetermined word lines, the first word line is selected again, and this is repeated as many times as necessary. Thus, a predetermined plurality of word lines or all the word lines can be constantly maintained at a high voltage during the accelerated test.

While the preferred embodiment has been described above,
The present invention is not limited to the above embodiments,
Various modifications are possible within the gist of the present invention described in the claims. For example, in the embodiment, the word line driving circuit is divided into two stages, a former stage and a latter stage. However, this can be changed to one stage or three or more stages.

[0018]

As described above, in the semiconductor memory device of the present invention, the transistor for lowering the potential of the word line to the ground level when the word line is deselected during the normal operation is set in the floating state during the acceleration test. Therefore, according to the present invention, each word line can hold a high voltage at the time of selection even after being deselected, and simultaneously set a plurality of word lines to a high potential. Will be able to do it. Thus, according to the present invention,
The time for applying the acceleration voltage to the word lines can be shortened as a whole semiconductor memory device. For example, if the potentials of the 128 word lines are simultaneously raised to a high potential, the time for applying stress to the word lines can be reduced to 1/128.

According to the present invention, it is not necessary to apply an excessively high voltage to perform an effective acceleration test, and the acceleration test time can be set arbitrarily. Prediction is easier, and the degree of acceleration is easier to control. Further, according to the present invention,
Then, the word line can be selected even during the accelerated test.
Perform acceleration tests in word line units or block units.
Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of a word line driving circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a subsequent word line drive circuit in the embodiment of FIG.

FIG. 3 is an explanatory diagram of the operation of the embodiment circuit shown in FIG. 2;

FIG. 4 is a block diagram of a conventional word line drive circuit.

FIG. 5 is a circuit diagram of a subsequent word line drive circuit in a conventional example.

6 is an operation explanatory diagram of the conventional circuit shown in FIG. 5;

[Explanation of symbols]

Reference Signs List 1 high voltage generation circuit 2 front word line drive circuit 3, 3a rear word line drive circuit BT acceleration test signal RAE high voltage generation enable signal RAV row address high voltage signal WPE1-WPEj first row decoder output signal WLE1-WLEi second row Decoder output signal WPL1 to WPLj Previous word line or previous word line drive signal WL1 to WLi Word line or word line drive signal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (3)

(57) [Claims] In a semiconductor memory device, during a normal operation, the potential of a selected word line is set to a first level, and when the selection is completed, the charge of the word line is drawn to set the potential to a second level. When a high voltage is applied in an acceleration test, a third-level potential higher than the first level, which is formed by a high-voltage generating circuit provided inside, is applied to a selected word line, and when the word line is not selected, the word line and floating state stops the charge pull-out operation for said word lines to be performed during normal operation, the word
A semiconductor memory device characterized in that a storage line is maintained at a high potential . 2. A word line drive signal line to which a first level potential is applied during a normal operation and a third level potential higher than the first level during an acceleration test, and a point to which a second level potential is applied. Between the first MOS transistor and the second MOS
A transistor is connected in series with the first MOS transistor as the word line drive signal line side, a connection point of both transistors is connected to the word line, and a row decoder output signal is input to the gate of the first MOS transistor; NO to which row decoder output signal and acceleration test signal are input
A word line driving circuit in which an output signal of an R gate is input to a gate of a second MOS transistor;
Wherein the MOS transistor is turned on when the row decoder output signal is activated, and the second MOS transistor is turned off when the row decoder output signal or the acceleration test signal is activated. apparatus. 3. The semiconductor memory device according to claim 1, wherein a part or all of the word lines are repeatedly selected at a constant period when a high voltage is applied in the acceleration test.