KR20040027214A - Liquid crystal display having a pixel including a plurality of subpixels - Google Patents

Abstract

PURPOSE: An LCD device having pixels consisting of many sub pixels is provided to combine other portions of sub pixels with other sub pixels, and to apply a data voltage having the same polarity to one pair of sub pixels that cross each other, thereby improving picture quality. CONSTITUTION: Many display signal lines are connected to an LCD plate assembly(300). Many pixels are arrayed in matrix type. The display signal lines include many gate lines for transmitting gate signals and data lines for transmitting data signals. The gate lines are extended in row direction, and are parallel with each other. The data lines are extended in column direction, and are parallel with each other. The display signal lines include many storage electrode lines to which predetermined voltages such as common voltages are applied. Each storage electrode line is located between the gate lines, and is extended in row direction, being parallel with each other.

Description

A liquid crystal display having a pixel composed of a plurality of subpixels {LIQUID CRYSTAL DISPLAY HAVING A PIXEL INCLUDING A PLURALITY OF SUBPIXELS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a pixel composed of a plurality of subpixels.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Among these liquid crystal displays, TN (twisted nematic) liquid crystal displays have various advantages, but they have limitations in extending their range to monitors or TVs due to viewing angle problems. For this reason, in order to improve the viewing angle of the TN liquid crystal display, a series of achievements have been shown through many studies such as the development of a multi-domain method or the development of a new compensation film. However, the problem of gray level reversal still remains in the up and down directions, especially when viewed from the bottom.

In particular, in the case of a multi-domain liquid crystal display device, the gamma curve on the front side and the gamma curve on the side surface do not coincide with each other, thus showing inferior visibility on the left and right sides as compared with a conventional TN liquid crystal display device. For example, in the case of PVA (patterned vertically aligned) method, which cuts out by domain dividing means, the screen is brighter and the color tends to move toward the white side toward the side, and in severe cases, there is no difference in luminance between high grays. It also occurs when the image looks clumped.

The technical problem to be achieved by the present invention is to solve this problem.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one subpixel in a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 3.

5 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 5.

7 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 8A is a cross-sectional view of the liquid crystal panel assembly of FIG. 7 taken along the line 'a-'a'.

FIG. 8B is a cross-sectional view of the lower panel of the liquid crystal panel assembly of FIG. 7 taken along the line 'b-'b'.

9 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 10 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 9.

11 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 12 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 11.

13 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 14 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display shown in FIG. 13.

15 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

16A, 16B, and 16C are cross-sectional views of the lower panel of the liquid crystal panel assembly of FIG. 15 taken along lines XVIa-XVIa ', XVIb-XVIb', and XVIc-XVIc ', respectively.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of first signal lines, a plurality of second signal lines, and a plurality of pixels connected to the first signal line and the second signal line. . Each pixel includes a plurality of subpixels each including a switching element connected to one of the first signal lines and one of the second signal lines, wherein the subpixels are arranged in a matrix form. The pixel is capacitively coupled with other subpixels, and at least some of the subpixels are bi-coupled with other subpixels.

At least another part of the subpixels may be cross-linked with another subpixel,

According to an embodiment of the present invention, the first and second signal lines are not disposed between the subpixels coupled to each other. In this case, the subpixels include red, green, and blue subpixels, and the subpixels coupled to the second heat are red and green subpixels.

According to an embodiment of the present invention, at least some of the blue subpixels are co-coupled, and the data voltages applied to the pair of sub-columns coupled to each other have the same polarity. In this case, the data voltages applied to the pair of blue subpixels coupled in the same column may have opposite polarities.

The second signal line may be disposed between the two sub-coupling sub-pixels, and the sub-pixels of each pixel are capacitively coupled to sub-pixels of different columns.

According to an embodiment of the present invention, at least another part of the subpixels is co-coupled with another subpixel, and a data voltage having the same polarity is applied to a pair of subpixels that are capacitively coupled.

A liquid crystal display according to another exemplary embodiment of the present invention may include a plurality of gate lines formed on the substrate, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of pairs of thin films connected to the gate lines and the data lines. A plurality of pixel electrodes connected to the transistor, the thin film transistors and arranged in a matrix form, and connected to one of the pixel electrodes, and overlapping the other one of the pixel electrodes with an insulator to form a first coupling capacitor. And a plurality of first coupling members, wherein the coupling capacitors are formed between pixel electrodes of different columns.

The first coupling member may be formed of the same layer as the gate line, and the first coupling member may cross the data line.

The first coupling member may not cross the data line, and the plurality of second coupling members may be connected to one of the pixel electrodes and overlap the other one of the pixel electrodes with an insulator to form a second coupling capacitor. It may further include.

The second coupling member may be formed of the same layer as the data line, and the first coupling member and the second coupling member may cross each other.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one subpixel in a liquid crystal display according to an embodiment of the present invention, and FIG. An equivalent circuit diagram of a liquid crystal panel assembly in the liquid crystal display device according to the embodiment.

As shown in FIG. 1, the liquid crystal display according to the present invention includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected thereto. In addition, a driving voltage generator 700 connected to the gate driver 400 and a gray voltage generator 800 connected to the data driver 500 and a signal controller for controlling the driving voltage generator 700 are connected to the gate driver 400. And 600.

Referring to FIGS. 1 and 3, the liquid crystal panel assembly 300 is connected to a plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and SL in an equivalent circuit, and is in a substantially matrix form. It includes a plurality of pixels arranged.

The display signal lines (G ₁ -G _n , D ₁ -D _m , SL) are a plurality of gate lines (also called "scan signal lines") that carry gate signals (also called "scanning signals"). (G ₁ -G _n ) and a data line (also called an "image signal line") (D ₁ -D _m ) that carries a data signal (also called an "image signal"). . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and they are also substantially parallel to each other.

The display signal lines G ₁ -G _n , D ₁ -D _m , SL may also be provided with a plurality of common voltages (V _com ) (also called "reference voltages"). A storage electrode line SL is included. Each storage electrode line SL is positioned between the gate lines G ₁ -G _n and substantially extends in the row direction, and is substantially parallel to each other. This storage electrode line SL may be omitted.

One pixel is defined by one gate line G ₁ -G _n and one data line D ₁ -D _m , for example, (i, j) (i = 1, 2, ..., n, j = 1, 2, ..., m) means a pixel connected to the i-th gate line G _i and the j-th data line D _j .

As shown in FIG. 3, each pixel P _i and _j has two subpixels ( , ), And each subpixel ( , ) Is a switching element Q ₁ , Q ₂ connected to the corresponding gate line G _i and the corresponding data line D _j , and a liquid crystal capacitor C _LC1 , C _LC2 connected thereto; Storage capacitors C _ST1 , C _ST2 . The storage capacitors C _ST1 and C _ST2 can be omitted, in which case the storage electrode line SL is also unnecessary.

The switching elements Q ₁ , Q ₂ are three-terminal elements whose control terminals are connected to the gate lines G ₁ -G _n , the input terminals are connected to the data lines D ₁ -D _m , and the output terminals are liquid crystals. It is connected to one terminal of capacitors C _{LC1 and} C _LC2 and holding capacitors C _{ST1 and} C _ST2 .

The liquid crystal capacitors C _LC1, C _LC2 are between the switching elements Q ₁ , Q ₂ and the common voltage V _com , and the holding capacitors C _ST1, C _ST2 are held with the switching elements Q ₁ , Q ₂ . It is connected between the electrode lines SL. When the storage electrode line SL is not present, the storage capacitors C _{ST1 and} C _ST2 may be connected to adjacent gate lines G _{1 to} G _n .

In a planar arrangement, one subpixel is allocated to one region partitioned by an adjacent gate line G ₁ -G _n and a storage electrode line SL, and two adjacent data lines D ₁ -D _m . The subpixels are arranged in a matrix. Conversely, any one of the gate lines G ₁ -G _n and the storage electrode lines SL is disposed between adjacent subpixel rows, and one data line D ₁ -D _m is disposed between the adjacent subpixel columns. It is arranged. The number of subpixel rows is twice the number of gate lines, but since the number of subpixel columns is about the same as the number of data lines, "subpixel columns" and "pixel columns" are used in the same meaning in the future.

The subpixels of each pixel _Pi and _j , ) Are positioned opposite to each other with respect to the corresponding gate line G _i . The sub-pixels in each pixel line hatching are all connected to the same gate line (G ₁ -G _n), a gate line (G ₁ -G _n) sub-pixels of the hatched pixel rows adjacent to both sides of all the gate lines (G ₁ - G _n ). For example, sub-pixels of two rows located above the hatch i-th gate line (G _i) directly below in Figure 3 are all connected to the same gate line (G _i). Therefore, in the present specification, the i-th pixel row means two sub-pixel rows connected to the i-th gate line G _i .

In contrast, the subpixels of each pixel _Pi and _j ( , ) Is located on the same side with respect to the data line D _j . The subpixels of the pixels connected to one gate line G ₁ -G _n are all positioned on the same side with respect to the data line D ₁ -D _m . However, one of the data lines (D ₁ -D _m) pixels of the sub-pixels of the pixel portion are connected to the data lines (D ₁ -D _m) is located on one other sub-pixel of the pixel portion of the are located on the other side. In other words, the subpixels of some of the pixels of one subpixel column are connected to the data lines D ₁ -D _m located on the left side, and the subpixels of the remaining pixels are positioned on the right side of the data line (D). D ₁ -D _m ).

In FIG. 3, pixels are arranged such that relative positions of the data lines D _{1 to} D _m are changed in units of two pixels. For example, among the pixels connected to the j-th data line D _j , the subpixels of the pixels P _{i-1, j} , P _{i, j} ( , , , ) To the data line (located to the right of the D _j), the sub-pixels of the pixel _{(P i + 1, j,} P i + 2, j) ( , , , ) Is on the left.

The upper pixel of each pixel (P _i , _j ) ) And the subpixel below ( ) Are each connected up and down by a neighboring subpixel row with a coupling capacitor (C _pp ). In FIG. 3, each subpixel is combined with a neighboring subpixel below or above the same subpixel column. For example, the upper subpixel of the pixels P _i and _j ( ) Is a sub _- pixel (P _i-1 , _j ) ) And the coupling capacitor (C _pp ) ) Is the upper subpixel of the pixels P _{i + 1} , _{j + 1} ) And a coupling capacitor (C _pp ). Thus, capacitive coupling between subpixels of the same pixel string is referred to as "column coupling" from now on.

Meanwhile, the liquid crystal panel assembly 300 may be schematically illustrated as shown in FIG. 2. For convenience, only one subpixel is shown in FIG. 2.

As shown in FIG. 2, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 therebetween. The lower panel 100 includes a gate line G _i , a data line D _j , a switching element Q1, and a storage capacitor C _ST . The liquid crystal capacitor C _LC has two terminals, a pixel electrode 190 of the lower panel 100 and a common electrode (also referred to as a “reference electrode”) 270 of the upper panel 200 as two terminals, and two electrodes 190 and 270. The liquid crystal layer 3 in between functions as a dielectric.

The pixel electrode 190 is connected to the switching element Q ₁ , and the common electrode 270 is formed on the entire surface of the upper panel 200 and is connected to the common voltage V _com .

Herein, the liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode 190 and the common electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The pixel electrode 190 overlaps the storage electrode line SL to form a storage capacitor C _ST , and is connected to a neighboring pixel electrode through a coupling capacitor C _pp . In addition, the pixel electrode 190 and / or the common electrode 270 may have a plurality of cutouts or protrusions formed on the electrodes 190 and 270. In this case, the viewing angle may be improved by the fringe field.

FIG. 2 shows a MOS transistor as an example of the switching element Q ₁ , which is implemented as a thin film transistor using amorphous silicon or polysilicon as a channel layer in an actual process. . Therefore, the lower display panel 100 is referred to as a "thin film transistor display panel".

Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 are linearly formed.

On the other hand, in order to implement color display, each pixel should be able to display a color, which is provided with a color filter 230 of red, green, or blue in a region corresponding to each pixel electrode 190. It is possible by doing. Since the color filter 230 is mainly formed in a corresponding region of the upper panel 200 as shown in FIG. 2, the upper panel 200 is referred to as a “color filter panel”. However, the color filter 230 may be formed on or under the pixel electrode 190 of the lower panel 100.

Returning to Figure 1, the driving voltage generator 700 includes a switching element (Q _1, Q _2), the gate-off voltage turn turning off the gate-on voltage (V _on) and switching elements (Q _1, Q ₂₎ to turn on the (V _off) and generates a common voltage (V _com) and so on is applied to the common electrode 270.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display.

The gate driver 400 may also be referred to as a scan driver. The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to provide a gate-on voltage V _on from the driving voltage generator 700. And a gate signal composed of a combination of the gate off voltage V _off are applied to the gate lines G ₁ -G _n .

The data driver 500 may also be referred to as a source driver. The data driver 500 may be connected to the data lines D ₁ -D _m of the display panel 300 to select a gray voltage from the gray voltage generator 800 to select data as a data signal. Applies to lines D ₁ -D _m .

The signal controller 600 generates a control signal for controlling operations of the gate driver 400, the data driver 500, the driving voltage generator 700, and the gray voltage generator 800, thereby generating the respective devices 400 and 500. , 700).

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 controls an gray level signal R, G, B and its display from an external graphic controller (not shown), for example, a vertical synchronization signal. A vertical synchronizing signal (V _sync ), a horizontal synchronizing signal (H _sync ), a main clock (CLK), and a data enable signal (DE) are provided. The signal controller 600 generates a gate control signal and a data control signal based on the control input signal, appropriately processes the gray level signals R, G, and B according to the operating conditions of the liquid crystal panel 300, and then controls the gate control signal. Are sent to the gate driver 400 and the driving voltage generator 700, and the data control signal and the processed gray level signals R ′, G ′, and B ′ are sent to the data driver 500.

The gate control signal includes a vertical synchronization start signal (STV) indicating the start of output of the gate-on pulse (gate-on voltage section of the gate signal), and a gate clock signal controlling the output timing of the gate-on pulse. signal, CPV) and a gate on enable signal (OE) defining a width of the gate on pulse. The gate on enable signal OE and the gate clock signal CPV are also supplied to the driving voltage generator 700. The data control signal is a horizontal synchronization start signal (STH) indicating the start of input of the gray scale signal and a load signal (load signal, LOAD or TP) for applying the corresponding data signal to the data lines D ₁ -D _m . ), The polarity of the data signal voltage with respect to the common voltage (V _com ) (hereinafter referred to as "data voltage" by reducing the "data signal voltage", and "polarity of the data voltage" by reducing the "polarization of the data voltage" for the common voltage " And a reversing control signal (RVS) and a data clock signal (HCLK). The inversion control signal RVS is also supplied to the driving voltage generator 700.

The gate driver 400 sequentially applies gate-on pulses to the gate lines G ₁ -G _n in response to the gate control signals from the signal controller 600, and thus provides two rows connected to the gate lines G ₁ -G _n . The switching elements Q ₁ and Q ₂ are turned on. At the same time, the data driver 500 controls the gray level signals R ', G', and B 'of the pixels including the turned-on switching elements Q ₁ and Q ₂ according to a data control signal from the signal controller 600. The analog gray voltage from the gray voltage generator 800 corresponding to the data signal is supplied as a data signal to the data lines D ₁ -D _m . The data signal supplied to the data lines D ₁ -D _m is applied to the liquid crystal capacitors C _LC1 and C _LC2 of each subpixel of the corresponding pixel through the turned-on switching elements Q ₁ and Q ₂ . In this manner, gate-on pulses are sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data signals to all the pixels. When one frame is finished and the inversion control signal RVS is supplied to the driving voltage generator 700 and the data driver 500, the polarities of all data voltages of the next frame are changed. At this time, the polarity of the data voltage flowing through one data line D ₁ -D _m is changed even within one frame, and the polarities of the data voltages applied to one pixel row are also different.

On the other hand, the difference between the data voltage and the common voltage (V _com) to which pixel (P _up), and as d _up, above and below: the sub-pixels of the pixel (P _up) ( , Voltages (hereinafter referred to as "pixel voltages") of liquid crystal capacitors C _LC1 and C _LC2 of ), V ( Let's say Also, the subpixel below the pixel P _up ( ) Is the subpixel above the pixel (P _down ) ) Is coupled to the coupling capacitor C _pp , and the difference between the data voltage and the common voltage V _com for the pixel P _down is d _down . _Assume that a data voltage is first applied to the pixel P _up and then a data voltage is applied to the pixel P _down . Then the following relation holds.

In Equations 1 and 2, C _LC2 and C _ST2 represent lower subpixels ( Is the capacitance of the liquid crystal capacitor and the holding capacitor, C _pp is the capacitance of the coupled capacitor, and d ' _down is the subpixel ( The difference between the data voltage and the common voltage (V _com ) applied to). For convenience, the wiring resistance and signal delay of the data lines D ₁ -D _m are ignored.

When d _up and d _down in Equation 2 have the same polarity, d _down and d ' _down are opposite polarities, Becomes Particularly, in the case where the pixel P _down displays the same gray level as the pixel P _up and is a still image, d _up = d _down = -d ' _down so that Equation 2 can be summarized as follows.

,

＞ 1

to be.

Conversely, if d _up and d _down are opposite polarities,

Becomes If the pixel P _down displays the same gray level as the pixel P _up and is a still image

,

<1

Becomes

According to Equations 3 and 5, the lower subpixel of a pixel P _up ( ) Is a subpixel above other pixels (P _down ) ) And capacitively coupled two subpixels ( , If the polarities of the data voltages applied to the same are the same, the lower subpixel of the pixel P _up ( ), The top of the sub-pixels of the pixel (P _up) ( ) Than the high voltage is charged, on the other hand the bottom of the sub-pixels of the pixel (P _up) when the opposite polarity ( At the top subpixel ( A voltage lower than) is charged.

Therefore, it is desirable to make the polarities of the data voltages applied to the two capacitively coupled subpixels the same so as to charge the pixel with a relatively high voltage at the same voltage.

Next, a method of applying a data voltage to the liquid crystal display shown in FIG. 3 will be described in detail with reference to FIG. 4.

4 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 3.

As shown in FIG. 4, in the present embodiment, polarities of data voltages applied to neighboring data lines D ₁ -D _m are opposite to each other, and data voltages applied to one data line D ₁ -D _m are different from each other. The polarity is reversed every two pixel rows. In this case, data voltages having the same polarity are applied to pixels of two adjacent pixel rows having the same relative position with respect to one data line D ₁ -D _m .

In this case, since the voltage having the same polarity is applied to the two capacitively coupled subpixels, the voltage charged in the pixel increases.

5 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in Fig. 5, the liquid crystal display device of this embodiment is not provided with the sustain electrode line SL. Therefore, in a planar arrangement, two subpixels arranged vertically are allocated to one region partitioned by two adjacent gate lines G ₁ -G _n and two adjacent data lines D ₁ -D _m . The two subpixels are connected to different gate lines G ₁ -G _n . In other words, one data line is disposed between two adjacent subpixel columns, but there is one gate line or no gate line between two adjacent subpixel rows.

The positional relationship of each subpixel with respect to the gate lines G ₁ -G _n is the same as that of the example of FIG. 3. That is, the subpixels of each pixel _Pi and _j ( , ) It is located on the opposite side with respect to the corresponding gate line (G _i) and are all of the sub-pixels of each pixel row connected to the same hatching gate lines (G ₁ -G _n), on both sides of the gate lines (G ₁ -G _n) All the subpixels of adjacent subpixel rows are connected to the gate lines G ₁ -G _n .

In addition, the data lines (D ₁ -D _m) of the positional relationship between each sub-pixel, the sub-pixels ({P} of the pixels <sub>(P i, j) `_</sub> {i, j} ^ {1} on, {P } `_ {i, j} ^ {2}) are located on the same side with respect to the data line D _j , and the subpixels of pixels connected to one gate line G ₁ -G _n are all corresponding to the data line ( viscosity that located on the same side with respect to the D ₁ -D _m) is the same.

Data lines (D ₁ -D _m) is the positional relationship of the difference from Fig. 3 for each sub-pixel for all the sub-pixels of a pixel connected to one data line (D ₁ -D _m) is the data lines (D ₁ -D _m ) on one side. 5 has all the sub-pixels connected to data lines (D ₁ -D _m) are shown a structure, which is disposed on the left side of the data lines (D ₁ -D _m).

Another difference between FIG. 5 and the structure of FIG. 5 is a capacitive coupling relationship between subpixels, in which subpixels of each pixel column are capacitively coupled to subpixels of other columns. For example, in FIG. 5, the upper subpixel of the pixels _Pi and _j ( ) Is a lower subpixel (P _i-1 , _j-1 ) of the row pixels P _i-1 and _j-1 immediately above the left pixel column. ) And the coupling capacitor (C _pp ) ) Is an upper subpixel (P _{i + 1} , _{j + 1} ) of the row pixels immediately below the right pixel column. ) And capacitively coupled. Such capacitive coupling between different rows of subpixels is referred to as "bi-coupling" in the future.

FIG. 6 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 5.

As shown in FIG. 6, in the present embodiment, polarities of data voltages applied to neighboring data lines D ₁ -D _m are opposite to each other, and data voltages applied to one data line D ₁ -D _m are different from each other. The polarity is reversed every pixel row.

In this case, since the voltage having the same polarity is applied to the two capacitively coupled subpixels, the voltage charged in the pixel increases.

Next, a detailed structure of the liquid crystal panel assembly 300 of the liquid crystal display device illustrated in FIG. 3 will be described with reference to FIGS. 7 to 8B.

FIG. 7 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 8A is a cross-sectional view of the liquid crystal panel assembly of FIG. 7 taken along the line 'a-'a', and FIG. 8b is the liquid crystal panel assembly of FIG. Is a cross-sectional view of the lower display panel taken along the line Ⅷb-Ⅷb '.

First, the lower panel will be described.

A plurality of gate lines 121 and a plurality of coupling members 133 are formed on a transparent insulating substrate 110 such as glass. Each gate line 121 mainly extends in the horizontal direction and a part of the gate line 121 protrudes up and down to form the gate electrode 124.

The gate line 121 and the coupling member 133 are covered with the gate insulating layer 140, and a plurality of linear semiconductors 151 formed of amorphous silicon and mainly extending in the vertical direction are formed on the gate insulating layer 140. . A portion 156 of each semiconductor 151 protrudes over the gate electrode 124, and portions 154a and 154b of each protrusion 156 overlap the gate electrode 124 to form a channel portion of the thin film transistor. On each of the semiconductors 151, ohmic contacts 161, 165a and 165b made of amorphous silicon doped with N-type impurities such as phosphorus are formed.

A data line 171 and a plurality of pairs of drain electrodes 175a and 175b are formed on each of the ohmic contacts 161, 165a and 165b.

The data line 171 extends mainly in the vertical direction and branches over each protrusion 156 to form a source electrode 173 of the thin film transistor. The pair of drain electrodes 175a and 175b are separated from each other and also separated from the data line 171, and are disposed substantially symmetrically with respect to the corresponding gate electrode 124 and the source electrode 173.

In this case, the ohmic contacts 161, 165a, and 165b are disposed only at a portion where the semiconductor 151, the data line 171, and the drain electrodes 175a and 175b overlap each other. The data line 171, the drain electrodes 175a and 175b, the ohmic contacts 161, 165a and 165b, and the semiconductor 151 have substantially the same planar shape except for the channel portions 154a and 154b. However, the semiconductor 151, the data line 171, and the drain electrodes 175a and 175b may not have the same planar shape. For example, the semiconductor 151 may include only the protrusion 156 including the channel portions 154a and 154b, and the linear portion extending along the data line 171 may be omitted. In addition, the semiconductor 151 may be present at a portion where the gate line 121 and the data line 171 cross each other for effective electrical insulation.

The data line 171 and the drain electrodes 175a and 175b are covered with the passivation layer 180, and the plurality of contact holes 181 and 182 and the data lines 171 exposing portions of the drain electrodes 175a and 175b, respectively. It has a plurality of contact holes 189 exposing one end of the. The passivation layer 180 and the gate insulating layer 140 may include a plurality of contact holes 188 exposing one end portion of the gate line 121 and a plurality of contact holes 183 exposing one end portion of the coupling member 133. Have

A plurality of pairs of pixel electrodes 190a and 190b are formed on the passivation layer 180, and each pair of pixel electrodes 190a and 190b has a pair of drain electrodes 175a and 175b through contact holes 181 and 182. ), Respectively. On the passivation layer 180, a plurality of gate contact assistant members 95 and a plurality of data contact assistant members 97, which are connected to the gate line 121 and the data line 171, respectively, through the contact holes 188 and 189, respectively. Is formed. The pixel electrodes 190a and 190b and the contact auxiliary members 95 and 97 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In each pair of pixel electrodes 190a and 190b, the lower pixel electrode 190b is connected to the coupling member 131 through a contact hole 183, and the upper pixel electrode 190a overlaps the coupling member 131. have. The coupling member 131 capacitively couples the upper and lower pixel electrodes 190b and 190a of the adjacent pixel column across the data line 171. A portion of the coupling member 131 overlapping the pixel electrode 190a extends in a substantially horizontal direction along the upper edge of the pixel electrode 190a and the contact hole 183 is disposed at a position near the crossing data line 171. It is.

On the other hand, the pixel electrode 190a has one linear horizontal cutout 191 extending generally in the horizontal direction. The number of horizontal cutouts 191 may be plural, and a linear cutout extending in the vertical direction may be provided in the lower pixel electrode 190b. In order to eliminate the gray level inversion phenomenon, the ratio of the upper pixel electrode 190a to the entire pixel electrode area is preferably 10% to 50%, and particularly preferably 20 to 30%.

The contact assistants 95 and 97 are not essential to protect exposed gate line and data line portions and to increase physical and electrical contact.

An alignment layer 11 is formed on an entire surface of the lower panel 100 except for the vicinity of the contact auxiliary members 95 and 97.

Next, the upper panel will be described with reference to FIGS. 7 and 8A.

The black matrix 220 is formed on a transparent insulating substrate 210 such as glass, and the red, green, and blue color filters 230 are formed in each pixel region defined by the black matrix 220. An overcoat layer 250 is formed on the color filter 230, and a common electrode 270 made of a transparent conductive material such as ITO is formed on the overcoat layer 250.

The common electrode 270 includes a plurality of cutouts, and each group includes three linear cutouts 271, 272, and 273. In each group, one cutout 271 generally extends in the longitudinal direction and divides the lower pixel electrode 190b into two small regions from side to side. In each group, the two cutouts 272 and 273 extend generally in the horizontal direction and are disposed substantially symmetrically with respect to the horizontal cutout 191 of the pixel electrode 190a. The incisions 272, 191, and 273 in the horizontal direction are positioned at the top and bottom portions of the upper pixel electrode 190a, and each of the small regions partitioned by the group of incisions 191, 271, 272, and 273 is formed. It is substantially square and two long sides thereof are substantially parallel to the gate line 121 or the data line 171.

The positions of the cutouts 191, 271, 272, and 273 of the pixel electrodes 190a and 190b and the common electrode 270 may be interchanged. That is, the horizontal cutouts 191, 272, and 273 may be located in the upper pixel 190a, and the vertical cutout 271 may be located in the lower pixel 190b.

An alignment layer 21 is formed on the entire upper panel 200.

Polarizers 12 and 22 are attached to the outer sides of the two substrates 110 and 210, respectively. At this time, the polarization axes of these polarizing plates 12 and 22 are arranged parallel to the gate line 121 or the data line 171 and orthogonal to each other.

The liquid crystal material is injected between the lower substrate 100 and the upper panel 200 having the above structure to form the liquid crystal layer 3. The liquid crystal molecules of the liquid crystal layer 3 may be homogeneous alignment or homeotropic alignment or vertical alignment, but it is preferable in terms of the viewing angle.

At least one of the cutouts 191, 271, 272, and 273 illustrated in FIGS. 7 to 8B may be replaced with a protrusion formed on the passivation layer 180.

5 to 8B have the following advantages over the liquid crystal display of FIGS. 3 and 4.

First, in the case of FIG. 3, data lines D ₁ -D _m must be disposed on the left and right sides of each column in order to fill all the subpixels in all rows and all columns. However, in the leftmost column and the rightmost column, data lines D ₁ -D _m must be disposed on the left and right sides, so that the number of data lines D ₁ -D _m is one more than the number of subpixel columns. In contrast, in FIG. 5, the data lines D ₁ -D _m only need to exist on one side of each pixel column, so that the number of data lines D ₁ -D _m and the number of subpixel columns are the same, thereby simplifying the structure. .

Next, in FIG. 3, a problem may occur when a parasitic capacitance change occurs due to a misalignment between the data lines D ₁ -D _m and the pixel electrodes 190 of FIG. 2, but not in FIG. 5. . For example, suppose that the square in FIG. 4 is referred to as the pixel electrode 190 shown in FIG. 2, and these pixel electrodes 190 are moved to the right as a whole. Then, the pixel electrode 190 located on the left side of each data line D ₁ -D _m is close to the data line D ₁ -D _m , whereas the pixel electrode 190 located on the right side is the data line D _1. -D _m ) Then, the parasitic capacitance between each data line D ₁ -D _m and the pixel electrode 190 located on the left side is increased, and the parasitic capacitance between each data line D ₁ -D _m and the pixel electrode 190 located on the right side thereof is increased. Parasitic doses are small.

The influence of such a parasitic capacitance change will be described with reference to the pixel of the pixel column located to the left of the j th data line D _j in FIG. 4. The pixels in this pixel column are more affected by the j-th data line D _j located on the right side than the (j-1) -th data line D _j-1 located on the left side. When the (i + 1) -th pixel row is charged, the j-th data line D _j carries a data voltage of (-) polarity with respect to the common voltage V _com , and (i-1) -th and i-th The pixels are still charged with a negative voltage. Therefore, the parasitic capacitance between the pixel electrode 190 and the data line D _j increases the magnitude of the voltage applied to the pixels in this pixel row. Next, when the (i + 3) th pixel row is charged, the jth data line D _j carries the data voltage of positive polarity with respect to the common voltage V _com , and the (i + 1) th and i The pixels in the first pixel row are charged with a negative voltage. Therefore, the parasitic capacitance between the pixel electrode 190 and the data line D _j reduces the magnitude of the voltage applied to the pixels in this pixel row.

As a result, in the cross-array structure as shown in FIG. 3, the parasitic capacitance variation between the pixel electrode and the data lines on both sides causes a problem of increasing the charging voltage for some pixels and decreasing the charging voltage for some pixels.

Another problem caused by misalignment may be that the overlapping area between the gate electrode 124 and the source and drain electrodes 173a, 173b, 175a, and 175b may vary depending on the position of the pixel. As a result, a difference in kickback voltage may occur for each pixel, thereby changing the brightness of the pixel.

In addition, since the thin film transistors are alternately formed on the left side and the right side, the effect of the pixel electrodes 190a and 190b when the shape of the pixel electrodes 190a and 190b, especially the cutout is not symmetrical, for example, the pixel electrodes 190a and 190b ) And the shape of the electric field generated by the common electrode 270 are difficult to accurately fit so as to be identical for each pixel.

However, this problem does not occur in the structure of FIG. 5 because all the pixels of one pixel column are connected to the same data line D ₁ -D _m .

9 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in Fig. 9, in the liquid crystal display of the present embodiment, the capacitive coupling between subpixels alternates column-coupling and di-coupling in rows along the column direction, and in the row direction, any one of the column coupling and the column coupling is shown. Same as the example of FIG. 5 except that only one is to appear.

FIG. 10 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 9.

As shown in FIG. 10, in the present embodiment, polarities of data voltages applied to neighboring data lines D ₁ -D _m are opposite to each other, and data voltages applied to one data line D ₁ -D _m are different from each other. The polarity is reversed every two pixel rows. In this case, voltages of the same polarity are applied to the two column rows that are column-coupled, and voltages of the opposite polarity are applied to the two pixel rows that are column-coupled.

In this case, since the voltage of the same polarity is applied to the two capacitively coupled sub-pixels, the voltage charged in the pixel increases, which is the same as that of FIG.

11 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

As described above with reference to FIG. 2, since each pixel displays any one of red, green, and blue colors, a data signal applied to each pixel is related to the color. Accordingly, the pixels displaying red, green, and blue are called red pixels, green pixels, and blue pixels, respectively, and the data signals applied to the pixels of the corresponding colors are called red, green, and blue data signals, respectively.

In the present exemplary embodiment, the pixels of one pixel column all display the same color, and the pixels displaying red, green, and blue appear alternately when viewed in the row direction. In this embodiment, the pixels of one pixel column are all connected to the same data line. Accordingly, since one data line carries only one color data signal, data lines carrying data signals of the corresponding color are referred to as red, green, and blue data lines, respectively. In FIG. 11, r _k is a red data line and g _k. Denotes a green data line, b _k-1 , and b _k denotes a blue data line.

When the liquid crystal display of the present embodiment is viewed in a planar arrangement, the subpixels allocated to one region partitioned by two adjacent gate lines G ₁ -G _n and two adjacent data lines D ₁ -D _m are included. The number is zero, two or four. If two subpixels are allocated, the two subpixels are arranged in a column direction, and in the case of four, they are arranged in a rectangle. In other words, there is one gate line or no gate line between two adjacent pixel rows as in FIG. 5, but the number of data lines disposed between two adjacent pixel columns is zero, one, or two.

In FIG. 11, two pixel columns of a red pixel column and a green pixel column are disposed between adjacent red data lines r _k and green data lines g _k , and adjacent green data lines g _k and blue data lines b _k. ), Only one blue pixel column is disposed, and there is no pixel between the adjacent blue data line b _k-1 and the red data line r _k .

In addition, the positional relationship of each subpixel with respect to the gate lines G ₁ -G _n or the positional relationship of each subpixel with respect to the data lines r _k , g _k , and b _k is the same as in the case of FIG. 5.

Another difference between the structure of FIG. 11 and FIG. 5 is the capacitive coupling relationship between subpixels. The subpixels of the red and green pixel columns are double-coupled, and the subpixels of the two pixel columns cross-couple each other. For example, two sub-pixels of each pixel PR _{i, k in the} red pixel column ( , ) Is the subpixel of the subpixel row above and below the adjacent green pixel column. , ) And combined capacity. However, the subpixels of the blue pixel column have the same column coupling.

FIG. 12 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display illustrated in FIG. 11.

As shown in Fig. 12, in this embodiment, the polarities of the data voltages applied to neighboring data lines are opposite to each other, and the polarities of the data voltages applied to one data line are inverted every pixel row.

In this case, since the voltage of the same polarity is applied to the cross-coupled red and green subpixels, the voltage charged in the pixel increases, and the same advantages as in FIG. 3 are obtained.

13 is an equivalent circuit diagram of a liquid crystal panel assembly in a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in Fig. 13, in the liquid crystal display according to the present embodiment, the capacitive coupling between the red pixel columns and the subpixels of the green pixel columns alternates column-coupling and cross-coupling in rows along the column direction, and the columns in the row direction. Same as the example of FIG. 11 except that only one of the coupling and the cross coupling is to appear.

FIG. 14 is a diagram illustrating polarities of data voltages applied to each subpixel of the liquid crystal display shown in FIG. 13.

As shown in Fig. 14, in this embodiment, the polarities of the data voltages applied to neighboring data lines are opposite to each other, and the polarities of the data voltages applied to one data line are inverted every two pixel rows. At this time, among the red pixels and the green pixels, voltages of the same polarity are applied to two pixels that are co-coupled with each other, and polarities are changed such that voltages of opposite polarities are applied to the two pixels that are cross-coupled.

In this case, since the voltage of the same polarity is applied to the capacitively coupled red subpixel and the green subpixel, the voltage charged to the green and red pixels increases, and the same advantages as those of FIG. have.

Next, a detailed structure of the lower panel of the liquid crystal panel assembly 300 of the liquid crystal display shown in FIG. 13 will be described with reference to FIGS. 15 to 16C.

FIG. 15 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIGS. 16A, 16B, and 16C illustrate XVIa-XVIa 'line, XVIb-XVIb' line, and XVIc- line of the lower panel of the liquid crystal panel assembly of FIG. A cross-sectional view taken along the line XVIc '.

Since the upper panel may have the shapes shown in FIGS. 7 and 8A, only the lower panel will be described in detail.

Since the lower panel according to the present exemplary embodiment has almost the same basic structure as that shown in FIGS. 7 to 8A and the arrangement of the pixel and the data line has been described with reference to FIG. 13, only the characteristic part, that is, the part related to the coupling capacitor, is detailed. Explain.

The layered structure includes the substrate 110, the gate line 121, the gate insulating layer 140, the semiconductor 151, the ohmic contacts 161, 165a, and 165b, the data line 171, and the drain electrode 175a from below. 175b, the passivation layer 180, the pixel electrodes 190a and 190b, and the contact auxiliary pads 95 and 97 are sequentially formed.

The coupling members 133-137 used to capacitively couple the pixel electrodes 190a and 190b are made of the same layer as the gate line 121 or the data line 171.

The coupling members 135, 136, and 137 used for the same thermal coupling may be the same layer as the gate line 121 or the same layer as the data line 171. However, the two coupling members 133 and 134, which are used for cross coupling and cross each other, should be different layers.

15 to 16C, the coupling members 134 and 136 mainly located in the leftmost pixel column, that is, the red pixel column, are formed of the same layer as the data line 171, and the coupling member mainly located in the intermediate pixel column, that is, the green pixel column. Reference numerals 133 and 135 and the coupling member 137 positioned in the rightmost pixel column, that is, the blue pixel column, are formed of the same layer as the gate line 121.

The contact holes 183-187 exposing the coupling members 133-137, respectively, are formed only in the passivation layer 180 or in both the gate insulating layer 140 and the passivation layer 180, depending on the layered positions of the coupling members 133-137. do. That is, since only the passivation layer 180 is disposed on the coupling members 134 and 136 made of the same layer as the data line 171, only the passivation layer 180 is provided with contact holes 184 and 186, and the same layer as the gate line 121. Since the gate insulating layer 140 and the passivation layer 180 are formed on the coupling members 133, 135, and 137, contact holes 184 and 186 are formed in both layers 140 and 180.

Below the coupling members 134 and 136 having the same layer as the data line 171, a semiconductor island 158 and an ohmic contact island 168 having substantially the same planar shape as the coupling members 134 and 136 are provided. .

Meanwhile, in the liquid crystal display of FIGS. 11 to 16C, since voltages of opposite polarities are applied to the blue subpixels that are co-coupled, voltages charged to the pixels decrease when the opposite polarities are applied. However, since the human eye is usually insensitive to the change in the luminance of blue light, the decrease in the luminance of the blue pixel is not so much of a problem.

Rather, the reduction of the luminance of the blue pixel has an advantageous effect as compared to other embodiments in the following points will be described in detail.

In general, in a vertically aligned liquid crystal display device in normally black mode, that is, a vertically aligned liquid crystal display device that appears dark when the voltage charged to the pixel is 0, the intensity I of the light passing through the liquid crystal layer is given as follows.

Where Δn ^. d is a retardation of the liquid crystal layer, and the refractive index anisotropy (Δn) of the liquid crystal material is multiplied by the thickness d of the liquid crystal layer 3, and λ is a wavelength of light.

In Equation 6, since the wavelength of the blue light is short, the change in the intensity of the light with respect to the change in the delay value is sharp compared to the light of other colors.

This means that the change in transmittance of blue light with respect to the applied voltage is relatively severe and faster than other lights. Therefore, when the same voltage is applied to the red, blue, and green pixels, the blue pixels are first and brightest. It also means that the brightness of blue light is the brightest for the same gradation.

Therefore, when the luminance of the blue pixel is lower than that of the pixel of other colors, the variation of each color is reduced by that and the image quality of the liquid crystal display is improved accordingly.

On the other hand, when the increase in the luminance of the red and green pixels and the decrease in the luminance of the blue pixels due to the capacitive coupling are not enough to almost eliminate the difference in brightness, the correction may be performed using another method.

In general, the transmittance and luminance of red light are the lowest, the transmittance and luminance of blue light are the highest, and green is the middle. In particular, the difference is more severe in the intermediate grayscale. Therefore, even when the gray level is the same, it is necessary to apply a relatively high voltage to the red pixel and a relatively low voltage to the blue pixel to match the luminance to the green pixel.

To this end, when the gray voltage generator 800 shown in FIG. 1 generates the gray voltage, the gray voltage of different magnitudes for the same gray is generated under the control of the signal controller 600 to generate the gray voltage to the data driver 500. Can supply

As another method, when the signal controller 600 processes and exports the input gray data R, G, and B, the gray scale data itself may be corrected and exported.

In the case of FIGS. 13 and 14, since the polarity is changed once every two pixel rows, it is preferable to correct the pixel once every two pixel rows.

The subpixels are double-coupled or cross-coupled and two sub-pixels having the same polarity are applied to the two sub-pixels. The image quality of the liquid crystal display is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (18)

A plurality of first signal lines and a plurality of second signal lines, and A plurality of pixels connected to the first signal line and the second signal line Including; Each pixel includes a plurality of subpixels each including a switching element connected to one of the first signal lines and one of the second signal lines, The subpixels are arranged in the form of a matrix, Each subpixel is capacitively coupled with another subpixel, At least some of the subpixels are in double bond with the other subpixels Liquid crystal display. In claim 1, And at least another part of the subpixels is cross-coupled with another subpixel. In claim 2, And the first and second signal lines are not disposed between the two subpixels. In claim 3, The subpixels include red, green and blue subpixels, The subpixels of the second heat coupling are red and green subpixels. In claim 4, And at least some of the blue subpixels are thermally coupled. In claim 5, A liquid crystal display device having the same polarity as the data voltage applied to a pair of subpixels coupled to two columns. In claim 6, 12. A liquid crystal display device having a reverse polarity in which data voltages applied to a pair of co-coupled blue subpixels have opposite polarities. In claim 2, And a second signal line disposed between the two subpixels. In claim 8, The subpixels of each pixel are capacitively coupled to subpixels of different columns. In claim 1, The subpixels include red, green, and blue subpixels, And a data voltage applied to the blue subpixel for the same gray scale is smaller than a data voltage applied to the red and green pixels. In claim 1, And at least another portion of the subpixels is covalently coupled to another subpixel. The method of claim 1 or 11, A liquid crystal display device in which data voltages of the same polarity are applied to a pair of subpixels that are capacitively coupled. Board, A plurality of gate lines formed on the substrate, A plurality of data lines insulated from and intersecting the gate lines; A plurality of pairs of thin film transistors connected to the gate line and the data line, A plurality of pixel electrodes connected to the thin film transistors and arranged in a matrix; A plurality of first coupling members connected to one of the pixel electrodes and overlapping the other of the pixel electrodes with an insulator to form a first coupling capacitor Including; The coupling capacitor is formed between the pixel electrodes of different columns. Liquid crystal display. In claim 13, And the first coupling member is formed of the same layer as the gate line. The method of claim 14, And the first coupling member crosses the data line. The method of claim 14, And the first coupling member does not cross the data line. The method of claim 16, And a plurality of second coupling members connected to one of the pixel electrodes and overlapping the other of the pixel electrodes with an insulator to form a second coupling capacitor. The method of claim 17, The second coupling member is formed of the same layer as the data line, and the first coupling member and the second coupling member cross each other.