KR20040022592A - Method for manufacturing a semiconductor flash memory cell - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor flash memory cell is provided to improve capacity and yield by basically preventing a residual ONO layer from being formed on a sidewall such that the ONO layer can function as a fatal defect of a subsequent process in removing the ONO layer and polysilicon for forming a logic region. CONSTITUTION: A tunneling oxide layer(2) is deposited on a silicon substrate(1). Polysilicon(3) for a floating gate is formed in a flash cell region, the polysilicon in the logic region is eliminated. After a buffer oxide layer is deposited on the polysilicon, an ion implantation process is performed. The buffer oxide layer is eliminated. After a tunneling ONO layer(4) is deposited in the flash cell region, a patterning process is performed to eliminate the ONO layer in the logic region. After a tunneling oxide layer(6) is deposited in the logic region, polysilicon(7) for a control gate and a logic gate is deposited. The polysilicon for the control gate and the logic gate is patterned and etched.

Description

METHOD FOR MANUFACTURING A SEMICONDUCTOR FLASH MEMORY CELL

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor flash memory cell fabrication technology, and more particularly, to a method of fabricating a semiconductor flash memory cell suitable for removing ONO residues occurring at the boundary region of a flash cell region and a logic cell region.

1A to 1C are diagrams for describing a general semiconductor flash memory cell fabrication process, in which a flash cell region and a logic cell region are formed in the same chip.

First, in FIG. 1A, the tunneling oxide films 2 and 6 are deposited on the silicon substrate 1, the floating gate 3 of the flash cell region is formed, and the tunneling ONO film 4 of the flash region is deposited. .

Next, in FIG. 1B, a patterning process is performed to remove the ONO film 4 and the polysilicon 3 in the logic cell region before depositing the polysilicon for forming the control gate.

In FIG. 1C, after the tunneling oxide film 6 is formed in the logic region, the polysilicon 7 for the control gate / logic gate is deposited, and a patterning and etching process for forming the control gate is performed. Subsequent processes proceed in the same way as general logic processes.

At this time, in the process of removing the ONO film 4 and the polysilicon 3 in the logic cell region of FIG. 1B, the ONO film 4 is deposited on the side of the polysilicon 3 so that the ONO film 4 and the polysilicon ( In the removal of 3), sufficient side etching cannot be realized and the ONO film 4 remains.

That is, in the conventional semiconductor flash memory cell manufacturing technology, a poly residue or an oxide / nitride residue may be generated in the boundary region of the flash cell region and the logic cell region, resulting in a defect in a subsequent process, thereby causing the entire process. There was a problem that could reduce the yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and when forming a floating gate of a semiconductor flash cell, a polysilicon of a logic region is removed, a buffer oxide is deposited, a ONO layer of a logic region is removed, and then a logic region is removed. An object of the present invention is to provide a method for fabricating a semiconductor flash memory cell in which polysilicon is deposited after the tunneling oxide film is deposited, thereby minimizing damage of logic regions during subsequent processing.

In order to achieve the above object, the present invention provides a semiconductor flash memory cell manufacturing method in which a flash cell region and a logic cell region are formed in the same chip, wherein a tunneling oxide film is deposited on a silicon substrate, and a floating gate poly of the flash cell region is formed. Forming silicon, but removing polysilicon in the logic region; A second step of performing an ion implantation process after depositing a buffer oxide film on polysilicon; Removing a buffer oxide film, depositing a tunneling ONO film of a flash cell, and performing a patterning process for removing ONO in a logic region; Depositing a tunneling oxide film of a logic region on the layer formed in the third step, and then depositing polysilicon for the control gate / logic gate; And a fifth step of patterning and etching polysilicon for control gate / logic gate.

1A through 1C are cross-sectional views of a conventional semiconductor flash memory cell manufacturing process;

2A-2C are cross-sectional views of a process of fabricating a semiconductor flash memory cell in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: silicon substrate 2, 6: tunneling oxide film

3, 7: polysilicon 4: ONO film

5: photoresist

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Prior to the description, a key technical aspect of the present invention is to remove the polysilicon in the logic region when forming the floating gate of the semiconductor flash cell, deposit a buffer oxide film, and deposit ONO before the deposition of the polysilicon to be used for the control gate and the logic gate. By patterning and etching the film and then depositing the tunneling oxide and polysilicon for the logic gate, it is possible to minimize the damage of the logic region during the subsequent ion implantation process and the wet cleaning process. Can be implemented.

2A to 2C are cross-sectional views illustrating a process of fabricating a semiconductor flash memory cell according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, the tunneling oxide film 2 is deposited on the silicon substrate 1, and the floating gate 3 in the flash cell region is formed.

When the floating gate 3 of the flash cell region is formed, the polysilicon of the logic region is removed. Thereafter, in order to minimize damage to subsequent processes, a buffer oxide film (not shown) is deposited, followed by a basic ion implantation process of the flash cell. At this time, by controlling the thickness of the buffer oxide film it may be possible to minimize the damage caused by the ion implantation process to be carried out before the deposition of polysilicon in the future.

Then, in FIG. 2B, the buffer oxide film is removed before the ONO film 4 is deposited. For example, an HF solution or the like may be used to remove the buffer oxide film, which will be easily understood by those skilled in the art.

Thereafter, the tunneling ONO film 4 of the flash cell is deposited, and a patterning process for removing the ONO of the logic region is performed. At this time, since the ONO film 4 is in the form of a flat plate, residual ONO existing as a problem in the existing process is not formed, thereby eliminating a defect problem that may be caused in a subsequent process.

Meanwhile, in FIG. 2C, after the tunneling oxide film 6 in the logic region is deposited on the layer formed in FIG. 2B, polysilicon 7 to be used as the control gate and the logic gate is deposited.

The polysilicon 7 for control gate and logic gate is patterned and etched.

Subsequent processes proceed in the same way as general logic processes.

As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.

Therefore, the present invention improves device performance by ultimately preventing the formation of sidewall residual ONO, which can act as a fatal defect in subsequent processes upon removal of the ONO film and polysilicon for the formation of logic regions, resulting in stable device operation. There is an effect of improving the semiconductor yield.

Claims (2)

A semiconductor flash memory cell manufacturing method in which a flash cell region and a logic cell region are formed in the same chip. Depositing a tunneling oxide film on the silicon substrate and forming polysilicon for floating gate in the flash cell region, wherein the polysilicon in the logic region is removed; A second step of performing an ion implantation process after depositing a buffer oxide on the polysilicon; Removing the buffer oxide film, depositing a tunneling ONO film of a flash cell, and performing a patterning process for removing ONO in a logic region; Depositing a tunneling oxide film of a logic region on the layer formed in the third step, and then depositing polysilicon for the control gate / logic gate; And patterning and etching the polysilicon for the control gate / logic gate. The method of claim 1, The second step, And controlling the thickness of the buffer oxide layer to minimize damage due to an ion implantation process to be performed until subsequent deposition of polysilicon.