KR20040021791A - A matching device of dual mode ds3 circuit network for atm exchange - Google Patents

Abstract

PURPOSE: A DS3 dual mode subscriber line interface unit in an ATM exchange is provided to selectively operate either a structure mode or an unstructured mode according to an associated selection signal. CONSTITUTION: A DS3 dual mode subscriber line interface unit in an ATM exchange consists of the first and second LIUs(Line Interface Units)(100,105), the first and second matching parts(110,115), a cell processing part(160), a control part(140), a memory part(150), a clock part(190), and a power supply part(200). The first and second LIUs(100,105) input and output line signals of 44.736Mbps DS3 line level signals in a matching state according to associated control signals. The first and second matching parts(110,115), respectively connected to the first and second LIUs(100,105), input and output multiplexing, demultiplexing, bypass or framer processed line signals through associated paths according to associated control signals. The cell processing part(160) is composed of the first cell processing parts(170,175) and the second cell processing parts(180,185). The control part(140), controlling and monitoring each function part, executes processor communication with an upper level part. The memory part(150) writes, stores, and outputs the operation information of the control part(140) and the first and second cell processing parts(170,175,180,185). The clock part(190) processes a clock signal supplied from an upper level part and converts it a plurality of relevant clock signals. The power supply part(200) processes a power signal supplied from an upper level part and converts it into a plurality of DC power sources.

Description

A MATCHING DEVICE OF DUAL MODE DS3 CIRCUIT NETWORK FOR ATM EXCHANGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a matching device for interworking DS class 3 signals of an ASYNCHRONOUS TRANSFER MODE (ATM) exchange, and in particular, a signal applied to the DS class 3 from a circuit network in unstructured and structured modes. A dual mode circuit network matching device for selective processing.

The asynchronous transfer mode (ATM) exchange transmits communication data by dividing the communication data into 53 bytes (CELL) or a packet (PACKET), and allocates 5 bytes (BYTE) of the 53 bytes of the cell or packet to the head information. The head information includes destination route information.

The path between the subscriber and the subscriber does not have a physical path, and if necessary, it improves the bandwidth efficiency of the transmission path of the path virtually set in the head information, and also processes data in small cells or packets of 53 bytes, thereby enabling high-speed exchange. .

The asynchronous transfer mode (ATM) exchange is for connecting voice or data line signals of a circuit switching network or a general telephone network to an ATM switching network. Asynchronous transfer mode (ATM) exchange provides a constant rate of continuous data (CBR: CONSTANT BIT RATE) having a constant speed. A matching device of interworking function that converts to 53 bytes of cells or packets or vice versa is essential.

The circuit network matching device of the ATM switch includes a structure mode for multiplexing and demultiplexing an input signal and a structure for bypassing the input signal through one ATM virtual path (UNSTRUCTURED). ) Mode.

The voice signal of the exchange is called a line signal, and the circuit signal is exchanged by a circuit switching network or a circuit network. The line level signal or circuit signal includes an externally supplied clock, data to be transmitted, and a frame (FRAME) unit. In order to separate the voice signal by mixing the frame sync bits for synchronizing to transmit them in one path, and to be strong in noise or attenuation, the data signal should be detected and processed. .

Although a matching device for interworking the structure mode signal and a matching device for interworking the unstructured mode signal were separated from each other, development of a matching device that can be used in dual mode due to the demand for miniaturization and performance improvement of the exchanger. This is required.

Hereinafter, a DS3 class high-speed signal interworking matching device of an ATM switch according to the prior art will be described with reference to the accompanying drawings.

It is attached to explain the prior art, Figure 1 is a structure structure matching device function configuration according to the prior art, Figure 2 is a structure structure matching device structure according to the prior art.

Referring to FIG. 1, the structure mode matching device according to the prior art matches a line level signal generated by a plurality of subscribers from a lower part and converted to DS3 class for high speed transmission by a corresponding control signal. A DS3 matching unit 10 which inputs in a (MATCHING) state and extracts a clock signal, a data signal, a frame sync bit from the line level line signal by the framer function, or vice versa,

A demultiplexing process connected to the DS3 matching unit 10 and separating a DS3 (DS3) class line level signal into 28 T1 (T1) or 21 binary (E1) signals according to the control signal; A multiplexer 20 for multiplexing 28 tee-level (T1) signals or 21 binary (E1) signals to the DS3-class signal, and

Framer unit 30 connected to the multiplexer 20 and extracting a clock signal, a data signal, a frame sync bit from a tee one (T1) and a binary (E1) signal according to the control signal, or vice versa. )Wow,

A cell processing unit connected to the framer unit 30 and converting a line signal applied to the AAL1 (ATM ADAPTION LAYER 1) cell (CELL) signal in the asynchronous transmission mode (ATM) according to the control signal, or vice versa. 40,

An ATM matching unit 50 connected to the cell processing unit 40 and transmitting the applied ATM cell signal to the upper ATM network in a matching state and vice versa;

A clock unit 60 which receives a network synchronizer clock from an upper ATM network and supplies it to each functional unit through a corresponding control unit;

The controller 70 is configured to monitor and control the respective functional units and to apply a clock signal applied from the clock unit 60 to the respective functional units.

In addition, referring to the attached FIG. 2, the unstructured mode matching device according to the prior art is the same as the structured mode matching device, and the DS3 class line level line signal applied from the lower part is a control signal. The matching unit 15 extracts a clock signal, a data signal, and a frame sync bit from the line level line signal by a framer function and vice versa by inputting it into a matching state. )Wow,

A cell processor 45 which is connected to the DS matching unit 15 and converts the line signal applied to the AAL1 cell signal of the asynchronous transmission mode (ATM) or vice versa by a corresponding control signal; ,

An ATM matching unit 55 connected to the cell processing unit 45 and transmitting an ATM cell signal applied to the uppermost ATM network in a matching state and vice versa;

A clock unit 65 which receives a network synchronizer clock from an upper ATM network and supplies it to each functional unit through a corresponding control unit;

And a control unit 75 for monitoring and controlling the respective function units and supplying a corresponding clock to each function unit.

In the above, the upper part processes the functions of the upper level functionally, and the lower part processes the functions of the lower level.

Hereinafter, a structure mode matching device and an unstructured mode matching device according to the related art having the above-described configuration will be described in detail with reference to FIGS. 1 and 2.

The DS3-class line-level line signal transmitted and received from the lower part is a high-speed signal of 44.736 Mbps, and the DS3-class line subscriber signal is a 28-T1 line subscriber signal or a 21-member (E1) line subscriber signal. Is multiplexed, and it is determined whether one ATM virtual path is set by BYPASS or demultiplexed by the matching device to set a plurality of ATM virtual paths to be transmitted to the corresponding path, respectively. Judging from

The demultiplexing is applied to and processed by the structure mode matching device of FIG. 1, and the BYPASS is applied and processed to the unstructured mode matching device of FIG. 2.

As an example, a case where the DS3 signal applied from the lower portion is demultiplexed will be described with reference to FIG.

The 44.736 Mbps DS3-class line level line signal is received by the DS3 matching unit 10 receiving the corresponding control signal from the control unit 70 in a matching state, and the corresponding clock signal and data signal. And the frame sync bit are separately extracted and are output in a synchronized state by the frame sync bit signal.

DS3 signals output from the DS3 matching unit 10 in synchronization with the framer function are applied to the multiplexer 20, and 28 T-ones T1 are generated by corresponding control signals applied from the control unit 70. The demultiplexed line signal is outputted to the framer unit 30 by being separated into a) signal or 21 binary (E1) signal.

The framer unit 30 receives 28 T1 (T1) or 21 binary (E1) line signals, and according to the control signal applied from the control unit 70, the T1 (T1) or binary ( It extracts the clock signal, data signal and frame sync bit of E1) class and applies 28 T1 signal or 21 binary (E1) signal in the synchronized state to the cell processor 40.

The cell processing unit 40 processes eight T-one (T1) level signals or eight binary (E1) level signals, and according to the control signal of the control unit 70, the T-one (T1) level or binary E1. In order to process the signal applied from the framer unit 30 by converting the class signal into the AAL1 ATM cell signal and applying it to the ATM matching unit 50, for example, in the case of a T1 class signal, the maximum number is 28. In addition, four cell processing units 40 should be provided in parallel, and the signals output from the cell processing units 40 are outputted to the upper part of the ATM network in a state matched by the ATM matching unit 50.

The clock unit 60 receives a network synchronizer clock applied from an upper portion of an ATM network and performs a corresponding process, and the processed clock signal is applied to each functional unit through the control unit 70.

The control unit 70 outputs a clock signal applied from the clock unit 60 to each corresponding function unit, outputs a corresponding control signal for controlling each function unit, and monitors an operation state of each function unit.

In the structure mode matching device of FIG. 1, each functional unit operates using a clock applied from an upper part of an ATM network, that is, an internal clock, and ATM cell signals applied from an upper part of the ATM network are reversed in the above description. Is processed and applied to the lower part.

The non-structural mode matching device of FIG. 2 is a case of simply passing through, and each functional unit is the same as that of the structure mode matching device of FIG. 1. The line signal of the high-level line level is received in the matching state by the DS3 matching unit 15 according to the control signal applied from the control unit 75, and the clock signal, the data signal, and the frame sync bit are separated. The external clock signal is output to the cell processor 45 in a state synchronized with the frame sync bit signal.

The cell processing unit 45 converts the DS3 signal applied in the synchronized state into an AAL1 ATM cell signal under the control of the control unit 75 and outputs the same to the ATM matching unit 55. Transmit to the upper part of ATM network in the state matched by 55).

The clock unit 65 receives a network synchronizer clock from an upper portion and outputs the same to the controller 75, but in general, the controller 75 does not use the network synchronizer clock signal, that is, an internal clock signal. The external clock signal detected by the function is used as a signal for synchronization, and the respective functional units are monitored and the corresponding control is performed.

If necessary, the unstructured mode matching device can use the upper network synchronizer clock signal as a clock required for internal clock synchronization without using an external clock applied from the lower portion by the control, and is applied from the upper portion. In case of transmitting the BYPASS ATM cell signal to the lower part, the reverse operation is performed.

The structure-mode matching device and the unstructured-mode matching device according to the related art of the above-described structure are each configured on separate boards, and each of the boards must be provided with a large number of corresponding boards by processing the corresponding signal in the designated mode. There is a problem.

In addition, since the exchanger must be provided with a matching device for each mode, there are many problems such as bulky, high power consumption, complicated and difficult maintenance, and frequent failure of the system.

According to the present invention, in the DS3-class line subscriber matching device, a dual-mode DS3 line that can be selectively operated in an unstructured mode that passes through a structure mode for demultiplexing and multiplexing into multiple path signals according to the selection signal. The purpose is to provide a subscriber matching device.

In order to achieve the above object, the present invention is connected to the lower part for processing the signal of the circuit subscriber, the first and second line interface unit for inputting and outputting the DS class signal in a matched state by the control signal; ; First and second matching units respectively connected to the first and second line interface units and selectively inputting / outputting line signals multiplexed, demultiplexed, routed, and framed by the corresponding control signals through corresponding paths; The line signal connected to and applied to the first and second matching units is converted into an A1 MT cell signal by a corresponding control signal, and is output to an upper portion as a Utopia level 2 signal and applied as a utopia level 2 signal from an upper portion. A cell processing unit for converting an AMT cell signal to be a line signal and outputting the signal; A control unit for controlling and monitoring the respective functional units and the processor communication with the upper unit.

1 is a structure diagram of a structure mode matching device according to the prior art,

2 is a functional block diagram of an unstructured mode matching device according to the prior art;

3 is a functional diagram of a dual mode DS3 line subscriber matching device according to the present invention;

4 is a converted clock signal supply state diagram of a clock unit according to the present invention;

5 is a detailed functional configuration diagram of a control unit according to the present invention;

Fig. 6 is a control operation state diagram of the dual mode DS3 line subscriber matching device according to the present invention.

** Explanation of symbols on the main parts of the drawing **

10,15 DS3 matching unit 20 multiplexing unit

30: framer portion 40, 45: cell processing portion

50,55: ATM matching unit 60,65: clock unit

70, 75: control unit 100: first line interface unit

105: second line interface unit 110: first matching unit

115: second matching unit 140: control unit

150: memory 170,175: first cell processing unit

180,185: second cell processing unit 190: clock unit

200: power supply

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, asynchronous transmission mode switch DS class dual mode circuit network matching device according to the present invention will be described with reference to the accompanying drawings.

3 is a functional configuration diagram of a dual mode DS3 line subscriber matching device according to the present invention, FIG. 4 is a converted clock signal supply state diagram of a clock unit according to the present invention, and FIG. 6 is a detailed functional configuration diagram of the control unit according to the present invention, and FIG. 6 is a control operation state diagram of the dual mode DS3 line subscriber matching device according to the present invention.

3 to 5, the dual mode DS subscriber line matching device according to the present invention is connected to a lower portion for processing a signal of multiple circuit subscribers and is connected to a lower portion of 44.736 Mbps. First and second line interface units (LIU: LINE INTERFACE UNIT) (100, 105) for inputting / outputting line signals of DS class 3 line level signals to a matching state by corresponding control signals;

It is connected to the first and second line interface units 100 and 105, respectively, and selectively transmits the multiplexing, demultiplexing, bypass and framer processing line signals according to the corresponding control signals. First and second matching units 110 and 115 for inputting and outputting through a path PATH,

A line signal of a line level signal connected to and applied to the first and second matching units 110 and 115 is converted into an AAL1 ATM cell by a corresponding control signal and then UTOPIA. : UNITALS TEST AND OPERATIONS PHYSICAL INTERFACE FOR ATM) Level 2 signal is output to upper part and AUT1 (AAL1) ATM CELL signal is applied from upper part to UTOPIA level (LEVEL) 2 signal. By converting the line level signal into a line signal and outputting the line signal, a plurality of tee-one (T1) or binary (E1) -level signals each connected between the first matching unit 110 and the upper part are processed. First cell processing units 170 and 175; The cell processor 160, which is connected between the second matching unit 115 and the upper part, and includes a plurality of second cell processing units 180 and 185 for processing 16 T-one (T1) or binary (E1) signals, respectively. Wow,

A control unit 140 which controls and monitors each function unit and performs processor communication with an upper unit;

A memory 150 for recording, storing and outputting corresponding operation information of the control unit 140 and the first and second cell processing units 170, 175, 180, and 185;

The clock signal applied from the upper part is processed and converted into a plurality of clock signals. For example, a clock signal of 19.44 MHz is received from the upper part and 38.88 MHz, 44.736 MHz, 37.056 MHz, 49.125 MHz, and 77.768 MHz are applied. A clock unit 190 converting the clock signal and applying a corresponding clock signal to each corresponding functional unit;

The power signal applied from the upper part is processed and converted into a plurality of DC power sources. For example, a -48V DC power is applied from the upper part and converted to DC power of + 2.5V and + 3.3V. The power supply unit 200 is applied to the corresponding operating power.

Hereinafter, according to the present invention having the above configuration, a dual mode DS3 line subscriber matching device will be described in detail with reference to the accompanying drawings.

For example, when the DS3-class line level signal or line level line signal applied from the lower part is transmitted to the upper part, the controller 140 moves from the lower part to the first or second line interface parts 100 and 105. When each signal is input, whether the DS3 line signal applied through the management terminal device of the ATM switching system is transmitted by BYPASS or transmitted to each designated path by DEMULTIPLEXING. Information is applied to the first or second line interface unit (100, 105) and the first or second matching unit (110, 115).

The framer function of the first matching unit 110 and the second matching unit 115 separates the clock, data and frame synchronization bits from the line signal of the line level signal and outputs them in a synchronized state. The overhead of recording attributes such as a transmission destination or a waypoint and data to be actually transmitted is included. The overhead is analyzed by the controller 140 to distinguish between operation of a structured mode or an unstructured mode.

For example, when the signal applied from the lower part is a signal of an unstructured mode passing through, the controller 140 controls the corresponding first or second line interface unit 100 and 105 to control the corresponding DS3. The line signal of the high-level line level signal is input in a matching state, and the primary control signal is output to the corresponding first or second matching units 110 and 115 to operate in an unstructured mode. do.

As described above, the first or second matching units 110 and 115 operating in the unstructured mode under the control of the controller are connected to the corresponding first or second cell processing units 170, 175, 180, and 185 of the cell processing unit 160, respectively. ), And the corresponding first or second cell processing unit (170,175, 180, 185) receiving the DS3 level signal as described above can be received in the matching (MATCHING) state in the upper portion of the UTOPIA level 2. Outputs the current signal.

When operating in an unstructured mode under the control of the controller 140, the clock unit 190 applies a 38.88 MHz clock signal to the cell processor 160, and applies a 44.736 MHz clock signal to the first and second structures. A clock signal of 77.768 MHz is applied to the second matching units 110 and 115 and applied to the cell processing unit 160 to use as a cell processing unit network clock.

The clock unit 190 receives the clock signal of 19.44 MHz from the upper part, and outputs clock signals of 38.88 MHz, 37.056 MHz, 49.125 MHz, 44.736 MHz, and 77.768 MHz.

According to another example of the dual mode DS3 line subscriber matching device according to the present invention, a plurality of T-ones in which a signal applied to the first or second line interface units 100 and 105 from the lower portion is included in the DS3 ( In the case of a structure mode (MODE) in which a T1) or binary (E1) level signal is demultiplexed and must be transmitted in each path, the controller 140 may include a corresponding first or second line interface unit 100 or 105. By applying a control signal to the control signal), the line signal of the corresponding DS3 line level signal is input in a matching state and output to the corresponding first matching unit 110 or the second matching unit 115.

The first or second matching unit 110, 115 converts the line signal of the DS3-class line level signal into 28 T1 level signals or 21 binary E1 signals by primary control of the controller 140. Demultiplex and analyze the corresponding overhead (OVERHEAD) information of the demultiplexed signal.

The control unit 140 enters an unstructured mode through which 28 T-type (T1) level signals or 21 binary (E1) level signals, which are demultiplexed, pass through the T-one (T1) or binary (E1) class. Check whether it is in operation, 28 T1 (T1) level signals or 21 binary (E1) level signals by demultiplexing each channel (CH) to be transmitted to the corresponding path (PATH), and the corresponding control signal The secondary control signal is output to the first or second matching unit.

The first or second matching units 110 and 115 receiving the secondary control signal have an unstructured mode for passing 28 T-one (T1) signals or 21 binary (E1) signals via BYPASS. It is selected and operated in binary (E1) class and T-one (T1) class structure modes to separate or demultiplex into the corresponding channel.

At this time, the control unit 140 receives the clock signal of 49.125 MHz and 37.056 MHz output from the clock unit 190, divides into a common clock signal of 1.544 MHz and 2.048 MHz, respectively, in the divider unit to match the first matching unit ( It is applied or supplied to the 110, the second matching unit 115 and the cell processing unit 160, respectively.

In addition, the operation mode controller of the controller 140 receives a clock signal of 38.88 MHz output from the clock unit 190, generates a clock of 2.43 MHz, and applies or supplies the clock signal to the cell processor 160 to perform a cell processor. It is used as network clock of.

The first and second matching units 110 and 115 operate in a dual mode selected as a structure mode or an unstructured mode according to the control signal of the controller 140.

When the first and second matching units 110 and 115 are operated in the DS3 structure mode by the primary control of the controller 140, when the signal to be demultiplexed is a T-one (T1) class, the signals are separated into 28 signals. In the case of binary (E1) class, it is divided into 21 signals.

The cell processor 160 converts an applied signal into an AAL1 ATM cell signal and vice versa, and a first cell processor individually connected to the first matching unit 110 and the second matching unit 115, respectively. (170,175) and the second cell processing unit (180,185).

The first cell processing unit 170 and 175 and the second cell processing unit 180 and 185 receive up to 16 T-one (T1) or binary (E1) signals of each functional unit, and convert each signal into an ATM cell signal as described above. They are provided in two or two directions, respectively, and have a UTOPIA level 2 matching function. The ATM cell CELL signals are matched with UTOPIA level 2 signals to input and output.

The control unit 140 outputs a control signal to each function unit as described above through the monitoring control unit, and monitors the operation state of each function unit, and transmits and receives corresponding information by performing processor communication (IPC) with the upper unit through the interface unit. The corresponding operation information is stored in the memory 150 and output.

Under the control of the controller 140, the clock unit 190 applies a 38.88 MHz clock signal to the cell processor 160 in two modes, a structure mode or an unstructured mode. It is used as the system clock.

The cell processor 160 separates and transmits one piece of information into a plurality of ATM cells, and transmits and receives the plurality of ATM cells. The plurality of ATM cells are separated and recombined at the same time by being given a unique number by a SAR (SEGMENT ASSEMBLY REASSEMBLY) function. In addition, the necessary information is recorded in the 5-byte overhead of the ATM cell as SN (SEQUENCE NO) and SNP (SEQUENCE NO POINT), and the above operation information after being read and analyzed is recorded and stored in the memory 150. This processing is performed, and the information transmitted from the ATM cell is stored in the payload.

The clock used for the matching device in the structure mode has an SRTS function and a CAS function. In the SRTS function, a clock source of data applied from an external line becomes a master, and a system clock of a cell processor is a slave. Coding the difference between the clock recovered from the external line and the system clock of the cell processing unit, and the value is inputted to the CSI (CONVERSIONS SUBLAYER INDICATOR), which is the overhead of the ATM cell together with the odd sequence number. Send it.

The above is a T1 (T1) or binary (E1) UDF (UNSTRUCTURED DATA FORMAT), which accepts all transmitted data effectively and has a clock frequency of 2.43 MHz, which is less than twice that of 1.544 MHz and 2.048 MHz. Required as network clock.

In addition, the CAS function of the ATM cell payload (T1) 24 channels or T2 (E1) 30 channels in the SDF-MF (STRUCTURED DATA FOR MULTI FRAME) mode (MODE) valid only payload ( PAYLOAD) to configure the overhead, transmit the ABCD signal bits associated with each time slot, form a boundary of the structure in a multi-frame, and generated by dividing the clock received from the upper ATM network in the controller 140 In synchronization with CTCLK (COMMON TRANSMIT CLK) / CRCLK (COMMON RECEIVE CLK), signaling bits are transmitted from the framer function along with SERIAL DATA / FRAME PULSE.

Signals applied from the upper portion and transmitted to the lower portion are processed in the opposite direction to the above, and thus descriptions thereof will not be repeated.

According to the present invention having the above-described configuration, the controller 140 recognizes or demultiplexes the DS3 signal in the non-structural mode passing by BYPASS by using the information obtained through the operation terminal of the ATM exchange. Check whether the DS3 signal of the structure mode transmitted to the first mode, the first or second matching unit (110, 115) or the cell processing unit operating in the dual mode (DUAL MODE) structure mode or unstructured by the primary control and the secondary control It operates in one of the modes.

The present invention having the above-described configuration reduces the size of the equipment and reduces the power required by selectively operating in an unstructural mode for passing through a class 3 signal transmitted at high speed and a structure mode for demultiplexing and transmitting in a corresponding path. There is less industrial use.

In addition, since the structure mode and the unstructured mode are handled using one circuit board, there is an industrial use effect that the system is simple and easy to maintain.

Claims (4)

First and second line interface parts connected to a lower part which processes a signal of a circuit subscriber and input / output a third-class signal in a matched state by a corresponding control signal; First and second matching units respectively connected to the first and second line interface units and selectively inputting / outputting a line signal multiplexed, demultiplexed, routed, and framed by a corresponding control signal to a corresponding path; The line signal connected to and applied to the first and second matching units is converted into an A1 MT cell signal by a corresponding control signal, and is output to an upper portion as a Utopia level 2 signal and applied as a utopia level 2 signal from an upper portion. A cell processor for converting an AMT cell signal to be a line signal and outputting the converted AMT cell signal; And a class 3 dual mode circuit network matching device comprising a control unit for controlling and monitoring the respective functional units and communicating with the upper unit. According to claim 1, A memory for recording and storing the corresponding operation information of the controller and the cell processor; Asynchronous transmission mode switch DS3 dual mode circuit network matching device, further comprising a clock unit for processing the clock signal applied from the upper part and converting the signal into a plurality of clock signals, and applying the clock signal to each functional unit. . The method of claim 1, wherein the cell processing unit, A first cell processing part connected between the first matching part and an upper part; And a second cell processing unit connected between the second matching unit and the upper unit. The method of claim 3, wherein the first cell processing unit and the second cell processing unit, A class 3 dual-mode network matching device for asynchronous transmission mode switch, characterized in that each of the 16 T- or dual-level signal processing, consisting of a plurality.